Vaishali Semiconductor VS3V253QX, VS3V253Q, VS3V2253QX, VS3V2253Q Datasheet

Advance Information

VS3V253 / VS3V2253

High-speed 3.3V CMOS VSwitch

Dual 4:1 Mux/Demux

Applications

•= 3.3V to 2.5V translation

•= 2.5V to 1.8V translation

•= Hot-Swapping

General Description

The VS3V253 is a high-speed LVTTL–compatible dual 4:1 multiplexer/demultiplexer. The VS3V2253
contains two mux/dem ux channels with com mon path control ( S0 & S1) and individual active LOW enables

and /EB. The low ON res istance of VS3V253 allows inputs to be connected to outputs without adding

/E

A

propagation delay and without generating additional signal noise. The VS3V2253 has 25Ω resistors i n series
with the switches to reduce ground-bounce noise and signal reflections.

The VS3V253 and VS3V2253 mux/demux switches are designed for 3.3V to 2.5V, or 2.5V to 1.8V
translation, without any external components

. These switches also offer very high impedance between
switch terminals in the power off or ‘disabled’ state. This feature, combined with near-zero propagation
delay in the ‘on’ state, makes VS3V253 and VS3V2253 ideal interface elements for hot-swapping
applications.

Features

•= Enhanced N-FET with no DC path to VCC
or GND in normal operating signal voltage
range.

•= Low impedance switches connect inputs to
outputs with near-zero propagation delay:
5Ω (VS3V253) and 25Ω (VS3V2253)

•= Pin-compatible with 74LVC253 or
equivalent logic devices

•= Zero added ground bounce or signal noise

•= Logic replacement

•= Memory bank, video, and audio

switching

•= Break-before-make feature

•= Undershoot clamp diodes on all switch and

control pins

•= ESD rating >2000V (Human Body Model)
or >200V (Machine Model)

•= Latch-up current >100mA

•= Available in 150-mil wide QSOP package

Figure 1. Functional Block Diagram Figure 2. Pin Configuration

S0
S1

/E

A

/E

B

I0

A

I1

Y

A

Y

B

2000-11-28 Page 1 MDSS-0003-01

Vaishali Semic onductor  1300 White Oak s Road  Campbell  CA 95008  Ph. 408.377.6060  Fax [phone]

A

I2

A

I3

A

I0

B

I1

B

I2

B

I3

B

/E

I2
I1

GND

QSOP

1

A

S1

2

I3

3

A

4

A

5

A

I0

6

A

Y

7

A

8

(All Pins Top View)

16
15
14
13
12

11

10

9

V

CC

/E

B

S0
I3

B

I2

B

I1

B

I0

B

Y

B

VS3V253/VS3V2253 Advance Information
Table 1. Pin Description

Name I/O Description

IXA, IXB I/O Data Input or Output
S0, S1 I Select Input
/EA, /EB I Enable Input
YA - YB I/O Data Output or Input

Table 2. Function Table

Inputs Select Outputs Function

/EA /EB S1 S0 YA Y

H X X X Hi-Z X Disable A
X H X X X Hi-Z Disable B
L L L L I0A I0B S1-0 = 0
L L L H I1A I1B S1-0 = 1
L L H L I2A I2B S1-0 = 2
L L H H I3A I3B S1-0 = 3

B

Table 3. Absolute Maximum Ratings

Supply Voltage to Ground………………………….…..-0.5V to +4.6V
DC Switch Voltage VS……………………….………….-0.5V to +4.6V

DC Input Voltage VIN…………………………………...-0.5V to +4.6V
AC Input Voltage (Pulse Width < 20ns)……………….…………-3.0V
DC Output Sink Current per Switch Pin…………………...…..128 mA
Maximum Power Dissipation…………………………….…..0.5 Watts
Storage Temperature………………………………...-65oC to +150oC

Note ABSOLUTE MAXIMUM CONTINUOUS RATINGS are those values beyond which damage to the device may occur. Exposure

to these conditions or conditi ons beyond those indicated may adversely affect devic e reliabilit y. Correct functional operation
while operating in the absolute maximum rated conditions is not implied.

Table 4. Capacitance

TA = 25oC, f = 1 MHz, VIN = 0V, V

OUT

= 0V

QSOP

Pins Operation Typ Max Unit

Control Inputs 4 5 pF
VSwitch Channels Demux 5 7 pF

(Switch OFF) Mux 7 8 pF

Note Capacitance is guaranteed, but not production tested. Total capacitance of a path, when the switch i s closed, is the sum of the

switch terminal capac i tances.

2000-11-28 Page 2 MDSS-0003-01

Vaishali Semic onductor  1300 White Oak s Road  Campbell  CA 95008  Ph. 408.377.6060  Fax [phone]