V3 Semiconductor V96BMC-40LP, V96BMC-33LP Datasheet

V96BMC

Rev. D

HIGH PERFORMANCE BURST

DRAM CONTR O LLER

FOR i960Cx/Hx/Jx PROCESSORS

• Pin/Software compatible with earlier V96BMC.

• Direct interfaces to i960Cx/Hx/Jx processors.

• 3.3V DRAM interface support.

• Near SRAM perf orm an ce a chi ev e d with DRA M.

• Supports up to 512Mb of DRAM.

• Interleaved or non-interleaved operation.

• Supports symmetric and non-symmetric arrays. The V96BMC Revision D Burst DRAM Controller

is an enhanc ed v er sion of the pre vio us V96B MC with improved timing and provides dedicated Power and Ground rails to support the increasingly popular 3.3V DRAM modules. Timing parameters are also impr oved over the older versions of the de vi ce.

The V96BMC provides the DRAM access protocols, buffer signals, data multiplexer signals, and bus timing resources required to work with DRAM. By using the V96BMC, system designers can replace tedious design work, expensive FPGAs and valuable board space with a single, high-performance, easil configured device. The process or interface of the V96BMC implements the bus protocol of the i960Cx/Hx/Jx. The pin naming conventio n has been duplicated on the V96BMC; simply wire like-named pins together to create the interface.

The V96BMC supports a total DRAM memor subsystem size of 5 12M bytes. The array may be

• Software-configured operational parameters.

• Integrated Page Cache Management.

• 2Kbyte burst transaction support.

• On chip memory address multiplexer/drivers.

• Two 24-bit timers, 8-bit bus watch timer.

• Up to 40MHz operation.

• Low cost 132-pin PQFP package. organized as 1 or 2 leafs of 32-bits each.

Standard memory sizes of 256Kbit to 64Mbit devices are supp orted and 8, 16, and 32 -bit accesses are allowe d. The V96BMC takes advantage of Fast Page Mode or EDO DRAMs and row comparison logic to achieve static RAM performance using dynamic RAMs. Control signals required for optional external data path buffers/latches are also provided by the V96BMC. The V96BMC provides an 8-bi t bus watch timer to detect and recover from accesses to unpopulated memory regions.Two 24-bit counters/timers can supply an external interrupt signal at a constant frequency relative to the system cloc k. The V96B MC is pack aged in a low-cost 132- pin PQ FP pack age and is available in 25, 33, or 40 MHz versions.

This document contai ns the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V96BMC. Detailed functio nal information is contained in the User’s Manual.

i960Cx/Hx/Jx

CPU

VxxxEPC

LOCAL TO

PCI BRIDGE

V3 Semiconductor reserves the right to change the specifications of this product without notice. V96BMC and V96xPBC are trademarks of V3 Semiconductor. All other trademarks are the propert

V96BMC

MEMORY

CONTROL

PCI

PERIPHERAL

D R A M

PCI SLOT or EDGE CONNECTOR

ROM

TYPICAL APPLICATION

of their respective owners.

V96BMC Rev.D

V3 Semiconductor retains the rights to change documentation, specif ications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.

1.0 Product Codes

Table 1: Product Codes

Product Code Processor Bus Type Package Frequency

V96BMC-33LP i960Cx/Hx/Jx

V96BMC-40LP i960Cx/Hx/Jx

32-bit multiplexed /

demultiplexed

32-bit multiplexed /

demultiplexed

132-pin PQFP 33MHz

132-pin PQFP 40MHz

2.0 Pin Description and Pinout

Table 2 below lists the pin types found on the V96BMC. Table 3 describes the function of each pin on the V96BMC. Table 4 lists the pin s by pin n umber. Figure 1 shows the p inout for the 13 2-pin PQF P package and Figure 2 shows the mechanical dimensions of the package.

Table 2: Pin Types

Pin Type Description

I/O

I TTL input only pin

TTL I/O pin with 12 mA output drive

TTL Output pin with 12 mA output drive TTL Output pin with 12 mA output drive that can be

configured for either 5 volt or 3.3 volt signaling, These outputs can be configured for 3.3V operation by

12-3

connecting the Vcc3 power pins to a 3.3V power plan e (Vcc should always be connected to a 5V supply). Vcc3 can also be connected to the 5V plane if 5V signaling is desired.

Table 3: Signal Descriptions

Memory Interface Signals

V96BMC Rev.D

Signal Type

AA[11:0] AB[11:0]

RASA[3:0] RASB[3:0]

CASA[3:0] CASB[3:0]

MWEA MWEB

RFS/AUXT

Description

Leaf A and B row and column address, multiplexed on the same

12-3

pins. When non-interleaved operation is select ed, only address bus AA should be used.

Row Address Strobe. These strobes indicate the presence of a valid

12-3

row address on busses AA(B)[11:0]. These signals are to be connected one to each 32-bit lea f of memory.

12-3

Column Address Strobe. These strobes latch a column address from

AA(B)[11:0]. They are assigned one to each byte in a leaf. Memory Write Enable. These are the DRAM write strobes. One is

supplied for eac h leaf to minimize signal loading. Refresh in progress. This output is multi-function signal. The signal

name, as it appears on the logic symbol, is the default signal names.

This signal gives notice that a refresh cycle is to be executed. The timing leads RAS only refresh by one cycle. The output may also function as AUX timer interrupt.

Configuration

Signal Type R Description

HMODE

I Connected to Vcc (for i960Cx) or GND (for i960Hx/Jx).

Buffer Controls Signals

Signal Type R Description

Data Transmit A and B. These outputs are multi-function signals.

The signal names, as they appear on the logic symbol, are the TXA TXB

default signal names (Mode 0). The purpose of these outputs is to

control buffer output enables during data read transactions and, in

effect, control the multiplexing of data from each memory leaf onto

the i960Cx/Hx/Jx data bus.

These outputs are mode independent, however, the timing of the

signals chan ge for different operational m odes. They control transLEA LEB

parent latche s that hold data t ransmitted during a write transaction.

In modes 0 and 1, the latch controls follow the timing of CAS for

each leaf, while in modes 2 and 3 the timing of LEA and LEB is

shortened to 1/2 clock.

Local Bus Interfac e

V96BMC Rev.D

Table 3: Signal Descriptions (cont’d)

Signal Type R Description

A[31:2] I Local address bus.

Address Latch Enable: cont rols a set of transparent latches on the

address bus. When asserted high, the address input flows through ALE I

the latch. When ALE is low, the internal address holds the previous

value. With an i960Cx/Hx processor ALE is not typically used and

has an internal pull-up resistor that will keep it hi gh when not con-

nected (to provide backward pin compatibility with earlier versions).

D/C

I Data/Code.

BE[3:0] I L ocal bus byte write enables.

W/R IWrite/Read.

READY

Z Local Bus data ready.

ADS I Asserted low to indicate the beginning of a bus cycle

DEN I

SUP I

Data Enable. This input is monitored by the Bus Watch Timer to

detect a bus access not returning READY.

Indicates supervisor mode. Required for access to configuration reg-

isters.

BLAST I Burst last.

BTERM

BERR

Burst terminate. (this signal requires a nominal pull up resistor so

that the signal is deasserted when RESET goes inactive)

H Bus Time-out error.

Local interrupt request. This signal is asserted when the 24-bit

INT

counter reaches terminal count, and interrupt out is enabled. May

be programmed for pulse or level operation.

RESET I Local bus reset signal.

PCLK I Local bus clock.

ID[2:0] I These inputs select the address offset of the configuration registers.

Power and Ground Signals

Signal Type R Description

Vcc - POWER leads intended for external connection to a 5V Vcc plane Vcc3 - POWER for DRAM control outp uts . Ca n b e co nn ect e d to 3. 3V o r 5 V. GND - GROUND leads intended for external connection to a GND plane.

a. R indicates state during reset.

V96BMC Rev.D

Ta ble 4: Pin Assignments

PIN # Signal PIN # Signal PIN # Signal PIN # Signal

1 A14 34 ADS 2 A15 35 BE2 68 AA11 101 AB10 3 A16 36 BE3 69 Vcc3 102 AB11 4 Vcc 37 BTERM 70 GND 103 Vcc3 5 A17 38 READY 71 CASA 0 104 GND 6 A19 39 ID0 72 CASA1 105 CASB0 7 A20 40 ID1 73 CASA2 106 CASB1 8 A18 41 ID2 74 CASA3 107 CASB2

9 A21 42 RFS/AUXT 75 Vcc3 108 CASB3 10 A24 43 LEA 76 GND 109 Vcc3 11 A22 44 LEB 77 RASA0 110 GND 12 A23 45 TXA 78 R ASA 1 111 RASB0 13 A26 46 TXB 79 R ASA 2 112 RASB1 14 A25 47 Vcc 80 RASA3 113 RASB2

67 AA10 100 AB9

15 A27 48 GN D 81 Vcc3 114 RASB3 16 ALE 49 HMODE 82 MWEA 115 Vcc 17 - 50 - 83 - 116 18 - 51 - 84 - 117 19 A31 52 - 85 - 118 MWEB 20 A28 53 AA0 86 GND 119 GND 21 A29 54 AA1 87 AB0 120 RESET 22 A30 55 AA2 88 AB1 121 A2 23 D/C 56 AA3 89 AB2 122 A3 24 SUP 57 Vcc3 90 AB3 123 A4 25 PCLK 58 GND 91 Vcc3 124 A5 26 INT 59 AA4 92 GND 125 A6 27 BERR 60 AA5 93 AB4 126 A7

GND

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