V3 Semiconductor V360EPC-50, V360EPC-33 Datasheet

V360EPC Rev. A0 / A1

LOCAL BUS TO PCI BRIDGE

FOR DE-MULTIPLEXED A/D PROCESSORS

V3 Semiconductor reserves the right to change the specifications of this product without notice. V360EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.

• Glueless interface to i960Cx/Hx and AMD29030/40 processors

• Configurable for primary master, bus master or target operation.

• Type 0 and type 1 configuration cycles.

•Upto1KbyteburstaccessonPCIorlocal.

• Large, 640-byteFIFOs using V3’s unique

YNAMIC BANDWIDTH ALLOCATION™ architecture

• 64-byte read FIFO per aperture.

• Enhanced support for 8/16-bit local bus devices with programmable region sizes.

• 3.3 volt support

• Dual bi-directional address space remapping

• Fully compliant with PCI 2.1 specification

• On-the-fly byte order(endian) conversion

•I

O ATU and messaging unit including

hardware controlled circularqueues

• 2 channel DMA controller plus multiprocessor DMA chaining and demand mode DMA

• Hot swapping capability

• 16 8-bit bi-directionalmailboxregisters with doorbell interrupts

• Flexible PCI and local interrupt management

• Optional power-on serial EEPROM initialization

• 33MHz and 50MHz local bus versions

• Industrials Temperature Grade -40 to +85’C

• Low cost 160-pin EIAJPQFP package

V360EPC provides the highest performance, most fle xible, an d mos t economic al method to directly connect i960Cx/Hx or AMD2930/40 processors to the PCI bus. As a generic solution for 32-bit de-multiplexed local bus applications, V360EP C is also a suita ble ca ndid ate f or a variety of high -perfor mance applications based on Motorola, IBM, DEC and Hitachi embedded processors - where a minimal amount of glue logicis needed.

V360EPC is the second generation of V3’s I

O ready PCI bridges - fully backw ar d com patible with V962P BC and V292PBC Rev B2 devices and is su pporti ng pow erful fea tures l ike Ho t Swap and DMA ch aining. Th e PC I bu s can be run at full 33MHz, independent of local bus clock rate. The overall throughput of the system is dram at ically i m pr oved b y inc r e asing the FIF O

depths and utilizing the unique D

YNAMIC

BANDWIDTH ALLOCATION™ architecture.

Access to the PCI bus can be performed through two programmable address apertures. Two more aper tur es a re provided for PCI -to- loc al b us accesses. There are 64-bytes of read FIFOs in each direction, 3 2-b ytes d edi cate d for each aperture.

Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer engine for bulk data transfers. Ma ilbox regis ters and flex ible PCI interrupt controllers are also included to provide a simple mechanism to emulate PCI device control ports. The part is available in 160-pin low cost PQFP packages.

i960Cx/Hx

CPU

V96BMC

MEMORY

CONTROL

D R A M

ROM

V360EPC

LOCAL TO

PCI BRIDGE

TYPICALAPPLICATION

PERIPHERAL

PCI

PCI SLOT or EDGE CONNECTOR

V360EPC

This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V360EPC. Detailed functional information is contained in the User’s Manual.

V3 Semiconductor retains the rights to change documentation, specifications, or device functi ona li ty at any tim e wit h out no t ic e. Ple ase ve rif y tha t you ha ve th e late s t copy of all documents before finalizing a design.

1.0 Product Codes

2.0 Pin Description and Pinout

Table 2 below lists the pin types found on the V360EPC. Table 3 describes the function of each pin on the V360EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP packageand Figure 2 shows the mechanical dimensions of thepackage.

Table 1: Product Codes

Product Code Processors Bus Type Package Frequency

V360EPC-33

REV A0 / A1

i960Cx/Hx,

AMD29030/40

32-bit de-multiplexed 160-pin EIAJ PQFP 33MHz

V360EPC-50

REV A0 / A1

i960Cx/Hx,

AMD29030/40

32-bit de-multiplexed 160-pin EIAJ PQFP 50MHz

Table 2: Pin Types

Pin Type Description

PCI I PCI input only pin.

PCI O PCI output only pin.

PCI I/O PCI tri-state I/O pin.

PCI I/OD PCI input with open drain output.

I/O

TTL I/O pin with 4mA output drive.

I TTL input only pin.

TTL output pinwith 4mA outputdrive.

V360EPC

Table 3: S i gnal Descriptions

PCI Bus Interface

Signal Type R

Description

AD[31:0] PCI I/O Z Address and data, multiplexed on the same pins.

C/BE[3:0]

PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins.

PAR PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0]

FRAME

PCI I/O Z

Cycle Frame indicates the beginning and burst length of an access.

IRDY

PCI I/O Z

Initiator Readyindicates theinitiating agent’s (busmaster’s)ability to complete the current data phase of the transaction.

TRDY

PCI I/O Z

Target Readyindicates thetarget agent’s(selecteddevice’s) ability to complete the current data phase of the transaction.

STOP

PCI I/O Z

Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect).

DEVSEL

PCI I/O Z

DeviceSelect, when actively driven by a target,indicates the driving device has decoded its address as the target of the current access. As an inputto the initiator, DEVSEL

indicates whether

any device on the bus has been selected.

IDSEL PCI I

Initialization Device Selectis used as a chip selectduringconfiguration read and write transactions. It must be driven high in order to access the chip’s internal configuration space.

REQ

PCI O Z

Request indicates to the arbiter that this agent requests use of the bus.

GNT

PCI I

Grant indicates to the agent that access to the bus has been granted.

PCLK PCI I PCLK provides timing for all transactionson thePCI bus.

PRST

PCI I/O Z/L

Acts as an input when RDIR is high, an output when RDIR is low. As aninput it isasserted low to bringall internal EPC operation to a reset state.

PERR

PCI I/O Z

Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle.

SERR PCI I/OD Z

System Error is u sed to report address parity errors, data parity errors on the Special Cycle command, or any other system error where t he result will be catastrophic.

INT[A:D]

PCI I/OD Z Level-sensitive interruptrequests may be received or generated.

V360EPC

Local Bus Interface

Signal Type R Description

LD[31:0] ID[31:0]

I/O4 Z Local multiplexed addr ess and data bus.

LA[31:2] I/O4 Z Local address bus.

BE[3:0]

BWE[3:0]

I/O4 Z Local bus byte enables.

W/R

R/W

I/O4 Z Read-Write strobe.

ADS

LREQ

I/O4 Z Asserted low to indicate the beginning of a bus cycle.

READY

RDY

I/O4 Z Local Bus data ready

HOLD

LBREQ

O4 L

Local bus hold request: assertedby the chip to initiate a localbus mastercycle.

HOLDA

LBGRT

I Local bus hold acknowledge.

LPAR[3:0] I/O4 Z Localbus parity.

BLAST

BURST

I/O4 Z Burst lastc. Burst requestb.

BTERM

ERR

I/O4 Z Bus Time-out. Burst terminatec.

LINT

O4 H Localinterrupt request.

LRST

I/O4 L/Z Local bus RESET signal.

LCLK

MEMCLK

I Local bus clock.

Serial EEPROM Interface

Signal Type R Description

SCL/LPERR

O4 X EEPROM clock. Local parity error.

SDA I/O4 X EEPROM data.

Table 3: Signal Descriptions (cont’d)

V360EPC

2.1 Test Mode Pins

Several device pins are used during manufacturing test to put the V360EPC device into various test modes.These pinsmust be maintained at proper levels during reset to insure proper operation. Thisis typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signalpins if they are not guaranteedto be at theproper level during reset. Table4 below shows the reset statesfor test mode pins:

Configuration

Signal Type R Description

RDIR I

Resetdirection.TielowtodrivePRST

out and LRST in, high to

drive LRST

out and PRST in.

EN5V

Selects 5V (EN5V

driven low) or 3.3V (EN5V driven high) device

operationmodes.

Power and Ground Signals

Signal Type R Description

POWER leads intended for external connection to a V

board

plane.

GND -

GROUND leads intended for external connection to a GND board plane.

a. R indicates state during reset. b. Applies to AMD29030/40 mode. c. Applies to i960Cx/Hx mode.

Ta ble 4: RESET State for Test M ode Pins

Mode Pin 134 Pin 135 Pin 153

i960Cx/Hx Pull-Up Pull-Up Pull-Up

AMD2930/40 Pull-Down Pull-Up Pull-Up

Table 3: Signal Descriptions (cont’d)

V360EPC

Table 5: Pin Assignments

PIN # Signal PIN # Signal PIN # Signal PIN # Signal

41 V

81 V

121 V

2INTD42 AD14 82 LA23 122 LA6 3PRST

43 AD13 83 LD8/ID8 123 LD25/ID25 4 PCLK44AD1284LA22124LA5 5GNT

45 AD11 85 LD9/ID9 125 LD26/ID26 6REQ

46 AD10 86 LA21 126 LA4 7 AD31 47 AD9 87 LD10/ID10 127 LD27/ID27 8 AD30 48 AD8 88 LA20 128 LA3 9 AD29 49 C/BE0

89 LD11/ID11 129 LD28/ID28

10 AD28 50 V

90 LA19 130 LA2 11 GND 51 GND 91 LD12/ID12 131 LD29/ID29 12 AD27 52 AD7 92 LA18 132 LD30/ID30 13 AD26 53 AD6 93 LD13/ID13 133 LD31/ID31

14 AD25 54 AD5 94 LA17 134

'1'

’0’

15 AD24 55 AD4 95 LD14/ID14 135

BTERM

ERR

16 C/BE3 56 AD3 96 LA16 136

READY

RDY

17 IDSEL 57 AD2 97 LD15/ID15 137

HOLD

LBREQ

18 AD23 58 AD1 98 LA15 138

HOLDA

LBGNT

19 AD22 59 AD0 99 LD16/ID16 139

ADS

LREQ

20 V

60 V

100 V

140 V

21 GND 61 GND 101 GND 141 GND

22 AD21 62 LD0/ID0 102 LA14 142

LCLK

MEMCLK

+ 12 hidden pages