V3 Semiconductor V320USC-75REVB1 Datasheet

Datasheet

V3 Semiconductor Corp.

2348G W alsh Avenue

Santa Clara, CA 95051

Phone (408) 988-1050, Fax (408) 988-2601

Toll Free (800) 488-8410 (US and Canada)

http://www.vcubed.com

• Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus

• Fully compliant with PCI 2.2 speciﬁcation

• Conﬁgurable for primary master, bus master, or target operation

• SDRAM controller with support for Enhanced SDRAM

• Up to 1 Kbyte burst access to (E)SDRAM from PCI, 32 bytes from local processor (MIPS mode)

• 640 bytes of on-chip FIFO storage with

Dynamic

Bandwidth Allocation™ architecture

• On-the-ﬂy byte order (endian) conversion

• I

O Ready™ ATU and messaging unit

• Programmable chip select / peripheral device strobe generation

• Hot Swap Ready (PICMG™ Hot Swap Speciﬁcation 2.1)

• Implementation of PCI Bus Pow er Management Interf ace Speciﬁcation V ersion 1.0

• 3.3V operation with 5V tolerant inputs

• 208-pin PQFP package

• Up to 75 MHz local bus clock with separate asynchronous PCI clock up to 50 MHz

• Two 32-bit timers

• Initialization through local processor, PCI or serial EEPROM

Typical Application

V320USC Universal System Controller

PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

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V320USC Datasheet

Introduction

1.0 Introduction

The V320USC Universal System Controller simplifies the design of systems based on MIPS and SuperH microprocessors by replacing many lower integration support components with a single, high-integration device. This saves design time, board area, and manufacturing cost.

The I

O Ready V320USC from V3 Semiconductor is a high performance PCI bridge with integrated SDRAM controller for MIPS processors operating at up to 75 MHz bus speed. It features address translation capabilities and large on-chip buffers. A separate peripheral bus provides low latency access to SDRAM. The peripheral controller on the V320USC also performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals.

The integrated SDRAM Controller connects the processor as well as the PCI bus through on-chip FIFOs to SDRAM arrays of up to 1 Gbytes in size. The fully programmable SDRAM controller also supports the use of Enhanced SDRAM to achieve even greater performance. Burst accesses of up to 1 Kbytes from PCI and 32 bytes from the MIPS

processor are

supported. The two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes

such as retriggerable or one-shot. The bus watch timer (MIPS mode) prevents system hangs during accesses to undecoded regions. Interrupts for a real time OS can be easily generated by the system heartbeat timer. A watchdog timer is also provided for graceful recovery from catastrophic program failures. Interrupt requests for all on-chip peripherals are managed by the Interrupt Control Unit. Additionally, off-chip interrupts can be routed to the Interrupt Control Unit.

The V320USC is packaged in a low-cost 208-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 75 MHz speed grade (MIPS mode), 66 MHz (SH mode).

This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V320USC. Detailed functional information is contained in the User’s Manual.

1.1 Listing of Figures

Figure 1: Pinout for 208-pin EIAJ PQFP in MIPS Mode (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2: Pinout for 208-pin EIAJ PQFP in SH3/4 Mode (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3: 208-pin EIAJ PQFP mechanical details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4: Clock and Synchronous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5: ALE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6: Serial EEPROM Waveforms and Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.2 Listing of Tables

Table 1: Product Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 2: Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 3: Signal Description—PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 4: Signal Description—Local Bus Interface, MIPS™ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 5: Signal Description—Local Bus Interface, SH3/4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 6: Signal Description—DRAM and Peripheral Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 7: Signal Description—Mode and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 8: Signal Description—Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 9: Signal Description—Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 10: Pin Assignments for MIPS™ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

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V320USC Datasheet

Product Code

Table 11: Pin Assignments for SH3/4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13: Guaranteed Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14: DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15: PCI Bus Signals DC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 16: Local Bus/M Bus Signals DC Operating Specifications (VCC = 3.3V+ 0.3V) . . . . . . . . . . 17

Table 17: PCI Bus Signals AC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 18: Local and M Bus AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 19: M Bus AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 20: Capacitive Derating for Output and I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 21: Local Bus/M-Bus Timing Parameters for Vcc =3.3 Volts +/- 5% . . . . . . . . . . . . . . . . . . . . 19

Table 22: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10% . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 23: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

V3 Semiconductor retains the rights to change documentation, speciﬁcations, or

device functionality at any time without notice. Please verify that you have the latest copy

of all documents before ﬁnalizing a design.

2.0 Product Code

3.0 Pin Description

Table 2 lists the pin types found on the V320USC.

Table 1: Product Code

Product Code

Processors Package Frequency

V320USC-75 REV B1

MIPS (32-bit bus), SH3,

SH4 (32-bit bus)

208-pin EIAJ PQFP

75MHz

(66 MHz SH)

Table 2: Pin Types

Pin Type

Description

PCI I PCI input only pin.

PCI O PCI output only pin.

PCI I/O PCI tri-state I/O pin.

PCI I/OD PCI input with open drain output.

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V320USC Datasheet

Pin Description

3.1 Signal Description

The following tables describe the function of each pin on the V320USC.

I/O

TTL I/O pins with 2/8/12 mA drive

I TTL input only pin.

TTL output pins with 2/8/12 mA drive

Table 3: Signal Description—PCI Bus Interface

Signal

Type R

Description

AD[31:0] PCI I/O Z Address and data, multiplexed on the same pins.

C/BE[3:0]

PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins.

PAR PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0].

FRAME PCI I/O Z

Cycle Frame indicates the beginning and burst length of an access.

IRDY PCI I/O Z

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction.

TRDY PCI I/O Z

Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction.

STOP PCI I/O Z

Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect).

DEVSEL PCI I/O Z

Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected.

IDSEL PCI I

Initialization Device Select is used as a chip select during conﬁguration read and write transactions. It must be driven high in order to access the chip’s internal conﬁguration space.

PERR

PCI I/O Z

Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle.

Table 2: Pin Types

Pin Type

Description

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V320USC Datasheet

Pin Description

SERR

PCI I/OD Z

System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic.

REQ PCI O Z

Request indicates to the arbiter that this agent requests use of the bus.

GNT

PCI I

Grant indicates to the agent that access to the bus has been granted.

PCLK PCI I PCLK provides timing for all transactions on the PCI bus.

a. R indicates state during reset.

Table 4: Signal Description—Local Bus Interface, MIPS™ Mode

Signal

Type R Description

SYSAD[31:0] I/O Z System Address / Data (multiplexed)

SYSCMD[8:0] I/O Z

System Command / data identiﬁer. When MODE0 = ‘0’, SYSCMD[8:5] should be pulled high.

VALIDIN O

Valid command or data from external agent. This signal should have an external pull-up resistor.

ALIDOUT I Valid command or data from MIPS™

RELEASE I Release the system interface to slave state

WRRDY O

Z Write Ready: this signal should have an external pull-up resistor.

LCLK I Local clock

Table 5: Signal Description—Local Bus Interface, SH3/4 Mode

Signal Type R Description

A[31:26]/

CS[5:0]

I/O

Upper System Address

A[25:0] I/O

Z Lower System Address

D[31:0] I/O

Z Data Bus

RD/WR

I/O

Z Read/not Write. This is also referred to as MWE

for SDRAM

Table 3: Signal Description—PCI Bus Interface

Signal

Type R

Description

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V320USC Datasheet

Pin Description

I Bus Cycle Start

WAIT/RDY O

Z Bus Wait

RBE_EN

Enable Read Byte Enables: When active (‘0’), PCI byte lane enables are derived from RBE

[3:0] for a local-to-PCI read access.

RBE

[3:0]

Read Byte Enables: provides the byte enable pattern for local-toPCI read access when RBE_EN

is active. Byte enables for writes

are derived from the DQM

[3:0] signals.

BREQ

Bus Request Output: indicates that the V320USC wants to perform a bus cycle on the local bus

CK I

Bus Acknowledge: asserted to allow the V320USC to take ownership of the local bus.

BREQ_IN

Bus Request Input: assertion of this input will cause the V320USC to give up ownership of the local bus at the end of the current burst/single cycle so that a higher priority master can take ownership. Typically connected to IRQ_OUT

LCLK I

Local clock. This would be connected to either CKIO on the processor or a clock driver which provides a clock with the same phase relationship as CKIO. See V3 Reference Designs for further details.

a.Not available in revision B0 silicon b.Not available in revision B0 silicon c.Not available in revision B0 silicon

Table 6: Signal Description—DRAM and Peripheral Bus Interface

Signal Type R Description

MA[14:0] O

SDRAM Memory Address (also, A[16:2] for peripheral access). MA[14:13] are typically used for BA[1:0]

DCS

[3:0] O

SDRAM Chip Select. This should be connected to the CS inputs of SDRAM chips or DIMM devices.

DQM[3:0] I/O

SDRAM Data Mask (these act as MBE[3:0], A[1:0] for peripheral access)

RAS

Z SDRAM Row Address Strobe

CAS

Z SDRAM Column Address Strobe

MWE

Z SDRAM Memory Write Enable

Table 5: Signal Description—Local Bus Interface, SH3/4 Mode

Signal

Type R Description

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V320USC Datasheet

Pin Description

MAD[31:0] I/O

SDRAM and peripheral bus data. MAD[31:0] is known as D[31:0] when in SH3/4 mode.

SDA I/OD

Z Serial EEPROM Data

SCL O

Z Serial EEPROM Clock

IOC[11:0] I/O

Z Multi-purpose I/O that can be conﬁgured for many functions

INT

[3:0] PCI I/OD Z

General purpose interrupt inputs/outputs: may be used for either PCI or local processor interrupts

Table 7: Signal Description—Mode and Reset

Signal

Type R Description

RSTIN I

Reset Input: Active low reset input used to initialize all internal functions of the chip.

RSTOUT O

Reset Output: Driven activ e when the input reset is driv en activ e. Driven inactive when the RST OUT bit in the system register is set. The RST

OUT signal is synchronous to the rising edge of LCLK.

CH I

PCI Precharge Bias: This signal is driven low to activate the onchip precharge bias for use in PICMG Hot Swap applications. Non-Hot Swap applications should pull this signal high.

MODE2:1

MODE0

I/O

MODE Input: selects the CPU mode

‘H’ - Tie High with a weak pull up of 4.7–10K Ω ‘L’ - Tie Low with a weak pull down of 4.7–10K Ω

Table 6: Signal Description—DRAM and Peripheral Bus Interface

Signal

Type R Description

MODE

2 1 0 Description

Pin 55 Pin 54 Pin 202

SYSCMD7 SYSCMD8 ‘H’ MIPS with 9 bit SYSCMD

‘H’ ‘H’ ‘L’ MIPS with 5 bit SYSCMD ‘H’ ‘L’ ‘L’ SH3

‘L’ ‘L’ ‘L’ SH4

others reserved

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V3 Semiconductor V320USC-75REVB1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual