Datasheet UT62L6416MC-70LLE, UT62L6416MC-70LL, UT62L6416MC-70L, UT62L6416MC-70LE, UT62L6416MC-55LLE Datasheet (UTRON)

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A

A

A

A0 A1 A2 A3 A4 A8 A

A

A

A

UTRON

Preliminary Rev. 0.1

FEATURES

Fast access time :



55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V

CMOS Low operating power



Operating current: 45/35/25mA (Icc max)

Standby current: 20 uA(TYP.) L-version

3 uA(TYP.) LL-version

Single 2.7V~3.6V power supply

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Operating temperature:



Commercial : 0℃~70℃
Extended : -20℃~80℃

All inputs and outputs TTL compatible

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Fully static operation

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Three state outputs



Data retention voltage: 1.5V (min)

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Data byte control :



Package : 44-pin 400mil TSOPⅡ



48-pin 6mm × 8mm TFBGA

LB

UB

(I/O1~I/O8)

(I/O9~I/O16)

FUNCTIONAL BLOCK DIAGRAM

.

MEMORY ARRAY

1024 Rows x 64 Columns x 16 bits

.

. .

COLUMN I/O

12

13

14

15

I/O1

.

.

I/O16

DECODER

. . .

CONTROL

ROW

I/O

.

.

.
.
.

UT62L6416

64K X 16 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The UT62L6416 is a 1,048,576-bit low power
CMOS static random access memory organized
as 65,536 words by 16 bits.

The UT62L6416 operates from a single 2.7V ~

3.6V power supply and all inputs and outputs are
fully TTL compatible.

The UT62L6416 is design for upper and low byte
access by data byte control(

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A15 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs

CE

WE

OE

LB

UB
VCC Power Supply
VSS Ground
NC No Connection

VCC

VSS

UB

Chip Enable Input

Write Enable Input

Output Enable Input

Lower-Byte Control

High-Byte Control

LB

).

11

10

COLUMN DECODER

A9

A7 A6

5

CE

WE

OE

LB

UB

LOGIC

CONTROL

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T

UTRON

Preliminary Rev. 0.1

PIN CONFIGURATION

A4
A3

A2

A1

A0

CE

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

WE

A15

A14
A13

A12

NC

1

2
3

4

5
6

7

8

9

10

11

12

13

14

15

16
17

18

19
20

21

22 23

UT62L6416

64K X 16 BIT LOW POWER CMOS SRAM

44

43
42

41

40

39

38
37

36

35

34

33
32

31

30

29

28
27

26

25

24

A5

A6

A7

OE

UB

LB

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

NC

A8

A9

A10

A11

NC

A

B

C

D

E

F

G

H

LB

OE

I/O9

UB

I/O11I/O10

I/O12

Vss

I/O13

Vcc

I/O15 I/O14

I/O16

NC

NC

A8

123456

UT62L6416

A0

A3

A5

NC

A14

A12

A9

TFBGA

A1

A4

A6

A7

NC I/O5

A15 I/O6

A13

A10

A2

CE

I/O4NC

WE

A11

NC

I/O1

I/O3I/O2

Vcc

Vss

I/O7

I/O8

NC

TSOP II

TRUTH TABLE

MODE

Output
Disable
Read L

Write L

Note: H = VIH, L=VIL, X = Don't care.

CE

OE

H X X X X High – Z High – Z ISB, I
X X X H H High – Z High – Z I
L
L

H
H

L
L
L

L

L

X
L
L

X

X

WE

LB

UB

H
H
H
H
H

L
L
L

L
X
L

H

L
L

H

L

X L High – Z

H
L
L
H
L
L

I/O OPERATION

I/O1-I/O8 I/O9-I/O16

High – Z

High – Z

D

OUT

High – Z
D

OUT

DIN
High – Z
D

IN

High – Z
High – Z
D

OUT

D

OUT

High – Z
D

IN

DIN

SUPPLY CURREN

Standby

SB1

, I

SB

SB1

ICC,I

CC1,ICC2

I

CC,ICC1,ICC2

I

CC,ICC1,ICC2

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UTRON

Preliminary Rev. 1.0

ABSOLUTE MAXIMUM RATINGS

64K X 16 BIT LOW POWER CMOS SRAM

*

UT62L6416

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V
Operating Temperature

Commercial T
Extended T

Storage Temperature T

-0.5 to 4.6 V

TERM

A

A

-65 to +150

STG

0 to 70

-20 to 80

℃
℃
℃

Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 secs) Tsolder 260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.

50 mA

OUT

℃

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V, TA = 0℃ to 70℃ / -20℃ to 80℃(E))

PARAMETER

SYMBOL

Power Voltage VCC 2.7 3.0 3.6 V
Input High Voltage VIH 2.2 - VCC+0.3 V
Input Low Voltage VIL -0.2 - 0.6 V
Input Leakage Current ILI

Output Leakage Current ILO

Output High Voltage VOH IOH= -1mA 2.2 - - V
Output Low Voltage VOL IOL= 2 mA - - 0.4 V
Operating Power

ICC Cycle time=min, 100%duty,

Supply Current

Icc1

Current

Icc2

Standby Current (TTL) ISB

Standby Current (CMOS) -L - 20 80

I

SB

TEST CONDITION MIN. TYP. MAX. UNIT

V

≦VIN ≦VCC

SS

V

≦V

SS

I/O

≦V

Output Disabled

CC;

- 1 - 1

- 1 - 1

55 - 30 45 mA

I/O=0mA,

CE

=V

;

IL

70 - 25 35 mA

100 - 20 25 mA

Cycle time=1µs,100%duty,I/O=0mA,

≦

0.2V,other pins at 0.2V or Vcc-0.2V,

CE

Cycle time=500ns,100%duty,I/O=0mA,

≦

0.2V,other pins at 0.2V or Vcc-0.2V,

CE

=V

1

1.

2.

1.

CE

UB

CE

other pins =VIL or VIH,

IH,

=

= V

other pins =VIL or VIH,

IH,

-0.2V,

=V

LB

CC

4 5 mA Average Operation

-

8 10 mA

-

- 0.3 0.5 mA

other pins at 0.2V or Vcc-0.2V,

2.

UB

=

=VCC-0.2V,

LB

-LL - 3 25

other pins at 0.2V or Vcc-0.2V,

A

µ

A

µ

A

µ

A

µ

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UTRON

Preliminary Rev. 1.0

CAPACITANCE

(TA=25℃, f=1.0MHz)

64K X 16 BIT LOW POWER CMOS SRAM

UT62L6416

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C
Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

IN

I/O

-

-

6 pF
8 pF

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA / 2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER SYMBOL UT62L6416-55 UT62L6416-70 UT62L6416-100

Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change

,UB

LB

LB

LB

Access Time

,UB

to High-Z Output

,UB

to Low-Z Output

(2) WRITE CYCLE

PARAMETER SYMBOL UT62L6416-55 UT62L6416-70 UT62L6416-100

Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z

,UB

LB

*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V

Valid to End of Write

MIN. MAX. MIN. MAX. MIN. MAX.

tRC 55 - 70 - 100 - ns
tAA - 55 - 70 - 100 ns
t

- 55 - 70 - 100 ns

ACE

tOE - 30 - 35 - 50 ns
t

10 - 10 - 10 - ns

CLZ*

t

5 - 5 - 5 - ns

OLZ*

t

- 20 - 25 - 30 ns

CHZ*

t

- 20 - 25 - 30 ns

OHZ*

tOH 5 - 5 - 5 - ns
tBA - 55 - 70 - 100 ns

t

- 25 - 30 - 40 ns

BHZ

t

0 - 0 - 0 - ns

BLZ

MIN. MAX. MIN. MAX. MIN. MAX.

tWC 55 - 70 - 100 - ns
tAW 50 - 60 - 80 - ns
tCW 50 - 60 - 80 - ns
tAS 0 - 0 - 0 - ns
tWP 45 - 55 - 70 - ns
tWR 0 - 0 - 0 - ns
tDW 25 - 30 - 40 - ns
tDH 0 - 0 - 0 - ns
t

5 - 5 - 5 - ns

OW*

t

- 30 - 30 - 40 ns

WHZ*

tBW 45 - 60 - 80 - ns

(VCC =2.7V~3.6V, TA =0℃ to 70℃ / -20℃ to 80℃(E))

UNIT

UNIT

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UTRON

Preliminary Rev. 1.0

TIMING WAVEFORMS

64K X 16 BIT LOW POWER CMOS SRAM

READ CYCLE 1

(Address Controlled)

Address

t

OH

DOUT Data Valid

READ CYCLE 2

(CE and

OE

(1,2,4)

t

AA

Controlled)

t

RC

(1,3,5,6)

t

RC

UT62L6416

t

OH

Address

t

AA

t

CE

ACE

OE

LB , UB

t

CLZ

Dout

HIGH-Z

Notes :

1.

2. Device is continuously selected

3. Address must be valid prior to or coincident with

4.

5. t

6. At any given temperature and voltage condition, t

is HIGH for read cycle.

WE

is LOW.

OE

, t

, t

CLZ

OLZ

CHZ

, t

OHZ, tBHZ

and t

=V

IL.

CE

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

BLZ

t

OE

t

OLZ

t

BLZ

t

BA

transition; otherwise t

CE

is less than t

CHZ

CLZ

, t

OHZ

t

OHZ

t

BHZ

t

OH

Data Valid

is the limiting parameter.

AA

is less than t

OLZ.

, t

BHZ

t

CHZ

is less than t

BLZ.

HIGH-Z

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UTRON

Preliminary Rev. 1.0

WRITE CYCLE 1

(

Address

CE

WE

LB , UB

Dout

Din

WRITE CYCLE 2

(

WE

CE

Controlled)

Controlled)

(1,2,3,5)

AS

t

(1,2,5)

UT62L6416

64K X 16 BIT LOW POWER CMOS SRAM

t

WC

t

AW

t

CW

t

WP

t

BW

t

WHZ

(4) (4)

WC

t

High-Z

t

DW

Data Valid

t

WR

t

OW

t

DH

Address

AW

t

CE

AS

t

WE

LB , UB

WHZ

t

Dout

Din

Notes :

1.

2. A write occurs during the overlap of of

3. During a

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

6. t

or

WE

and data to be placed on the bus.

state.

OW

must be HIGH during all address transitions.

CE

＝

low ,

CE

controlled with write cycle with

WE

LOW transition occurs simultaneously with or after

CE

and t

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

WHZ

OE

CW

t

WP

t

BW

t

＝

WE

LOW, t

High-Z

and/or

low ,

LB

must be greater than t

WP

LOW transition, the outputs remain in a high impedance

WE

UB

t

DW

＝

Data Valid

low..

WHZ+tDW

WR

t

DH

t

to allow the drivers to turn off

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Preliminary Rev. 1.0

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time
Recovery Time

V

I

DR

t

CDR

t

R

DR

≧ V

CE

Vcc=1.5V

≧ V

CE
See Data Retention 0 - - ms
Waveforms (below)

DATA RETENTION WAVEFORM

VCC

CE

V

SS

2.7V

t

CDR

Data Retention Mode

V

DR

CE ≧ V

UT62L6416

64K X 16 BIT LOW POWER CMOS SRAM

(TA =

-0.2V

CC

-0.2V

CC

≧ 1.5V

-0.2V

CC

0℃ to 70℃ / -20℃ to 80℃(E)

1.5 - 3.6 V

- L - 1 50

- LL - 0.5 20

5 - - ms

2.7V

t

R

)

A

µ

A

µ

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UTRON

Preliminary Rev. 1.0

64K X 16 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

44 pin 400mil TSOP-Ⅱ PACKAGE OUTLINE DIMENSION

UT62L6416

θ

SYMBOLS

A 1.00 - 1.20 0.039 - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041

b 0.30 0.35 0.45 0.012 0.014 0.018

c 0.12 - 0.21 0.0047 - 0.083
D 18.313 18.415 18.517 0.721 0.725 0.728
E 11.854 11.836 11.838 0.460 0.466 0.470

E1 10.058 10.180 10.282 0.398 0.400 0.404

e - 0.800 - - 0.0315 ­L 0.40 0.50 0.60 0.0157 0.020 0.0236

2D - 0.805 - - 0.0317 -

y 0.00 - 0.076 0.000 - 0.003

Θ

DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS

MIN NOM MAX. MIN. NOM. MAX.

o

0

- 5o 0

o

- 5o

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UTRON

Preliminary Rev. 1.0

48 pin 6mm×8mm TFBGA PACKAGE OUTLINE DIMENSION

64K X 16 BIT LOW POWER CMOS SRAM

UT62L6416

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UTRON

Preliminary Rev. 1.0

64K X 16 BIT LOW POWER CMOS SRAM

UT62L6416

ORDERING INFORMATION

COMMERCIAL TEMPERATURE

PART NO. ACCESS TIME

(ns)

UT62L6416MC-55L 55 20
UT62L6416MC-55LL 55 3
UT62L6416MC-70L 70 20
UT62L6416MC-70LL 70 3
UT62L6416BS-55L 55 20 48 PIN TFBGA

UT62L6416BS-55LL 55 3 48 PIN TFBGA
UT62L6416BS-70L 70 20 48 PIN TFBGA
UT62L6416BS-70LL 70 3 48 PIN TFBGA

EXTENDED TEMPERATURE

PART NO. ACCESS TIME

(ns)

UT62L6416MC-55LE 55 20
UT62L6416MC-55LLE 55 3
UT62L6416MC-70LE 70 20
UT62L6416MC-70LLE 70 3
UT62L6416BS-55LE 55 20 48 PIN TFBGA

UT62L6416BS-55LLE 55 3 48 PIN TFBGA
UT62L6416BS-70LE 70 20 48 PIN TFBGA
UT62L6416BS-70LLE 70 3 48 PIN TFBGA

STANDBY CURRENT

(µA) TYP.

STANDBY CURRENT

(µA) TYP.

PACKAGE

44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ

PACKAGE

44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ
44 PIN TSOP-Ⅱ

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UTRON

Preliminary Rev. 1.0

64K X 16 BIT LOW POWER CMOS SRAM

UT62L6416

REVISION HISTORY

REVISION DESCRIPTION DATE

Preliminary Rev. 0.1 Original. Sep 5, 2001

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UTRON

Preliminary Rev. 1.0

THIS PAGE IS LEFT BLANK INTENTIONALLY.

64K X 16 BIT LOW POWER CMOS SRAM

UT62L6416

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