UTRON UT62L2568LS-70LLI, UT62L2568LS-70LI, UT62L2568LS-55LLI, UT62L2568LS-55LI, UT62L2568LC-70LLI Datasheet
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UTRON
UT62L2568(I)
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80082
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Fast access time :
55ns(max.) for Vcc=2.7V~3.6V
70ns(max.) for Vcc=2.5V~3.6V
CMOS Low operating power
Operating : 40/25mA (Icc max.)
Standby : T
A
=0℃~50℃
20 uA(max.) L -version
3 uA(max.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Industrial : -40℃~85℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Package : 32-pin 8mm x 20mm TSOP-
Ⅰ
32-pin 8mm x 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
GENERAL DESCRIPTION
The UT62L2568 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62L2568 is designed for very low power
system applications. It is particularly well suited for
battery back-up nonvolatile memory applications.
It operates from a wide range of 2.5V~ 3.6V supply
voltage. Easy memory expansion is provided by
using two chip enable input (
1CE
,CE2). And all
inputs and three-state outputs are fully TTL
compatible.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
256K ×8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A17
Vcc
Vss
I/O1-I/O8
CE2
CE1
UTRON
UT62L2568(I)
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80082
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
PIN CONFIGURATION
OE
WE
A12
A11
A13
NC
A17
A10 A14
A15
I/O6
I/O7
I/O8
A9
Vss
A8
A16
I/O5
Vcc
Vcc
I/O4
Vss
A7
A0
I/O3
I/O2
I/O1
NC
A6
A1
A3
A5
A4
A2
123456
H
G
C
D
E
F
A
B
TFBGA
CE2
CE1
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT62L2568
TSOP-1 / STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
1CE
CE2
A17
A15
32
31
30
29
A16
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
1CE
,CE2
Chip Enable Inputs
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
UTRON
UT62L2568(I)
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80082
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
TRUTH TABLE
MODE
1CE
CE2
OE
WE
I/O OPERATION SUPPLY CURRENT
H X X X High - Z
I
SB
,
I
SB1 , ISB2
Standby
X L X X High -Z
I
SB
,
I
SB1
, I
SB2
Output Disable L H H H High - Z I
CC ,
Icc1 , Icc2
Read L H L H
D
OUT
I
CC,
Icc1 , Icc2
Write L H X L
D
IN
I
CC,
Icc1 , Icc2
Note: H = VIH, L=VIL, X = Don't care.
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM
-0.5 to Vcc+0.3V V
Operating Temperature Industrial T
A
-40 to 85
℃
Storage Temperature T
STG
-65 to 150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 secs) Tsolder 260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.5V~3.6V, TA = -40℃ to 85℃)
PARAMETER
SYMBOL
TEST CONDITION MIN. TYP. MAX. UNIT
Power Voltage Vcc 2.5 3.0 3.6 V
Input High Voltage VIH 2.2 - Vcc+0.3 V
Input Low Voltage VIL - 0.3 - 0.6 V
Input Leakage Current ILI
V
SS
≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current ILO
V
SS
≦V
I/O
≦V
CC,
Output Disabled
- 1 - 1
µ
A
Output High Voltage VOH IOH= - 1mA 2.2 - - V
Output Low Voltage VOL IOL= 2.1mA - - 0.4 V
55 - 25 40 mA
ICC
Cycle time=Min.100% duty,
1CE
=V
IL
, CE2 = VIH, I
I/O
=0mA
70
- 15 25 mA
Icc1
Cycle time = 1µs,100% duty,
1CE
≦
0.2V,CE2≧V
CC
-0.2V, I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
- 4 5 mA
Operating Current
Icc
2
Cycle time =500ns,100% duty,
1CE
≦
0.2V,CE2≧V
CC
-0.2V, I
I/O=
0mA,
other pins at 0.2V or Vcc-0.2V,
- 8 10 mA
Standby Current (TTL) ISB
1CE
=V
IH
or CE2 = VIL
- 0.3 0.5 mA
-L - - 20 µA
I
SB1
1CE
≧
V
CC
-0.2V or .CE2≦0.2V,
other pins at 0.2V or Vcc-0.2V,
T
A
=0℃~50℃
-LL - - 3 µA
-L - - 80 µA
Standby Current (CMOS)
I
SB2
1CE
≧
V
CC
-0.2V or .CE2≦0.2V,
other pins at 0.2V or Vcc-0.2V,
T
A
= - 40℃~85℃
-LL - - 10 µA
UTRON
UT62L2568(I)
Preliminary Rev. 0.1
256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80082
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
IN
-
6 pF
Input/Output Capacitance C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF+1TTL, IOH= -1mA, IOL= 2.1mA
AC ELECTRICAL CHARACTERISTICS
( TA = - 40℃ to 85℃)
(1) READ CYCLE
UT62L2568-55
V
CC
= 2.7V~3.6V
UT62L2568-70
VCC = 2.5V~3.6V
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
tRC 55 - 70 - ns
Address Access Time
tAA - 55 - 70 ns
Chip Enable Access Time
t
ACE1, tACE2
- 55 - 70 ns
Output Enable Access Time
tOE - 30 - 35 ns
Chip Enable to Output in Low Z
t
CLZ1*, tCLZ2*
10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High Z
t
CHZ1*, tCHZ2*
- 20 - 25 ns
Output Disable to Output in High Z
t
OHZ*
- 20 - 25 ns
Output Hold from Address Change
tOH 10 - 10 - ns
(2) WRITE CYCLE
UT62L2568-55
V
CC
= 2.7V~3.6V
UT62L2568-70
VCC = 2.5V~3.6V
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
tWC 55 - 70 - ns
Address Valid to End of Write
tAW 50 - 60 - ns
Chip Enable to End of Write
t
CW1, tCW2
50 - 60 - ns
Address Set-up Time
tAS 0 - 0 - ns
Write Pulse Width
tWP 45 - 55 - ns
Write Recovery Time
tWR 0 - 0 - ns
Data to Write Time Overlap
tDW 25 - 30 - ns
Data Hold from End of Write Time
tDH 0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High Z
t
WHZ*
- 30 - 30 ns
*These parameters are guaranteed by device characterization, but not production tested.
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