UTRON UT62L1024SC-70LLI, UT62L1024SC-70LI, UT62L1024SC-55LLI, UT62L1024SC-55LI, UT62L1024LS-70LLI Datasheet
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UTRON
UT62L1024(I)
Preliminary Rev. 0.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Access time : 55/70ns (max.)
Low power consumption :
Operating : 30/20 mA (typical)
Standby : 10µA (max) L-version T
A
＝50℃
3µA (max) LL-version T
A
＝50℃
Power supply range : 2.5V ~ 3.6V
All inputs and outputs TTL compatible
Fully static operation
Data retention voltage : 2V (min.)
Operation Temperature
Industrial : -40℃~+85℃
Package : 32-pin 450mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
36-pin 6×8mm TFBGA
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input (
1CE
,CE2) and supports
industrial operating temperature range.
The UT62L1024 operates from a wide range
2.5V~3.6V power supply and all inputs and outputs
are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
2048 ×512
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A16
Vcc
Vss
I/O1-I/O8
CE1
CE2
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62L1024
SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
1CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-1/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT62L1024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE2
NC
A15
32
31
30
29
A16
1CE
I/O8
OE
WE
A12A11 A13
CE2
NC
A10 A14
A15
I/O6
I/O7
I/O8
A9
Vss
A8
A16
I/O5
Vcc
Vcc
I/O4
NC
Vss
A7
A0
I/O3
I/O2
I/O1
A6A1 A3
A5NC
A4A2
123456
H
G
C
D
E
F
A
B
TFBGA
CE1
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
1CE
,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss V
TERM
-0.5 to Vcc+0.5 V
Operating Temperature Industrial TA -40 to +85
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 sec) T
solder
260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
1CE
CE2
OE
WE
I/O OPERATION SUPPLY CURRENT
Standby H X X X High - Z
I
SB
,
I
SB1
Standby X L X X High -Z
I
SB
,
I
SB1
Output Disable L H H H High - Z ICC, ICC1
Read L H L H D
OUT
ICC, ICC1
Write L H X L D
IN
ICC, ICC1,
Note: H = VIH, L=VIL, X = Don't care.
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V~3.6V, TA = -40℃~+85℃ )
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage
V
IH
2.0 - V
CC
+0.5 V
Input Low Voltage
V
IL
- 0.5 - 0.6 V
Input Leakage Current
I
IL
VSS ≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current I
OL
VSS ≦V
I/O
≦
V
CC
1CE
=V
IH
or CE2 = VIL or
OE
= V
IH
or
WE
= V
IL
- 1 - 1
µ
A
Output High Voltage
V
OH
IOH = - 1mA 2.0 - - V
Output Low Voltage
V
OL
IOL= 2.1mA - - 0.4 V
55 - 30 40 mA
ICC
Cycle time = Min.,100% Duty,
1CE
=V
IL
, CE2 = VIH,I
I/O
=0mA
70 - 20 30 mA
Average Operating
Power Supply Courrent
I
CC1
Cycle time = 1µs, 100% Duty,
.
1CE
≦
0.2V,CE2≧V
CC
-0.2V, I
I/O
= 0mA
- - 5 mA
I
SB
1CE
=V
IH
or CE2 = VIL
- - 1.0 mA
TA = -40℃~+85℃
- - 50
- L
TA=+50℃
- - 10
µ
A
TA = -40℃~+85℃
- - 10
Standby Power
Supply Current
I
SB1
1CE
≧
V
CC
-0.2V
or .CE2≦0.2V
-
LL
TA=+50℃
- - 3
µ
A
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0.4V to 2.2V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=30pF, IOH/IOL=-1mA/2.1mA
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
128K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80078
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V~3.6V , TA = -40℃~+85℃ )
(1) READ CYCLE
UT62L1024-55 UT62L1024-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time tRC 55 - 70 - ns
Address Access Time tAA - 55 - 70 ns
Chip Enable Access Time t
ACE1
, t
ACE2
- 55 - 70 ns
Output Enable Access Time tOE - 30 - 35 ns
Chip Enable to Output in Low-Z t
CLZ1
*, t
CLZ2
* 10 - 10 - ns
Output Enable to Output in Low-Z t
OLZ
* 5 - 5 - ns
Chip Disable to Output in High-Z t
CHZ1
*, t
CHZ2
* - 30 - 35 ns
Output Disable to Output in High-Z t
OHZ
* - 30 - 35 ns
Output Hold from Address Change tOH 5 - 5 - ns
(2) WRITE CYCLE
UT62L1024-55 UT62L1024-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time tWC 55 - 70 - ns
Address Valid to End of Write tAW 50 - 60 - ns
Chip Enable to End of Write t
CW1
, t
CW2
50 - 60 - ns
Address Set-up Time tAS 0 - 0 - ns
Write Pulse Width tWP 40 - 45 - ns
Write Recovery Time tWR 0 - 0 - ns
Data to Write Time Overlap tDW 25 - 30 - ns
Data Hold from End of Write-Time tDH 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - ns
Write to Output in High-Z t
WHZ
* - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
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