UTRON UT62L1024SC-70LL, UT62L1024SC-70L, UT62L1024SC-55LL, UT62L1024SC-55L, UT62L1024SC-35LL Datasheet
...
Rev. 1.7
UTRON
128K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 40/35/30 mA (typical)
Standby : 2.5µA (typical) L-version
0.5µA (typical) LL-version
Power supply range : 2.7V to 3.6V
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8x20 mm TSOP-1
32-pin 8x13.4 mm STSOP
FUNCTIONAL BLOCK DIAGRAM
UT62L1024
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power
CMOS static random access memory organized
as 131,072 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
Easy memory expansion is provided by using
two chip enable input.(
particularly well suited for battery back-up
nonvolatile memory application.
The UT62L1024 operates from a single 2.7V~
3.6V power supply and all inputs and outputs
are fully TTL compatible.
,CE2) It is
1CE
2048 ×512
A0-A16
DECODER
MEMORY
ARRAY
Vcc
Vss
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE1
CE2
OE
CONTROL
CIRCUIT
WE
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
Rev. 1.7
UTRON
128K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
31
30
29
UT62L1024
28
27
26
25
24
23
22
21
20
19
18
1716
PDIP / SOP
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
,CE2
1CE
WE
OE
Chip enable 1,2 Inputs
Write Enable Input
Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
Vcc
A15
CE2
WE
A13
A9
A11
OE
A10
I/O8
I/O7
I/O6
I/O5
I/O4
UT62L1024
A11
A9
A8
A13
WE
A8
1CE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4 A3
1
2
3
4
5
6
7
8
UT62L1024
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
1CE
A0
A1
A2
TSOP-I/STSOP
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
Rev. 1.7
UTRON
128K X 8 BIT LOW POWER CMOS SRAM
UT62L1024
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss V
Operating Temperature TA 0 to +70
Storage Temperature T
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 sec) T
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
TRUTH TABLE
MODE
CE2
1CE
Standby H X X X High - Z
Standby X L X X High -Z
Output Disable L H H H High - Z
Read L H L H
Write L H X L
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current I
Output High Voltage
Output Low Voltage
Average Operating
I
V
V
V
V
I
CC
IL
OL
OH
OL
IH
IL
Power Supply Courrent
I
CC1
Standby Power
Supply Current
*Those parameters are for reference only under 50℃
I
SB
I
SB1
*
-0.5 to +4.6 V
TERM
℃
-65 to +150
STG
50 mA
OUT
260
solder
I/O OPERATION SUPPLY CURRENT
OE
VSS ≦VIN ≦VCC
VSS ≦V
=V
1CE
= V
OE
WE
(VCC = 2.7V~3.6V, Ta = 0℃ to +70℃)
≦
V
I/O
IH
IH
CC
or CE2 = VIL or
WE
= V
or
D
OUT
D
IN
IL
2.0 - V
- 0.5 - 0.6 V
- 1 - 1
- 1 - 1
,
I
I
SB
SB1
,
I
I
SB
SB1
I
CC , ICC1
I
CC , ICC1
I
CC , ICC1
CC
IOH = - 1mA 2.2 - - V
IOL= 4mA - - 0.4 V
Cycle time =Min. 100% Duty,
=V
I
= 0mA
I/O
, CE2 = VIH,
1CE
IL
35 - 40 60 mA
55 - 35 50 mA
70 - 30 40 mA
Cycle time = 1µs, 100% Duty,
≦
1CE
= 0mA
I/O
=V
1CE
≧
1CE
0.2V,CE2≧V
or CE2 = VIL
IH
V
CC
.
I
.CE2≦0.2V
-0.2V or
-0.2V,
CC
- - 5 mA
- - 1.0 mA
- L - 2.5
-
- 0.5
LL
100
20*
10*
℃
℃
+0.5 V
µ
µ
µ
40
µ
A
A
A
A
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
Rev. 1.7
UTRON
128K X 8 BIT LOW POWER CMOS SRAM
UT62L1024
CAPACITANCE
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=50pF, IOH/IOL=-1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time tRC 35 - 55 - 70 - ns
Address Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time t
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z t
Output Enable to Output in Low-Z t
Chip Disable to Output in High-Z t
Output Disable to Output in High-Z t
Output Hold from Address Change tOH 5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL
Write Cycle Time tWC 35 - 55 - 70 - ns
Address Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write t
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 25 - 40 - 45 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z t
*These parameters are guaranteed by device characterization, but not production tested.
(Ta=25℃, f=1.0MHz)
SYMBOL
, t
ACE1
*, t
CLZ1
* 5 - 5 - 5 - ns
OLZ
*, t
CHZ1
* - 25 - 30 - 35 ns
OHZ
, t
CW1
CW2
* - 15 - 20 - 25 ns
WHZ
C
IN
C
I/O
UT62L1024-35 UT62L1024-55 UT62L1024-70
-
-
(VCC = 2.7V~3.6V , Ta = 0℃ to +70℃)
MIN. MAX. MIN. MAX. MIN. MAX.
- 35 - 55 - 70 ns
ACE2
* 10 - 10 - 10 - ns
CLZ2
* - 25 - 30 - 35 ns
CHZ2
UT62L1024-35
MIN.
30 - 50 - 60 - ns
UT62L1024-55
MAX. MIN.
6 pF
8 pF
UT62L1024-70
MAX. MIN. MAX.
UNIT
UNIT
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
Rev. 1.7
UTRON
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
Address
DOUT Data Valid
READ CYCLE 2 (
1CE
t
AA
t
OH
, CE2 and
(1,2,4)
Controlled)
OE
t
RC
(1,3,5,6)
RC
t
UT62L1024
t
OH
Address
AA
t
t
CE1
CE2
OE
t
CLZ1
t
CLZ2
t
CHZ2
OLZ
OE
and t
Dout
Notes :
1.
2. Device is continuously selected
3. Address must be valid prior to or coincident with
4.
5. t
6. At any given temperature and voltage condition, t
is HIGH for a read cycle.
WE
is low.
OE
, t
CLZ1
CLZ2
, t
HIGH-Z
, t
OLZ
CHZ1
, t
ACE1
t
ACE2
,
=V
and CE2=V
IL
1CE
are specified with CL=5pF. Transition is measured ±500mV from steady state.
OHZ
t
OE
low
1CE
is less than t
CHZ1
t
CHZ1
t
CHZ2
t
OHZ
t
OH
HIGH-Z
Data Valid
IH.
and CE2 high transition; otherwise tAA is the limiting parameter.
, t
CLZ1
CHZ2
is less than t
CLZ2
, t
is less than t
OHZ
OLZ.
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
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