UTMC 5962R8957701QYA, 5962R8957701VYX, 5962R8957701VYC, 5962R8957701VYA, 5962R8957701QYX Datasheet

BCRTM-1

UT1553 BCRTM

FEATURES

p Comprehensive MIL-STD-1553 dual-redundant Bus

Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions

p MIL-STD-1773 compatible
p Multiple message processing capability in BC
p Time tagging and message logging in RT and M modes
p Automatic polling and intermessage delay in

BC mode

p Programmable interrupt scheme and internally

generated interrupt history list

p Register-oriented architecture to enhance

programmability

p DMA memory interface with 64K addressability
p Internal self-test
p Radiation-hardened option available for 84-lead

flatpack package only

p Remote terminal operations in ASD/ENASD-certified

(SEAFAC)

p Available in 84-pin pingrid array, 84-lead flatpack, 84-

lead leadless chip-carrier

p Standard Microcircuit Drawing 5962-89577 available

- QML Q and V compliant

16

16

16

CONTROL

DMA/CPU

MESSAGE

RT/MONITOR

MESSAGE

BC PROTOCOL

HANDLER

INTERRUPT

CONVER-

PARALLEL

SERIAL-TO-

CONVER-

TO-SERIAL

PARALLEL-

MODULE

DECODER

ENCODER/

CHANNEL

DUAL

BUS

TRANSFER

LOGIC

ADDRESS

16

TIMEOUT

TIMERON

CLOCK &

RESET

12MHz

MASTER
RESET

GENERATOR

ADDRESS

16

1553

HIGH-PRIORITY

RT ADDRESS

STANDARD INTERRUPT

HIGH-PRIORITY

INTERRUPT LOG

CURRENT COMMAND

BUILT-IN-TEST WORD

POLLING COMPARE

CURRENT BC (or M) BLOCK/

STATUS

CONTROL

REGISTERS

LIST POINTER

DATA

16

BUILT-

IN-

TEST

16

16

MONITOR ADDRESS

INTERRUPT STATUS

INTERRUPT ENABLE

SION

SION

PROTOCOL &

HANDLER

&

HANDLER

DATA
CHANNEL
B

1553

DATA
CHANNEL
A

LOGIC

HIGH-PRIORITY

STD PRIORITY LEVEL

STD PRIORITY PULSE

DMA ARBITRATION

REGISTER CONTROL

DUAL-PORT MEMORY CONTROL

RT DESCRIPTOR SPACE

ENABLE

BUILT-IN-TEST

START COMMAND
RESET COMMAND

CONTROL

MONITOR ADDRESS

SELECT (0-15)

MONITOR ADDRESS

Figure 1. BCRTM Block Diagram

SELECT (16-31)

RT TIMER

RESET COMMAND

BCRTM-2

Table of Contents

1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Features - Bus Controller (BC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.0 PIN IDENTIFICATION AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.0 INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.0 SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.0 SYSTEM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.2 Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3 CPU Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.4 RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.6 Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.0 REMOTE TERMINAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 RT Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.1 RT Subaddress Descriptor Definitions. . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.2 RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

6.3 RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

7.0 BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

7.2 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7.3 BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7.4 BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7.5 BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.0 MONITOR ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

8.2 Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

8.3 Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

9.0 EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . . . . . 36

10.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . 40

11.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12.0 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.0 PACKAGE OUTLINE DRAWINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

BCRTM-3

1.0 INTRODUCTION

The monolithic CMOS UT1553 BCRTM provides the
system designer with an intelligent solution to
MIL-STD-1553B multiplexed serial data bus design
problems. The UT1553B BCRTM is a single-chip device
that implements all three of defined MIL-STD-1553B
functions - Bus Controller, Remote Terminal, and Monitor.
Designed to reduce host CPU overhead, the BCRTM’s
powerful state machines automatically execute message
transfers, provide interrupts, and generate status
information. Multiple registers offer many programmable
functions as well as extensive information for host use. In
the BC mode, the BCRTM uses a linked-list message
scheme to provide the host with message chaining
capability. The BCRTM enhances memory use by
supporting variable-size, relocatable data blocks. In the RT
mode, the BCRTM implements time-tagging and message
history functions. It also supports multiple (up to 128)
message buffering and variable length messages to any
subaddress.In the Monitor (M) mode, the BCRTM’s
powerful linked list command block structure allows it to
process a series of monitored 1553 messages without the
intervention of the host. The BCRTM can store as much bus
traffic as can be contained in its 64K memory space. In
addition, the host has the capability of instructing the
BCRTM to monitor and store data for only selected remote
terminals.

The UT1553 BCRTM is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.

1.1 Features - Remote Terminal (RT) Mode
Indexing

The BCRTM is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTM, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.

Variable Space Allocation

The BCRTM can use as little or as much memory (up to
64K) as needed.

Selectable Data Storage

Address programmability within the BCRTM provides
flexible data placement and convenient access.

Sequential Data Storage

The BCRTM stores/retrieves, by subaddress, all messages
in the order in which they are transacted.

Sequential Message Status Information

The BCRTM provides message validity, time-tag, and

word-count information, and stores it sequentially in a
separate, cross-referenced list.

Illegalizing Mode Codes and Subaddresses

The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.

Programmable Interrupt Selection

The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.

Interrupt History List

The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.

1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing

The BCRTM autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.

Automatic Intermessage Delay

When programmed by the host, the BCRTM can delay a
host-specified time before executing the next message in
sequence.

Automatic Polling

When polling, the BCRTM interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTM
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.

Automatic Retry

The BCRTM can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTM can retry up to four times on the same or on the
alternate bus.

Programmable Interrupt Selection

The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.

Interrupt History List

The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.

Variable Space Allocation

The BCRTM uses as little or as much memory (up to 64K)
as needed.

Selectable Data Storage

Address programmability within the BCRTM provides
flexible data placement and convenient access.

BCRTM-4

1.3 Features - Monitor (M) Mode
Command History List

The BCRTM’s linked list command block structure permits
the BCRTM to process a series of monitored messages
without host intervention.

Monitor Selected Terminal Address

The host can select the remote terminals to be monitored by
programming the proper bits in the Terminal Address Select
registers (Registers16 and 17). The BCRTM can monitor
any or all remote terminals.

Variable Space Allocation

The BCRTM can use as little or as much memory (up to
64K) as needed

Selectable Data Storage

Address programmability within the BCRTM provides
flexible data placement and convenient access.

Sequential Data Storage

The BCRTM stores, by Terminal Address, all 1553
messages in the order in which they are transacted.

Programmable Interrupt Selection

The host can select a wide variety of events that may cause
an interrupting event.

Interrupt History List

The BCRTM stores, chronologically in memory, an
Interrupt History List of each event that causes an interrupt.

BCRTM-5

** Pin internally pulled up.
+ Pin at high impedance when not asserted
++ Bidirectional pin.
* Formerly MEMWIN.

++

++

+

+

+

**

**

**

LCC, flatpack pin number not in parentheses.

() Pingrid array pin identification in parentheses.

TAZ

TAO

RAZ

RAO

TBZ

TBO

RBZ

RBO

RTA0
RTA1
RTA2
RTA3
RTA4

RTPTY

CLK
MCLK
MCLKD2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

13 (K3)
14 (L2)
1718(L4)

(K6)

15
16
19
20

(L3)
(K5)

(L5)

(K4)

28 (K8) **
29 (L9) **
30 (L10) **
31 (K9) **
32 (L11) **

68 (A6)
69 (A4)
70 (B4)
25 (K7)

26 (J7)

27 (L8)
72 (A2)
75 (B2)

33 (K10) **

73 (B3)*

56 (A10)
57 (A9)
67 (B5)
58 (B8)

61 (B7)
60 (C7)

53 (A11)
52 (C10)
59 (A8)
54 (B10)

62 (A7)

55 (B9)

66 (A5)
11

(A3)

74

(K2)12

(A1)

10 (J2)
24 (L7)

34(J10)
35(K11)
36
37
38
39
40
41
44
45
46
47
48
49
50
51

(J11)
(H10)
(H11)
(G9)
(G10)
(G11)
(E9)
(E11)
(E10)
(F11)
(D11)
(D10)
(C11)
(B11)

9
8
7
6
5
4
3
2
83
82
81
80
79
78
77
76

(K1)
(J1)
(H2)
(H1)
(G3)
(G2)
(G1)
(F1)
(E1)
(E2)
(F2)
(D1)
(D2)
(C1)
(B1)
(C2)

23
43
64
84

1
22
42
63

(L6)
(F9)
(C6)
(E3)

(F3)
(J6)
(F10)
(B6)

21
65

(J5)
(C5)

71

(L1)

BIPHASE OUT

BIPHASE IN

TERMINAL

ADDRESS

STATUS
SIGNALS

DMA
SIGNALS

CONTROL
SIGNALS

ADDRESS
LINES

DATA
LINES

POWER

GROUND

CLOCK
SIGNALS

+

++
++
++

2.0 PIN I

DENTIFICATION AND DESCRIPTION

+

**

STDINTL
STDINTP

HPINT

TIMERON

COMSTR

SSYSF
BCRTF

CHA/B

TEST

DMAR
DMAG

DMAGO

DMACK

BURST

TSCTL

RD

WR

CS

AEN

BCRTSEL

LOCK
MRST

EXTOVR

RRD

RWR

MEMCSI

MEMCSO

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

Figure 2. BCRT Functional Pin Description

BCRTM-6

A0 34

B11

TTB Bit 0 (LSB) of the Address bus
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

35
36
37
38
39
40
41
44
45
46
47

C11

D10

D11

F11

E10

E11

E9

G11

G10

G9

H11

TTB

TTB

TTB

Bit 1 of the Address bus
Bit 2 of the Address bus
Bit 3 of the Address bus
Bit 4 of the Address bus
Bit 5 of the Address bus
Bit 6 of the Address bus
Bit 7 of the Address bus
Bit 8 of the Address bus
Bit 9 of the Address bus
Bit 10 of the Address bus
Bit 11 of the Address bus

48

H10

A13
A14

49
50

J11

K11

TTO

TTO
TTO

NAME

PIN NUMBER
LCC PGA

TYPE ACTIVE DESCRIPTION

A15 51

J10

TTB

TTO
TTO
TTO
TTO
TTO
TTO
TTO

TTO

Bit 12 of the Address bus

Bit 13 of the Address bus
Bit 14 of the Address bus
Bit 15 (MSB) of the Address bus

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

Legend for TYPE and ACTIVE fields:

TUI = TTL input (pull-up)
AL = Active low
AH = Active high
ZL = Active low - inactive state is high impedance
TI = TTL input
TO = TTL output
TTO = Three-state TTL output
TTB = Bidirectional

Notes:

1. Address and data buses are in the high-impedance state when idle.

2. Flatpack pin numbers are same as LCC.

BCRTM-7

TTB
TTB
TTB
TTB

D0
D1
D2
D3

9 K1
8
7
6

J1
H2
H1

Bit 0 (LSB) of the Data bus
Bit 1 of the Data bus
Bit 2 of the Data bus

Bit 3 of the Data bus
D4
D5
D6

D7
D8
D9
D10
D11

5
4
3

2
83
82
81
80

G3
G2
G1

F1
E1
E2
F2

D1

TTB
TTB
TTB

TTB
TTB
TTB
TTB
TTB

Bit 4 of the Data bus
Bit 5 of the Data bus
Bit 6 of the Data bus

Bit 7 of the Data bus
Bit 8 of the Data bus
Bit 9 of the Data bus
Bit 10 of the Data bus
Bit 11 of the Data bus

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

NAME TYPE ACTIVE DESCRIPTION

DATA BUS

D12
D13
D14
D15

79
78
77
76

D2
C1
B1
C2

TTB
TTB
TTB
TTB

Bit 12 of the Data bus
Bit 13 of the Data bus
Bit 14 of the Data bus
Bit 15 (MSB) of the Data bus

--

--

--

--

PIN NUMBER

LCC PGA

NAME TYPE ACTIVE DESCRIPTION

RTA0

TERMINAL ADDRESS INPUTS

28 K8 TUI Remote Terminal Address Bit 0 (LSB). The entire

RT address is strobed in at Master Reset. Verify it
by reading the Remote Terminal Address Register.
All the Remote Terminal Address bits are internally
pulled up.

RTA1 29 L9 TUI Remote Terminal Address Bit 1. This is bit 1 of

the Remote Terminal Address.

RTA2 30 L10 TUI Remote Terminal Address Bit 2. This is bit 2 of

the Remote Terminal Address.

RTA3 31 K9 TUI Remote Terminal Address Bit 3. This is bit 3 of

the Remote Terminal Address.

--

--

--

--

RTPTY 33 K10 TUI Remote Terminal (Address) Parity. This is an odd

parity input for the Remote Terminal Address.

RTA4 32 L11 TUI Remote Terminal Address Bit 4. This is bit 4

(MSB) of the Remote Terminal Address.

--

--

PIN NUMBER
LCC PGA

BCRTM-8

62

61

60

A7

B7

C7

TI

TI

TI

AL

AL

AL

AEN 66 A5 TI AH

BCRTSEL 11 L1 TUI --

LOCK 12

24

K2

L7

TUI

TUI

AH

AL

10 J2 AL

NAME TYPE ACTIVE DESCRIPTION

CONTROL SIGNALS

54

59

B10

A8

TO

TUI

AL

AL

52 C10 TO AL

53 A11 TO AL

TI

Read. The host uses this in conjunction with CS to read an
internal BCRTM register.

Write. The host uses this in conjunction with CS to write to an
internal BCRTM register.

BC/RT Select. This selects between either the Bus Con­troller or Remote Terminal mode. The BC/RT Mode
Select bit in the Control Register overrides this input if
the LOCK pin is not high. This pin is internally
pulled high.

Lock. When set, this pin prevents internal changes
to both the RT address and BC/RT mode select functions.
This pin is internally pulled high.

External Override. Use this in multi-redundant applica­tions. Upon receipt, the BCRTM aborts all current activ­ity. EXTOVR should be connected to COMSTR output of
the adjacent BCRTM when used. This pin is internally
pulled high.

Memory Chip Select Out. This is the regenerated
MEMCSI input for external RAM during the pseudo­dual-port RAM mode. The BCRTM also uses it to select
external memory during memory accesses.

RD

WR

CS

EXTOVR

MRST

MEMCSO

MEMCSI

RRD

RWR

Memory Chip Select In. Used in the pseudo-dual-port
RAM mode only, MEMCSI is received from the host and
is propagated through to the MEMCSO.

RAM Read. In the pseudo-dual-port RAM mode, the host
uses this signal in conjunction with MEMCSO to read
from external RAM through the BCRTM. It is also the
signal the BCRTM uses to read from memory. It is
asserted following receipt of DMAG. When the BCRTM
performs multiple reads, this signal is pulsed.

RAM Write. In the pseudo-dual-port RAM mode, the
CPU and BCRTM use this to write to external RAM. This
signal is asserted following receipt of DMAG. For multi­ple writes, this signal is pulsed.

PIN NUMBER

LCC PGA

Chip Select. This selects the BCRTM when accessing
the BCRTM’s internal register.

Address Enable. The host CPU uses AEN to indicate to the
BCRTM that the BCRTM’s address lines can be asserted;
this is a precautionary signal provided to avoid address bus
crash. If not used, it must be tied high.

Master Reset. This resets all internal state machines,
encoders, decoders, and registers. The minimum pulse
width for a successful Master Reset is 500ns.

BCRTM-9

68

69

70

A6

A4

B4

TTO

TO

TTO

ZL

AL

ZL

NAME TYPE ACTIVE DESCRIPTION

25

26

27

K7

J7

L8

TO

TO

TO AL

AL

SSYSF

BCRTF

TEST

72

75

73

A2

B2

B3

TI

TO

TO

AH

AH

AL

STATUS SIGNALS

(RT)Timer On. This is a 760-microsecond fail-safe trans­mitter enable timer. Started at the beginning of a transmis­sion. TIMERON goes inactive 760 microseconds later or
is reset automatically with the receipt of a new command.
Use it in conjunction with CHA/B output to provide a fail
safe timer for channel A and B transmitters.

--

Standard Interrupt Level. This is a level interrupt. It is
asserted when one or more events enabled in either the
Standard Interrupt Enable Register, RT Descriptor, or BC
Command Block occur. Resetting the Standard Interrupt
bit in the High-Priority Interrupt Status/Reset Register
clears the interrupt.

STDINTL

STDINTP

Standard Interrupt Pulse. STDINTP pulses when an inter­rupt is logged.

HPINT

High Priority Interrupt. The High-Priority Interrupt level
is asserted upon occurrence of events enabled in the High
Priority Interrupt Enable Register. The corresponding
bit(s) in the High-Priority Interrupt Status/Reset Register
reset HPINT.

TIMERON

COMSTR

CHA/B

Channel A/B. This indicates the active or last active
channel.

TEST. This pin is used as a factory test pin. (Formerly
MEMWIN.)

PIN NUMBER

LCC PGA

(RT) Command Strobe. The BCRTM asserts this
signal after receiving a valid command. The BCRTM deac-

tivates it after servicing the command.
Subsystem Fail. Upon receipt, this signal propagates
directly to the RT 1553 status word and the BCRTM
Status Register.

BCRT Fail. this indicates a Built-In-Test (BIT) failure.
In the RT mode, the Terminal Flag bit in 1553 status word
is also set.

NAME TYPE ACTIVE DESCRIPTION

BIPHASE INPUTS

RAO 16 K4 TI

RBO 20 L5 TI

RAZ

RBZ

15

19

L3

K5

TI

TI

--

--

--

--

PIN NUMBER
LCC PGA

Receive Channel A One. This is the Manchester-en-coded
true signal input from Channel A of the bus receiver

Receive Channel A Zero. This is Manchester-encoded
complementary signal input from Channel A of the bus
receiver

Receive Channel B One. This is the Manchester-en-coded
true signal input from Channel B of the bus receiver.

Receive Channel B Zero. This is the Manchester-en-coded
complementary signal input from Channel B of the bus
receiver

BCRTM-10

NAME TYPE ACTIVE DESCRIPTION

TAO 14 L2 TO

TAZ 13 K3 TO

TBO 18 K6 TO

--

--

--

TBZ 17 L4 TO --

BIPHASE OUTPUTS

Transmit Channel A One. This is the Manchester-encoded
true output to be connected to the Channel A bus transmitter
input. This signal is idle low.

Transmit Channel A Zero. This is the Manchester-encoded
complementary output to be connected to the Channel A bus
transmitter input. This signal is idle low.

Transmit Channel B One. This is the Manchester­encoded true output to be connected to the Channel B bus
transmitter input. This signal is idle low.

Transmit Channel B Zero. This is the Manchester-encoded
complementary output to be connected to the Channel B bus
transmitter input. This signal is idle low.

PIN NUMBER

LCC PGA

56 A10 ZL

57

67

58

A9

B5

B8

AL

AL

ZL

TTO

TI

TO

TTO

NAME TYPE ACTIVE DESCRIPTION

DMA SIGNALS

55 B9 TO AL

BURST 74 A1 TO AH

DMA Request. The BCRTM issues this signal when access to
RAM is required. It goes inactive after receiving a DMAG
signal.

DMAR

DMAG

DMAGO

DMACK

TSCTL

DMA Grant Out. If DMAG is received but not needed, it
passes through to this output.

DMA Acknowledge. The BCRTM asserts this signal to confirm

receipt of DMAG, it stays low until memory access is complete.

PIN NUMBER
LCC PGA

DMA Grant. This input to the BCRTM allows the
BCRT to access RAM. It is recognized 45ns before the rising
edge of MCLKD2.

Three-State Control. This signal indicates when the
BCRTM is actually accessing memory. The host subsystem’s

address and data lines must be in the high-impedance state when

the signals active. This signal assists in placing the external data

and address buffers into the high-impedance state.

Burst (DMA Cycle). This indicates that the current
DMA cycle transfers at least two words; worst case is five words
plus a “dummy” word.

BCRTM-11

NAME TYPE ACTIVE DESCRIPTION

CLK

MCLK

MCLKD2

21

65

71

J5

C5

A3

TI

TI

TO

Memory Clock Divided by Two. This signal is the
Memory Clock input divided by two. It assists the
host subsystem in synchronizing DMA events.

Clock. The 12MHz input clock requires a 50%
± 10% duty cycle with an accuracy of ± 0.01%. The accuracy
is required in order to meet the Manchester encoding/
decoding requirements of MIL-STD-1553.

Memory Clock. This is the input clock frequency the BCRTM
uses for memory accesses. The memory cycle time is equal
to two MCLK cycles. Therefore, RAM access time is
dependent upon the chosen MCLK frequency (6MHz
minimum, 12MHz maximum). Please see the BCRTM DMA
timing diagrams in this data sheet.

--

--

--

CLOCK SIGNALS

PIN NUMBER

LCC PGA

NAME TYPE ACTIVE DESCRIPTION

23
43
64
84

1

22
42

63

L6
F9

G13

C7

J3

N8

F10

B6

PWR
PWR
PWR
PWR
GND
GND

GND
GND

+5V
+5V
+5V
+5V
Ground
Ground

Ground
Ground

--

--

--

--

--

--

--

--

POWER AND

V

DD

V

SS

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

PIN NUMBER
LCC PGA

BCRTM-12

3.0 INTERNAL REGISTERS

The BCRTM’s internal registers (see table 1 on pages 18-

19) enable the CPU to control the actions of the BCRTM
while maintaining low DMA overhead by the BCRTM. All
functions are active high and ignored when low unless stated

otherwise. Functions and parameters are used in both RT

and BC modes except where indicated. Registers are

addressed by the binary equivalent of their decimal number.

For example, Register 1 is addressed as 0001B. Register

usage is defined as follows:

#0 Control Register
Bit

Number Description

BIT 15 Reserved.
BIT 14 Rt Address 31. When RT31=0, the BCRTM recognizes RT Address 31 as a Broadcast command. When

RT31=1,the BCRTM treats RT Address 31 as a normal terminal address.

BIT 13 Subaddress 31. When SA31=0, the BCRTM recognizes a command word with either subaddress 0 or 31 as being

a valid code. When SA31=1, the BCRTM only recognizes a command word with a subaddress of 0 as a valid
mode code.

BIT 12 Bus Controller Time out. When the BCRTM is a BC and BCTO=0, the BCRTM allows an RT up to 16us to

respond with a status word before it declares a bus time-out. If BCTO=1, the BCRTM allows an RT up to 32us to
respond with a status word before it declares a bus time-out. In the remote terminal mode of operation, this bit
controls to RT to RT response time-out. To support the requirements of MIL-STD-1553B, this bit is set to a

logical zero.
BIT 11 Enable External Override. For use in multi-redundant systems. This bit enables the EXTOVR pin.
BIT 10 BC/RT Select. This function selects between the Bus Controller and Remote Terminal/Monitor operation

modes. It overrides the external BCRTSEL input setting if the Change Lock-Out function is not used. A reset

operation must be performed when changing between BC and RT/M modes. For monitor operation this bit

must be "0". This bit is write-only.
BIT 9 (BC) Retry on Alternate Bus. This bit enables an automatic retry to operate on alternate buses. For example, if

on bus A, with two automatic retries programmed, the automatic retries occur on bus B.
BIT 8 (RT,M) Channel B Enable. When set, this bit enables Channel B operation.

(BC) No significance.
BIT 7 (RT,M) Channel A Enable. When set, this bit enables Channel A operation.

(BC) Channel Select A/B. When set, this bit selects Channel A.
BITs 6-5 (BC) Retry Count. These bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries)
BIT 4 (BC) Retry on Bus Controller Message Error. This bit enables automatic retries on an error the Bus Controller

detects (see the Bus Controller Architecture section, page 29).
BIT 3 (BC) Retry on Time-Out. This bit enables an automatic retry on a response time-out condition.
BIT 2 (BC) Retry on Message Error. This bit enables an automatic retry when the Message Error bit is set in the RT’s

status word response.
BIT 1 (BC) Retry on Busy. This bit enables automatic retry on a received Busy bit in an RT status word response.
BIT 0 Start Enable. In the BC mode, this bit starts/restarts Command Block execution. In the RT or M mode,

It enables the BCRTM to receive a valid command. RT operation does not start until a valid command is

received. When using this function:

• Restart the BCRTM after each Master Reset or programmed reset.

• This bit is not readable; verify operation by reading bit 0 of the BCRTM’s Status Register.

BCRTM-13

#1 Status Register (Read Only)

These bits indicate the BCRTM’s current status.

Bit
Number Description

BIT 15 TEST. This bit reflects the inverse of the TEST output. It changes state simultaneously with the TEST output.
BIT 14 (RT,M) Remote Terminal (or Monitor) Active. Indicates that the BCRTM, in the Remote Terminal (or Monitor)

mode, is presently servicing a command. This bit reflects the inverse of the COMSTR pin.
BIT 13 (RT) Dynamic Bus Control Acceptance. This bit reflects the state of the Dynamic Bus Control

Acceptance bit in the RT status word (see Register 10 on page 16).
BIT 12 (RT) Terminal Flag bit is set in RT status word. This bit reflects the result of writing to Register 10, bit 11
BIT 11 (RT) Service Request bit is set in RT status word.This bit reflects the result of writing to Register 10, bit 10.
BIT 10 (RT) Busy bit is set in RT status word.This bit reflects the result of writing to Register 10, bits 9 or 14.
BIT 9 BIT is in progress.
BIT 8 Reset is in progress. This bit indicates that either a write to Register 12 has just occurred or the BCRTM has

just received a Reset Remote Terminal (#01000) Mode Code. This bit remains set less than 1ms.
BIT 7 BC/(RT) Mode. Indicates the current mode of operation. A reset operation must be performed when changing

between BC and RT modes.
BIT 6 Channel A/B. Indicates either the channel presently in use or the last channel used.
BIT 5 Subsystem Fail Indicator. Indicates receiving a subsystem fail signal from the host subsystem on the

SSYSF input.
BITs 4-1 Reserved.
BIT 0 (BC) Command Block Execution is in progress. (RT) Remote Terminal is in operation. This bit reflects bit 0 of

Register 0.

#2 Current Command Block Register (BC,M)/Remote Terminal Descriptor Space Address Register (RT)

(BC) This register contains the address of the head pointer of the Command Block being executed. Accessing a new Command
Block updates it.

(RT) The host CPU initializes this register to indicate the starting location of the RT Descriptor Space. The host must allocate
320 sequential locations following this starting address. For proper operation, this location must start on an I x 512 decimal
address boundary, where I is an integer multiple.

(M) This register contains the address of the control/status word of the current Monitor Command Block. Accessing a new
Command Block updates it.

#3 Polling Compare Register

In the polling mode, the CPU sets the Polling Compare Register to indicate the RT response word on which the BCRTM should
interrupt. This register is 11 bits wide, corresponding to bit times 9 through 19 of the RT’s 1553 status word response. The
sync, Remote Terminal Address, and parity bits are not included (see the section on Polling, page 32).

BCRTM-14

#4 BIT (Built-In-Test) Word Register

The BCRTM uses the contents of this register when it responds to the Transmit BIT Word Mode Code (#10011). In addition,
the BCRTM writes to the two most significant bits of the BIT Word Register in response to either an Initiate Self-Test Mode
Code (RT mode) or a write to Register 11 (BIT Start Command) to indicate a BIT failure. If the BIT Word needs to be modified,
it can be read out, modified, then rewritten to this register. Note that if the processor writes a “1” to either bit 14 or 15 of this
register, it effectively induces a BIT failure.

Bit
Number Description

BIT 15 Channel B failure.
BIT 14 Channel A failure.
BIT 13-0 BIT Word. The least significant fourteen bits of the BIT Word are user programmable.

#5 Current Command Register (Read Only)

In the RT or Monitor mode, this register contains the command currently being processed. When not processing a command,
the BCRTM stores the last command or status word transmitted on the 1553B bus in this register. This register is updated only
when bit 0 of Register 0 is set. In the BC mode, this register contains the most current command sent out on the 1553B bus.

#6 Interrupt Log List Pointer Register

Initialized by the CPU, the Interrupt Log List Pointer Register indicates the start of the Interrupt Log List. After each list entry,
the BCRTM updates this register with the address of the next entry in the list. (See page 37.)

#7 High-Priority Interrupt Enable Register (Read/Write)

Setting the bits in this register causes a High-Priority Interrupt when the enabled event occurs. To service the High-Priority
Interrupt, the user reads Register 8 to determine the cause of the interrupt, then writes to Register 8 to clear the appropriate
bits. The BCRTM also provides a Standard Priority Interrupt Scheme that does not require host intervention. If High-Priority
Interrupt service is not possible in a given application, it is advisable to use the Standard Priority features.

Bit
Number Description

BITs 15-9 Reserved.
BIT 8 Data Overrun Enable. When set, this bit enables an interrupt when DMAG was not received by the BCRTM

within the allotted time needed for a successful data transfer to memory.
BIT 7 (BC) Illogical Command Error Enable. This bit enables a High-Priority Interrupt to be asserted upon the

occurrence of an Illogical Command. Illogical commands include incorrectly formatted RT-RT Command

Blocks.
BIT 6 (RT) Dynamic Bus Control Mode Code Interrupt Enable. When set, an interrupt is asserted when the

Dynamic Bus Control Mode Code is received.
BIT 5 Subsystem Fail Enable. When set, a High-Priority Interrupt is asserted after receiving a Subsystem Fail

(SSYSF) input pin.
BIT 4 End of BIT Enable. This bit indicates the end of the internal BIT routine.
BIT 3 BIT Word Fail Enable. This bit enables an interrupt indicating that the BCRTM detected a BIT failure.
BIT 2 (BC) End of Command Block List Enable (see Command Block Control Word, page 38.) This interrupt can be

superseded by other high-priority interrupts.
BIT 1 Message Error Enable. If enabled, a High-Priority Interrupt is asserted at the occurrence of a message error. If

a High-Priority Interrupt condition occurs, as the result of an enabled message error, the device will halt

operation until the user clears the interrupt by writing a “1” to Bit 1 of the High-Priority Interrupt Status/Reset

Register (Reg. #8). If this interrupt is not cleared, the BCRTM remains in the HALTED state (appearing to be

“locked up”), even if it receives a valid message. This High-Priority Interrupt scheme is necessary in order to

maintain the BCRTM’s state of operation so that the host CPU has this information available at the time of

interrupt service.
BIT 0 Standard Interrupt Enable. Setting this bit enables the STDINTL pin, but does not cause a high-priority

interrupt. If low, only the STDINTL pin is asserted when a Standard Interrupt occurs.

BCRTM-15

#8 High-Priority Interrupt Status/Reset Register

When a High-Priority Interrupt is asserted, this register indicates the event that caused it. To clear the interrupt signal and reset
the bit, write a “1” to the appropriate bit. See the corresponding bit definitions of Register 7, High-Priority Interrupt Enable
Register.

Bit
Number Description

BITs 15-9 Reserved.
BIT 8 Data Overrun.
BIT 7 Illogical Command.
BIT 6 Dynamic Bus Control Mode Received
BIT 5 Subsystem Fail.
BIT 4 End of BIT.
BIT 3 BIT Word Fail.
BIT 2 End of Command Block.
BIT 1 Message Error.
BIT 0 Standard Interrupt. The BCRTM sets this bit when any Standard Interrupt occurs, providing bit 0 of Register 7

is enabled.(Reset STDINTL output.)

#9 Standard Interrupt Enable Register

This register enables Standard Interrupt logging for any of the following enabled events (Standard Interrupt logging can also
occur for events enabled in the BC Command Block or RT Subaddress/Mode Code Descriptor):

Bit
Number Description

BITs 15-6 Reserved.
BIT 5 (RT) Illegal Broadcast Command. When set, this bit enables an interrupt indicating that an Illegal Broadcast

Command has been received.
BIT 4 (RT) Illegal Command. When set, this bit enables an interrupt indicating that an illegal command has been

received.
BIT 3 (BC) Polling Comparison Match. This enables an interrupt indicating that a polling event has occurred. The user

must also set bit 12 in the BC Command Block Control Word for this interrupt to occur.
BIT 2 (BC) Retry Fail. This bit enables an interrupt indicating that all the programmed number of retries have failed.
BIT 1 (BC, RT,M) Message Error Event. This bit enables a standard interrupt for message errors.
BIT 0 (BC,M) Command Block Interrupt and Continue. This bit enables an interrupt indicating that a Command

Block, with the Interrupt and Continue Function enabled, has been executed.

BCRTM-16

#10 Remote Terminal Address Register

This register sets the Remote Terminal Address via software. The Change Lock-Out Enable feature, when set, prevents the
Remote Terminal Address or the BCRTM Mode Selection from changing.

Bit
Number Description

BIT 15 (RT) Instrumentation. Setting this bit sets the RT status word Instrumentation bit.
BIT 14 (RT) Busy. Setting this bit sets the RT status word Busy bit. It does not inhibit data transfers to the subsystem.
BIT 13 (RT) Subsystem Fail. Setting this bit sets the RT status word Subsystem Flag bit. In the RT mode, the Subsystem

Fail is also logged into the Message Status Word.
BIT 12 (RT) Dynamic Bus Control Acceptance. Setting this bit sets the RT status word Dynamic Bus Control

Acceptance bit when the BCRTM receives the Dynamic Bus Control Mode Code from the currently active Bus

Controller. Host intervention is required for the BCRTM to take over as the active Bus Controller.
BIT 11 (RT) Terminal Flag. Setting this bit sets the RT status word Terminal Flag bit; the Terminal Flag bit in the RT

status word is also internally set if the BIT fails.
BIT 10 (RT) Service Request. Setting this bit sets the RT status word Service Request bit.
BIT 9 (RT) Busy Mode Enable. Setting this bit sets the RT status word Busy bit and inhibits all data transfers to the

subsystem.
BIT 8 BC/RT Mode Select. This bit’s state reflects the external pin BCRTSEL. It does not necessarily reflect the state

of the chip, since the BC/RT Mode Select is software-programmable via bit 10 of Register 0. This bit is

read-only.
BIT 7 Change Lock-Out. This bit’s state reflects the external pin LOCK. When set, this bit indicates that changes to the

RT address or the BC/RT Mode Select are not allowed using internal registers. This bit is read-only.
BIT 6 Remote Terminal Address Parity Error. This bit indicates a Remote Terminal Address Parity Error. It appears

after the Remote Terminal Address is latched if a parity error exists.
BIT 5 Remote Terminal Address Parity. This is an odd parity input bit used with the Remote Terminal Address. It

ensures accurate recognition of the Remote Terminal Address.
BITs 4-0 Remote Terminal Address (Bit 0 is the LSB). This reflects the RTA4-0 inputs at Master Reset. Modify the

Remote Terminal Address by writing to these bits.

#11 BIT Start Register (Write Only)

Any write (i.e., data = don’t care) to this register’s address location initiates the internal BIT routine, which lasts 100µs. Verify
using the BIT-in-Progress bit in the Status Register. A programmed reset (write to Register 12) must precede a write to this
register to initiate the internal BIT.A failure of the BIT will be indicated in Register 4 and the BCRTF pin.

The BCRTM’s self-test performs an internal wrap-around test between its Manchester encoder and its two Manchester decoders.
If the BCRTM detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of Register
4 (BIT Word Register) for Channel A and/or bit 15 for Channel B. When in the Remote Terminal mode, while the BCRTM is
performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test.

#12 Programmed Reset Register (Write Only)

Any write (i.e., data = don’t care) to this register’s address location initiates a reset sequence of the encoder/decoder and
protocol sections of the BCRTM which lasts less than 1 microsecond. This is identical to the reset used for the Reset Remote
Terminal Mode Code except that command processing halts. For a total reset (i.e., including registers), see the MRST signal
description.

BCRTM-17

#13 RT Timer Reset Register (Write Only)

Any write (i.e., data = don’t care) to this register’s address location resets the RT Time Tag timer to zero.
The BCRTM’s Remote Terminal Timer time-tags message transactions. The time tag is generated from a free-running eight-

bit timer of 64µs resolution. This timer can be reset to zero simply by writing to Register 13. When the timer is reset, it
immediately starts running.

#14 Activity Status/Operational Mode Register

BIT 15 Bus Monitor Select. This bit should be cleared for RT mode operation. The host sets this bit to enable the
BCRTM’s Monitor mode of operation. Bit 10 of Register 0 must also be "0" to enable the Monitor mode.

BIT 14 Monitor All Terminals. When this bit is set, the BCRTM monitors all remote terminal activity.If this bit is not set,

then bit 13 must be set. This bit should be cleared for RT Mode operation.
BIT 13 Monitor Declared Terminals. When this bit is set, the BCRTM monitors all remote terminal bus activity. If this

bit is not set, then bit 13 must be set.This bit should be cleared for RT mode operation.

BITs 12-0 Reserved

#15 Reserved Register

This register is reserved for BCRTM use only and the host should not access it.

#16 Monitor Selected Remote Terminal Address 15-0

BITs 15-0 Monitor Selected Remote Terminal Addresses 15-0. By setting the appropriate bit in this register, the host can

determine which or the Remote terminals, from RT 0 through RT 15, the BCRTM will monitor. For example,

by setting bit 5 in this register, the host instructs the BCRTM to only monitor the bus activity for remote terminal

5. These bits are not mutually exclusive, therefore, the host can monitor any number of different remote terminals

by selecting the proper combination of bits.

#17 Monitor Selected Remote Terminal Address 31-16

BITs 15-0 Monitor Selected Remote Terminal Addresses 31-16. By setting the appropriate bit in this register, the host can

determine which or the Remote terminals, from RT 16 through RT 31, the BCRTM will monitor. For example,

by setting bit 21 in this register, the host instructs the BCRTM to only monitor the bus activity for remote terminal

21. These bits are not mutually exclusive, therefore, the host can monitor any number of different remote

terminals by selecting the proper combination of bits on this register and Register 16.

BCRTM-18

7 6 5 4 3 2 1 0

89101112131415

7 6 5 4 3 2 1 0

89101112131415

7 6 5 4 3 2 1 0

89101112131415

7 6 5 4 3 2 1 0

89101112131415

#0

RTYTO

UNUSEDUNUSEDUNUSEDUNUSED

BCTOUNUSEDUNUSEDUNUSED

A15 A14 A13 A12 A11 A10 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

(BC) CURRENT COMMAND BLOCK REGISTER

TEST RTACT DYNBUS RT FLAG SRQ BUSY BIT RESET

BC/RT BUSA/B SSFAIL CMBKPG

BC/RT STATUS REGISTER

EXTOVR BC/RT RTYALTB BUSBEN

BUSAEN

CHNSEL

RTYCNT RTYBCME RTYME RTYBSY STEN

BC/RT CONTROL REGISTER

#3

#2

#1

7 6 5 4 3 2 1 0

89101112131415

(RT) REMOTE TERMINAL DESCRIPTOR SPACE ADDRESS REGISTER

POLLING COMPARE REGISTER

TFDBCSS FLAGBUSYBRDCST SWBT14SWBT13SWBT12

SRQINSTRMSGERRXXXXX

D7 D6 D5 D4 D3 D2 D1 D0

CURRENT COMMAND REGISTER

D10 D9 D8

#4#5BIT WORD REGISTER

CHBFAIL CHAFAIL D13 D12 D11

7 6 5 4 3 2 1 0

89101112131415

D7 D6 D5 D4 D3 D2 D1 D0

D10 D9 D8D15 D14 D13 D12 D11

UNUSEDUNUSEDUNUSEDUNUSEDUNUSEDUNUSED

#7

#6 INTERRUPT LOG LIST POINTER REGISTER

A0A1A2A3A4A5A6A7

A8A9A10A11A12A13A14A15

BCRTM HIGH-PRIORITYINTERRUPT ENABLE REGISTER

STDINTMSGERREOLBITFAILENDBITSSFAILDYNBUSILLCMD

DATOVRUNUSED

7 6 5 4 3 2 1 0

89101112131415

7 6 5 4 3 2 1 0

89101112131415

Table 1. BCRTM Registers

DATOVR

ILLCMD

BCRTM HIGH-PRIORITYINTERRUPT STATUS/RESET REGISTER#8

15 14 13 12 11 10 9 8

UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED

01234567

DYNBUS SSFAIL ENDBIT BITFAIL EOL MSGERR STDINT

BCRTM-19

#12

#13

PROGRAMMED RESET REGISTER

REMOTE TERMINAL TIMER RESET REGISTER

XXXXXXXX

XXXXXXXX

7 6 5 4 3 2 1 0

89101112131415

XXXXXXXX

XXXXXXXX

7 6 5 4 3 2 1 0

89101112131415

15 14 13 12 11 10 9 8

01234567

X

INSTR BUSY1BUSY2 SS FLAG DBC RT FLAG SRQ BC/RT

LOCK PARERR RTAPAR RTA4 RTA3 RTA2 RTA1 RTA0

ILLBCMD ILLCMD POLMTCH RTYFAIL MSGERR CMDBLK

BUILT-IN-TEST START REGISTER

REMOTE TERMINAL ADDRESS REGISTER

STANDARD INTERRUPT ENABLE REGISTER

#11

#10

#9

15 14 13 12 11 10 9 8

UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED

01234567

UNUSED UNUSED

15 14 13 12 11 10 9 8

01234567

X X X X X X X

X X X X X X X X

#14 BUS MONITOR CONTROL REGISTER

XXXXXXXX

XXXXXMDTMATBMS

7 6 5 4 3 2 1 0

89101112131415

#16 MONITOR SELECTED REMOTE TERMINAL ADDRESES 0-15

TA0TA1TA7

TA8TA9TA10TA11TA12TA13TA14TA15

7 6 5 4 3 2 1 0

89101112131415

TA6 TA5 TA4 TA3 TA2

X = DON’T CARE

#17 MONITOR SELECTED REMOTE TERMINAL ADDRESES 16-31

TA16TA17T23

TA24TA25TA26TA27TA28TA29TA30TA31

7 6 5 4 3 2 1 0

89101112131415

T22 T21 T20 T19 TA18

Table 1. BCRTM Registers (continued from page 18)