UTMC 5962R3829437SNC, 5962R3829437SNA, 5962R3829437BXX, 5962R3829437BXC, 5962R3829437BNX Datasheet

FEATURES

q 55ns maximum address access time, single-event upset less

than 1.0E-10 errors//bit day (-55oC to 125+oC)

q Asynchronous operation for compatibility with industry-

standard 8K x 8 SRAM

q TTL-compatible input and output levels
q Three-state bidirectional data bus
q Low operating and standby current

q Full military operating temperature range, -55oC to 125+oC,

screened to specific test methods listed in Table I MIL-STD­883 Method 5004 for Class S or Class B

q Radiation-hardened process and design; total dose irradiation

testing to MIL-STD-883 Method 1019

- Total-dose: 1.0E6 rads(Si)

- Dose rate upset: 1.0E9 rads (Si)/sec

- Dose rate survival: 1.0E12 rads (Si)/sec

- Single-event upset: <1.0E-10 errors/bit-day

q Industry standard (JEDEC) 64K SRAM pinout
q Packaging options:

- 28-pin 100-mil center DIP (.600 x 1.2)

- 28-pin 50-mil center flatpack (.700 x .75)

q 5-volt operation
q Post-radiation AC/DC performance characteristics

guaranteed by MIL-STD-883 Method 1019 testing at

1.0E6 rads(Si)

INTRODUCTION

The UT67164 SRAM is a high performance, asynchronous,
radiation-hardened, 8K x 8 random access memory
conforming to industry-standard fit, form, and function. The
UT67164 SRAM features fully static operation requiring no
external clocks or timing strobes. UTMC designed and
implemented the UT67164 using an advanced radiation­hardened twin-well CMOS process. Advanced CMOS
processing along with a device enable/disable function
result in a high performance, power-saving SRAM. The
combination of radiation-hardness, fast access time, and low
power consumption make UT67164 ideal for high-speed
systems designed for operation in radiation environments.

INPUT

DRIVERS

256 x 256

MEMORY ARRAY

COLUMN

I/O

Figure 1. SRAM Block Diagram

INPUT

DRIVERS

A(4:0)

INPUT

DRIVERS

A(12:5)

ROW

DECODERS

OUTPUT ENABLE

E2

W

G

E1

CHIP ENABLE

OUTPUT

DRIVERS

DATA

WRITE

CIRCUIT

DATA

READ

CIRCUIT

DQ(7:0)

COLUMN

DECODERS

WRITE ENABLE

Standard Products

UT67164 Radiation-Hardened 8K x 8 SRAM -- SEU Hard

Data Sheet

January 2002

2

PIN NAMES

DEVICE OPERATION

The UT67164 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable (G); 13
address inputs, A(12:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 are device enable inputs that control device
selection, active, and standby modes. Asserting both E1 and E2
enables the device, causes I

DD

to rise to its active value, and

decodes the 13 address inputs to select one of 8,192 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of W greater than V

IH

(min), E1 less than V

IL

(max), and E2 greater than V

IH

(min) defines a read cycle. Read

access time is measured from the latter of device enable, Output
Enable, or valid address to valid data output.

Read Cycle 1, the Address Access read in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified t

AVQV

is satisfied. Outputs remain

active throughout the entire cycle. As long as device enable and
output enable are active, the address inputs may change at a rate
equal to the minimum read cycle time (t

AVAV

).

Figure 3b shows Read Cycle 2, the Chip Enable-controlled
Access. For this cycle, G remains asserted, W remains
deasserted, and the addresses remain stable for the entire cycle.
After the specified t

ETQV

is satisfied, the eight-bit word
addressed by A(12:0) is accessed and appears at the data outputs
DQ(7:0).

Figure 3c shows Read Cycle 3, the Output Enable-controlled
Access. For this cycle, E1 and E2 are asserted, W is deasserted,
and the addresses are stable before G is enabled. Read access
time is t

GLQV

unless t

AVQV

or t

ETQV

have not been satisfied.

A(12:0) Address W Write

DQ(7:0) Data Input/Output G Output Enable

E1 Enable 1 V

DD

Power

E2

1

Enable 2 V

SS

Ground

1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15

Figure 2. SRAM Pinout

NC

A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2

Vss

VDD
W

E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3

G W E1

E2

I/O Mode Mode

X1

X X 0 3-state Standby

X X 1 X 3-state Standby
X 0 0 1 Data in Write

1 1 0 1 3-state

Read

2

0 1 0 1 Data out Read

3

WRITE CYCLE

A combination of W less than VIL(max), E1 less than VIL(max),
and E2 greater than VIH(min) defines a write cycle. The state of
G is a “don’t care” for a write cycle. The outputs are placed in

the high-impedance state when either G is greater than
VIH(min), or when W is less than VIL(max).

Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by t

WLWH

when the write is initiated by W, and by t

ETWH

when the write

is initiated by the latter of E1 or E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
user must wait t

WLQZ

before applying data to the eight

bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in

figure 4b, is defined by a write terminated by the latter of E1 or
E2 going inactive. The write pulse width is defined by t

WLEF

when the write is initiated by W, and by t

ETEF

when the write

is initiated by the latter of E1 or E2 going active. For the W
initiated write, unless the outputs have been previously placed
in the high-impedance state by G, the user must wait t

WLQZ

before applying data to the eight bidirectional pins DQ(7:0) to
avoid bus contention.

RADIATION HARDNESS

The UT67164 SRAM incorporates special design and layout
features which allow operation in high-level radiation
environments.

Table 2. Radiation Hardness

Design Specifications

1

Notes:

1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.

2. 90% Adam’s worst case spectrum (-55oC to 125+oC).

Total Dose 1.0E6 rads(Si)

Dose Rate Upset

1.0E9 rads(Si)/s 20ns pulse

Dose Rate Survival 1.0E12 rads(Si)/s 20ns pulse

Single-Event Upset 1.0E-10

errors/bit day

2

Neutron Fluencs 3.0E14

n/cm

2

Table 3. SEU versus Temperature

SEU

errors/bit-day

10

-4

10

-6

10

-8

10

-10

10

-10

10

-13

10

-11

10

-1210-13

10

-14

10

-16

-55 -35 -15 5 25 45 65 85 105 125

Temperature (oC)

4

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.5 to 7.0V

V

I/O

Voltage on any pin -0.5 to V

DD

+ 0.5

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.0W

T

J Maximum junction temperature

+150°C

Θ

JC

Thermal resistance, junction-to-case

2

10°C/W

I

LU

Latchup immunity +/-150mA

I

I

DC input current

+/-10 mA

SYMBOL PARAMETER LIMITS UNITS

V

DD

Positive supply voltage 4.5 to 5.5V V

T

C

Case temperature range -55 to +125°C

o

C

V

IN

DC input voltage 0V to V

DD

V

5

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 5.0V±10%; -55°C <Tc < +125°C)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage 2.2 V

V

IL

Low-level input voltage 0.8 V

V

OL

Low-level output voltage IOL = +/- 4.0mA, VDD = 4.5V 0.4 V

V

OH

High-level output voltage IOH = +/-4mA, VDD = 4.5V 2.4 V

C

IN

1

Input capacitance ƒ = 1MHz @ 0V, VDD = 4.5V 15 pF

C

IO

1

Bidirectional I/O capacitance ƒ = 1MHz @ 0V, VDD = 4.5V 20 pF

I

IN

Input leakage current VIN = VDD and V

SS

-10 +10 µA

I

OZ

Three-state output leakage current VO = VDD and V

SS

VDD = 5.5V
G = 5.5V

-10 +10 µA

I

OS

2, 3

Short-circuit output current VDD = 5.5V, VO = V

DD

VDD = 5.5V, VO = 0V

-90

+90 mA

mA

IDD(OP)

Supply current operating @1MHz CMOS inputs (I

OUT

= 0)

VDD = 5.5V

40 mA

IDD(SB)

pre-rad

Supply current standby CMOS inputs (I

OUT

= 0)

E1 = V

DD

- 0.5, V

DD

= 5.5V

200 µA

IDD(SB)

post-rad

Supply current standby
@ f = 0Hz

CMOS inputs (I

OUT

= 0)
CS1 = negated VDD = 5.5V
CS2 = negated

3 mA