UTMC 5962R0254301VXC, 5962R0254301VXA, 5962R0254301QXC, 5962R0254301QXA, 5962H0254301VXC Datasheet
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UT54ACS162245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver
Datasheet
March 12, 2003
FEATURES
• Voltage translation
- 3.3V bus to 2.5V bus
- 2.5V bus to 3.3V bus
• Cold sparing all pins
• 0.25µ Commercial RadHardTM CMOS
- Total dose: 300Krad(Si) and 1Mrad(Si)
- Single Event Latchup immune
• High speed, low power consumption
• Schmitt trigger inputs to filter noisy signals
• Cold and Warm Spare - all outputs
• Available QML Q or V processes
• Standard Microcircuit Drawing 5962-02543
• Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACS162245S MultiPurpose low voltage
transceiver is built using Aeroflex UTMC’s Commercial
RadHard
TM
epitaxial CMOS technology and is ideal for space
applications. This high speed, low power UT54ACS162245S
low voltage transceiver is designed to perform multiple functions including: asynchronous two-way communication,
Schmitt input buffering, voltage translation, warm and cold
sparing. With V
DD
equal to zero volts, the UT54ACS162245S
outputs and inputs present a minimum impedance of 1MΩ making it ideal for "cold spare" applications. Balanced outputs and
low "on" output impedance make the UT54ACS162245S well
suited for driving high capacitance loads and low impedance
backplanes. The UT54ACS162245S enables system designers
to interface 2.5 volt CMOS compatible components with 3.3
volt CMOS components. For voltage translation, the A port interfaces with the 2.5 volt bus; the B port interfaces with the 3.3
volt bus. The direction control (DIRx) controls the direction of
data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from
either port A or B. The direction and output enable controls
operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver.
LOGIC SYMBOL
PIN DESCRIPTION
Pin Names Description
OEx Output Enable Input (Active Low)
DIRx Direction Control Inputs
xAx Side A Inputs or 3-State Outputs (2.5V Port)
xBx Side B Inputs or 3-State Outputs (3.3V Port)
(48)
OE1
G2
(47)
1A1
(46)
1A2
(44)
(2)
1B1
(5)
(3)
1B2
1A3
(43)
1A4
(41)
1A5
(40)
1A6
1B3
(9)
1B6
(8)
1B5
(6)
1B4
(38)
1A7
(37)
1A8
(12)
1B8
(11)
1B7
(1)
DIR1 1EN1 (BA)
1EN2 (AB)
11
12
(25)OE2
G1
(24)
DIR2
21
22
(36)
2A1 2B1
(13)
(35)
2A2
(33)
2A3
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
(16)
2B2
2B3
(20)
2B6
(19)
2B5
(17)
2B4
(23)
2B8
(22)
2B7
(14)
2EN1 (BA)
2EN2 (AB)
2
PINOUTS POWER TABLE
When V
DD2
is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic
levels can be applied to all control inputs. For proper operation
connect power to all VDD and ground all VSS pins (i.e., no floating VDD or VSS input pins). Tie unused inputs to VSS. Always
insure V
DD1
> V
DD2
during operation of the part.
FUNCTION TABLE
COLD/WARM SPARE FUNCTION
The device will place all outputs into a high-impedance state if
either VDD supply is taken to zero volts (IWS, warm spare), or
if both VDD supplies are set to zero volts (ICS, cold spare).
DEVICE POWER UP FUNCTION
The device will place all outputs into a high-impedance during
power-up. The high impedance state is maintained for a time
period approximately equal to the rise time of V
DD1
.
1
2
3
4
5
7
6
48
47
46
45
44
42
43
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
OE1
1A1
1A2
V
SS
1A3
VDD2
8 41
1B5
1A5
1A4
9 40
1B6
1A6
10 39
V
SS
V
SS
48-Lead Flatpack
Top View
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
11
12
13
14
15
17
16
18
19
20
V
SS
2B7
2B8
DIR2
21
22
23
24
38
37
36
35
34
32
33
1A7
1A8
2A1
2A2
V
SS
2A4
31 VDD2
2A3
30 2A5
29 2A6
28 V
SS
27 2A7
26 2A8
25
OE2
Port B Port A OPERATION
3.3 Volts 2.5 Volts Voltage Translator
3.3 Volts 3.3 Volts Non Translating
2.5 Volts 2.5 Volts Non Translating
ENABLE
OEx
DIRECTION
DIRx OPERATION
L L B Data To A Bus
L H A Data To B Bus
H X Isolation
3
LOGIC DIAGRAM
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1
(1)
(47)
(48)
(2)
(46)
(3)
(44)
(5)
(43)
(6)
(41)
(8)
(40)
(9)
(38)
(11)
(37)
(12)
1B1
1B2
1B3
1B6
1B5
1B4
1B8
1B7
OE1
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
DIR2
(24)
(36)
(25)
(13)
(35)
(14)
(33)
(16)
(32)
(17)
(30)
(19)
(29)
(20)
(27)
(22)
(26)
(23)
2B1
2B2
2B3
2B6
2B5
2B4
2B8
2B7
OE 2
2.5V PORT
3.3 V PORT
2.5V PORT
3.3 V PORT
4
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent to CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For Cold Spare mode (V
DD1
=VSS, V
DD2
=VSS), V
I/O
may be -0.3V to the maximum recommended operating level of V
DD1
+0.3V.
3. Maximum junction temperature may be increased to +175oC during burn-in and life test.
DUAL SUPPLY OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E5 rad(Si)
SEL Latchup >113
MeV-cm2/mg
Neutron Fluence
(Note 2)
1.0E14
n/cm
2
SYMBOL PARAMETER LIMIT (Mil only) UNITS
V
I/O
(Note 2)
Voltage any pin -.3 to V
DD1
+.3 V
V
DD1
Supply voltage -0.3 to 4.0 V
V
DD2
Supply voltage -0.3 to 4.0 V
T
STG
Storage Temperature range -65 to +150 °C
T
J
(Note 3)
Maximum junction temperature +150 °C
Θ
JC
Thermal resistance junction to case 20 °C/W
I
I
DC input current ±10 mA
P
D
Maximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
V
DD1
Supply voltage 2.3 to 3.6 V
V
DD2
Supply voltage 2.3 to 3.6 V
V
IN
Input voltage any pin 0 to V
DD1
V
T
C
Temperature range -55 to + 125 °C
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