UTMC 5962R0153701VXC, 5962R0153701QXX, 5962R0153701QXC, 5962R0153701QXA, 5962H0153701VXX Datasheet

1

FEATURES

q 400.0 Mbps low jitter fully differential data path
q 200MHz clock channel
q 3.3 V power supply
q 10mA LVDS output drivers
q Input receiver fail-safe
q Cold sparing all pins
q Output channel-to-channel skew is 120ps max
q Configurable as quad 2:1 mux, 1:2 demux, repeater or1:2

signal splitter

q Fast propagation delay of 3.5ns max
q Receiver input threshold < + 100 mV
q Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si) and 1 Mrad(Si)

- Latchup immune (LET > 100 MeV-cm2/mg)

q Packaging options:

- 64-lead flatpack

q Standard Microcircuit Drawing 5962-01537

- QML Q and V compliant part

q Compatible with ANSI/TIA/EIA 644-1995 LVDS

Standard

INTRODUCTION

The UT54LVDM228 is a quad 2x2 crosspoint switch utilizing
Low Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The non-blocking design allows connection of
any input to any output or outputs on each switch. LVDS I/O
enable high speed data transmission for point-to point or multi­drop interconnects. This device can be used as a high speed
differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter. The mux and demux functions are useful for
switching between primary and backup circuits in fault tolerant
systems. The 1:2 signal splitter and 2:1 mux functions are useful
for distribution of a bus across several rack-mounted
backplanes.

The individual LVDS outputs can be put into Tri-State by use
of the enable pins.

All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.

Standard Products

UT54LVDM228 Quad 2x2 400 Mbps Crosspoint Switch

Data Sheet

August, 2002

Figure 1a. UT54LVDM228 Crosspoint Switch Block Diagram

(Partial - see Page 2 for complete diagram)

Out1+

En1
In1+

+

-

1

0

1

0

Out 2+

Sel1
En2

In2+

Sel2

+

-

In1-

Out1-

Out 2-

In2-

2

Out1+

En1
In1+

+

-

1

0

1

0

Out 2+

Sel1
En2

In2+

Sel2

Out3+

En3

In3+

1

0

1

0

Out4+

Sel3
En4

In4+

Sel4

Out5+

En5

In5+

1

0

1

0 Out6+

Sel5
En6

In6+

Sel6

Out7+

En7
In7+

1

0

1

0 Out8+

Sel7
En8

In8+

Sel8

Clk In+

Clk Out+

+

-

+

-

+

-

+

-

+

-

+

-

Figure 1b. UT54LVDM228 Crosspoint Switch Block Diagram

+

-

+

-

Skew
Match

In1-

Out1-

Out 2-

In2-

Out3-

In3-

In4-

Out4-

In5-

Out5-

In6-

Out6-

In7-

Out7-

In8-

Out8-

Clk In-

Clk Out-

ENCK

3

TRUTH TABLE

PIN DESCRIPTION

Figure 2. UT54LVDS228 Pinout

UT54LVDM228

Crosspoint

Switch

64
63

62

61
60

59

58
57

V

DD

1En1

2

3
4

5
6
7

8V

SS

9

10
11

12
13
14

15
16

V

DD

In4+

In4-

CLK In+

17
18
19

20
21
22

23
24

V

SS

In5+

In6+

In6-

Sel1

Out2+

56

55
54

53
52
51

50
49

Out4+

CLK Out+

Out3-

Sel4

48

47
46

45

44
43
42

41

Out6-

CLK Out-

Out5-

In1+

En2

In2+

In3+

In3-

En3

En4

ENCK

CLK In-

En5

In5-

En6

Out1+

Out1-

Sel2

Out2-

V

SS

Sel3

Out3+

Out4-

V

DD

Out5+

V

SS

Sel5

Sel6

Out6+

In7+

In7-

V

DD

V

SS

In8-

En8

En7

In8+

Out7+

V

DD

V

SS

Sel7

Out8-

Out7-

Sel8

Out8+

In1-

In2-

Out8-

Out5-

25
26
27

28
29
30

31
32

40
39
38
37

36
35

34
33

Sel1 Sel2 Out1 Out2 Mode

0 0 In1 In1 1:2 splitter
0 1 In1 In2 Repeater
1 0 In2 In1 Switch
1 1 In2 In2 1:2 splitter

Name # of Pins Description

In+ 8 Non-inverting LVDS input

In- 8 Inverting LVDS input

Out+ 8 Non-inverting LVDS output

Out- 8 Inverting LVDS Output

En 8 A logic low on the enable puts

the LVDS output into Tri-State

and reduces the supply current

ENCK 1 A logic low on the enable puts

the LVDS output into Tri-State

and reduces the supply current

Sel 8 2:1 mux input select

V

SS

6 Ground

V

DD

5 Power supply

CLK In+ 1 Non-Inverting Clock LVDS

Input

CLK In- 1 Inverting clock LVDS Input

CLK Out+ 1 Non-Inverting Clock LVDS

Output

CLK Out- 1 Inverting Clock LVDS Output

4

APPLICATIONS INFORMATION

The UT54LVDM228 provides three modes of operation. In
the 1:2 splitter mode, the two outputs are copies of the same
single input. This is useful for distribution / fan-out
applications. In the repeater mode, the device operates as a
9channel LVDS buffer. Repeating the signal restores the
LVDS amplitude, allowing it to drive another media segment.
This allows for isolation of segments or long distance
applications or buffers standard LVDS to 10mA multi-op
drivers.The switch mode provides a crosspoint function. This
can be used in a system when primary and redundant paths
are supported in a fault tolerant application.

The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of th e media, the noise coupling to the

environment, and other application specific characteristics.

Input Fail-Safe:

The UT54LVDM228 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.

PCB layout and Power System Bypass:

Circuit board layout and stack-up for the UT54LVDM228
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01µF to

0.1µ F. Tantalum capacitors may be in the range of 2.2µF to
10µF. Voltage rating for tantalum capacitors should be at
least 5X the power supply voltage being used. It is
recommended practice to use two vias at each power pin of
the UT54LVDM228, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.

The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.

Compatibility with LVDS standard:

In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50 Ω
differential impedance, the loading effects may reduce this
to the 35Ω range depending upon spacing and capacitance
load. Terminating the line with a 35Ω load is a better match
than with 50Ω and reflections are reduced.

5

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and life test.

3. Test per MIL-STD-883, Method 1012.

4. For Cold Spare mode (VDD=VSS), V

I/O

may be -0.3V to the maximum recommended operating VDD + 0.3V.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.3 to 4.0V

V

I/O

4

Voltage on any pin -0.3 to (VDD + 0.3V)

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 800mW

T

J Maximum junction temperature

2

+150°C

Θ

JC Thermal resistance, junction-to-case

3

22°C/W

I

I

DC input current

±10mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 3.3 to 3.6V

T

C

Case temperature range -55 to +125°C

V

IN

DC input voltage, receiver inputs 0 to 2.4V

DC input voltage, logic inputs 0 to VDD for EN, SEL