UTMC 5962R-9583302VXX, 5962R-9583302VXC, 5962R-9583302VXA, 5962R-9583302QXX, 5962R-9583302QXC Datasheet

FEATURES

q >155.5 Mbps (77.7 MHz) switching rates
q +340mV nominal differential signaling
q 5 V power supply
q TTL compatible inputs
q Ultra low power CMOS technology
q 5.0ns maximum, propagation delay
q 3.0ns maximum, differential skew
q Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si) and 1Mrad(Si)

- Latchup immune (LET > 111 MeV-cm2/mg)

q Packaging options:

- 16-lead flatpack (dual in-line)

q Standard Microcircuit Drawing 5962-95833

- QML Q and V compliant part

q Compatible with IEEE 1596.3SCI LVDS
q Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard

INTRODUCTION

The UT54LVDS031 Quad Driver is a quad CMOS
differential line driver designed for applications requiring
ultra low power dissipation and high data rates. The device
is designed to support data rates in excess of 155.5 Mbps
(77.7 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.

The UT54LVDS031 accepts TTL input levels and translates
them to low voltage (340mV) differential output signals. In
addition, the driver supports a three-state function that may
be used to disable the output stage, disabling the load
current, and thus dropping the device to an ultra low idle
power state.

The UT54LVDS031 and companion quad line receiver
UT54LVDS032 provide new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.

D1

D2

D3

D4

D

OUT1+

D

OUT1-

D

OUT2+

D

OUT2-

D

OUT3+

D

OUT3-

D

OUT4+

D

OUT4-

D

IN1

D

IN2

D

IN4

D

IN3

EN
EN

Standard Products

UT54LVDS031 Quad Driver

Data Sheet

June 7, 2000

Figure 1. UT54LVDS031 Quad Driver Block Diagram

2

TRUTH TABLE

PIN DESCRIPTION

APPLICATIONS INFORMATION

The UT54LVDS031 driver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media such as a
standard twisted pair cable, a parallel pair cable, or simply PCB
traces. Typically, the characteristic impedance of the media is
in the range of 100Ω. A termination resistor of 100Ω should be
selected to match the media and is located as close to the receiver
input pins as possible. The termination resistor converts the
current sourced by the driver into voltages that are detected by
the receiver. Other configurations are possible such as a multi­receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.

The UT54LVDS031 differential line driver is a balanced current
source design. A current mode driver, has a high output
impedance and supplies a constant current for a range of loads
(a voltage mode driver on the other hand supplies a constant
voltage for a range of loads). Current is switched through the
load in one direction to produce a logic state and in the other
direction to produce the other logic state. The current mode
requires (as discussed above) that a resistive termination be
employed to terminate the signal and to complete the loop as
shown in Figure 3. AC or unterminated configurations are not
allowed. The 3.4mA loop current will develop a differential
voltage of 340mV across the 100Ω termination resistor which
the receiver detects with a 240mV minimum differential noise
margin neglecting resistive line losses (driven signal minus
receiver threshold (340mV - 100mV = 240mV)). The signal is
centered around +1.2V (Driver Offset, VOS) with respect to

ground as shown in Figure 4. Note: The steady-state voltage
(VSS) peak-to-peak swing is twice the differential voltage (VOD)

and is typically 680mV.

Enables Input Output

EN EN D

IN

D

OUT+

D

OUT-

L H X Z Z

All other combinations

of ENABLE inputs

L L H
H H L

Pin No. Name Description

1, 7, 9, 15 D

IN

Driver input pin, TTL/CMOS

compatible

2, 6, 10, 14 D

OUT+

Non-inverting driver output pin,

LVDS levels

3, 5, 11, 13 D

OUT-

Inverting driver output pin,

LVDS levels

4 EN Active high enable pin, OR-ed

with EN

12 EN Active low enable pin, OR-ed

with EN

16 V

DD

Power supply pin, +5V + 10%

8 V

SS

Ground pin

Figure 2. UT54LVDS031 Pinout

UT54LVDS031

Driver

16
15

14
13

12
11

10

9

V

DD

D

IN4

D

OUT4+

D

OUT4-

EN
D

OUT3-

D

OUT3+

D

IN3

1

D

IN1

2D

OUT1+

3

D

OUT1-

4EN
5

D

OUT2-

6

D

OUT2+

7

D

IN2

8

V

SS

ENABLE

DATA

INPUT

1/4 UT54LVDS031

1/4 UT54LVDS032

+

-

DATA

OUTPUT

Figure 3. Point-to-Point Application

RT 100Ω

3

The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases
exponentially in most cases between 20 MHz - 50 MHz. This is
due to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current mode
driver switches a fixed current between its output without any
substantial overlap current. This is similar to some ECL and
PECL devices, but without the heavy static ICC requirements of

the ECL/PECL design. LVDS requires 80% less current than
similar PECL devices. AC specifications for the driver are a
tenfold improvement over other existing RS-422 drivers.

The Three-State function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.

D

IN

D

OUT-

D

OUT+

SINGLE-ENDED

D

OUT+

- D

OUT-

DIFFERENTIAL OUTPUT

V

0D

3V

0V

V

OH

V

OS

V

OL

+V

OD

-V

OD

0V

0V (DIFF.)

V

SS

Figure 4. Driver Output Levels

Note: The footprint of the UT54LVDS031 is the same as the in-

dustry standard Quad Differential (RS-422) Driver.

4

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.3 to 6.0V

V

I/O

Voltage on any pin -0.3 to (VDD + 0.3V)

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.25 W

T

J Maximum junction temperature

2

+150°C

Θ

JC Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 4.5 to 5.5V

T

C

Case temperature range -55 to +125°C

V

IN

DC input voltage 0V to V

DD

5

DC ELECTRICAL CHARACTERISTICS

1, 2

(VDD = 5.0V +10%; -55°C < TC < +125°C)

Notes:

1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.

2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

3. Guaranteed by characterization.

4. Devices are tested @ V

DD

= 5.5V only.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage (TTL) 2.0 V

DD

V

V

IL

Low-level input voltage (TTL) V

SS

0.8 V

V

OL

Low-level output voltage RL = 100Ω 0.90 V

V

OH

High-level output voltage RL = 100Ω 1.60 V

I

IN

4

Input leakage current VIN = V

DD

-10 +10 µA

V

OD

1

Differential Output Voltage

RL = 100Ω

(figure 5)

250 400 mV

∆V

OD

1

Change in Magnitude of VOD for
Complementary Output States

RL = 100Ω

(figure 5)

10 mV

V

OS

Offset Voltage

RL = 100Ω,

1.125

1.375 V

∆V

OS

Change in Magnitude of VOS for
Complementary Output States

RL = 100Ω

(figure 5)

25 mV

V

CL

3

Input clamp voltage ICL = -18mA -1.5 V

I

OS

3

Output Short Circuit Current

V

OUT

= 0V

2

5.0 mA

I

OZ

4

Output Three-State Current EN = 0.8V and EN = 2.0 V,

V

OUT

= 0V or V

DD

-10 +10 µΑ

I

CCL

4

Loaded supply current drivers
enabled

RL = 100Ω all channels
VIN = VDD or VSS(all inputs)

25.0

mA

I

CCZ

4

Loaded supply current drivers
disabled

DIN = VDD or V

SS

EN = VSS, EN = V

DD

10.0

mA

Vos

Voh Vol+

2

---------------------------=





6

Figure 5. Driver VOD and VOS Test Circuit or Equivalent Circuit

D

D

IN

D

OUT-

D

OUT+

20pF

Driver Enabled

Generator

50Ω

RL = 100Ω

V

OD

20pF

7

AC SWITCHING CHARACTERISTICS

1, 2, 3, 4

(VDD = +5.0V + 10%, TA = -55 °C to +125 °C)

Notes:

1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.

2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr < 6 ns, and tf < 6 ns.

3. CL includes probe and jig capacitance.

4. Guaranteed by characterization

5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.

SYMBOL PARAMETER MIN MAX UNIT

t

PHLD

Differential Propagation Delay High to Low
(figures 6 and 7)

0.5 5.0 ns

t

PLHD

Differential Propagation Delay Low to High
(figures 6 and 7)

0.5 5.0 ns

t

SKD

4

Differential Skew (t

PHLD

- t

PLHD

) (figures 6 and 7) 0 3.0 ns

t

SK1

4

Channel-to-Channel Skew1 (figures 6 and 7)

0 3.0 ns

t

SK2

4

Chip-to-Chip Skew5 (figure 6 and 7)

4.5 ns

t

TLH

4

Rise Time (figures 6 and 7) 2.0 ns

t

THL

4

Fall Time (figures 6 and 7) 2.0 ns

t

PHZ

4

Disable Time High to Z (figures 8 and 9) 10 ns

t

PLZ

4

Disable Time Low to Z (figures 8 and 9) 10 ns

t

PZH

4

Enable Time Z to High (figures 8 and 9) 10 ns

t

PZL

4

Enable Time Z to Low (figures 8 and 9) 10 ns

8

D

D

IN

D

OUT-

D

OUT+

Driver Enabled

Generator

50Ω

RL = 100Ω

Figure 6. Driver Propagation Delay and Transition Time Test Circuit or Equivalant Circuit

20pF

20pF

D

IN

D

OUT-

D

OUT+

V

DIFF

t

PHLD

V

DD

0V

V

OH

V

OL

0V

V

DIFF

= D

OUT+

- D

OUT-

0V (Differential)

1.25V

t

THL

20%

80%

0V

20%

80%

t

TLH

t

PLHD

1.25V

Figure 7. Driver Propagation Delay and Transition Time Waveforms

9

D

V

DD

V

SS

D

IN

EN

Generator

50Ω

EN

50Ω

50Ω

D

OUT+

D

OUT-

+1.2V

Figure 8. Driver Three-State Delay Test Circuit or Equivalant Circuit

20pF

20pF

EN when EN = V

DD

EN when EN = V

SS

or

D

OUT+

when DIN =V

DD

D

OUT-

when DIN = V

SS

D

OUT+

when DIN = V

SS

D

OUT-

when DIN = V

DD

t

PLZ

t

PZL

50%

50%

V

OL

1.2V

1.2V

V

OH

0V

V

DD

0V

V

DD

1.25V

1.25V

1.25V

1.25V

50%

t

PZH

t

PHZ

Figure 9. Driver Three-State Delay Waveform

10

Notes:

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance to MIL-PRF-38535.

4. Package dimensions and symbols are similar to MIL-STD-1835 variation F-5A.

5. Lead position and coplanarity are not measured.

6. ID mark symbol is vendor option.

7. With solder, increase maximum by 0.003.

Figure 10. 16-pin Ceramic Flatpack

PACKAGING

11

ORDERING INFORMATION
UT54LVDS031 QUAD DRIVER:

UT 54LVDS031 - * * * * *

Device Type:
UT54LVDS031 LVDS Driver

Access Time:
Not applicable

Package Type:
(U) = 16-lead Flatpack (dual-in-line)

Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither

tested nor guaranteed.

4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.

Radiation neither tested nor guaranteed.

12

UT54LVDS031 QUAD DRIVER: SMD

5962 -

* * *

Federal Stock Class Designator: No Options

Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)

Drawing Number: 95833

Device Type
02 = LVDS Driver

Class Designator:
(Q) = QML Class Q
(V) = QML Class V

Case Outline:
(X) = 16 lead Flatpack (dual-in-line)

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)

95833

**

Notes:

1.Lead finish (A,C, or X) must be specified.

2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.