UTMC 5962R-0153402VXX, 5962R-0153402VXC, 5962R-0153402VXA, 5962R-0153402QXX, 5962R-0153402QXC Datasheet

1

FEATURES

q 15 to 75 MHz shift clock support
q Low power consumption
q Power-down mode <216µW (max)
q Cold sparing all pins
q Narrow bus reduces cable size and cost
q Up to 1.575 Gbps throughput
q Up to 197 Megabytes/sec bandwidth
q 325 mV (typ) swing LVDS devices for low EMI
q PLL requires no external components
q Rising edge strobe
q Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si) and 1 Mrad(Si)

- Latchup immune (LET > 100 MeV-cm2/mg)

q Packaging options:

- 48-lead flatpack

q Standard Microcircuit Drawing 5962-01534

- QML Q and V compliant part

q Compatible with TIA/EIA-644 LVDS standard

INTRODUCTION

The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel
with the data streams over a fourth LVDS link. Every cycle of
the transmit clock 21 bits of input data are sampled and
transmitted.

At a transmit clock frequency of 75MHz, 21 bits of TTL data
are transmitted at a rate of 525 Mbps per LVDS data channel.
Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197
Mbytes/sec).

The UT54LVDS217 Serializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.

All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.

Standard Products

UT54LVDS217 Serializer

Data Sheet

June, 2003

TTL PARALLEL-TO-LVDS

PLL

POWER DOWN

TRANSMIT CLOCK IN

CMOS/TTL INPUTS

21

DATA (LVDS)

CLOCK (LVDS)

TTL PARALLEL -TO-

Figure 1. UT54LVDS217 Serializer Block Diagram

2

PIN DESCRIPTION

Figure 2. UT54LVDS217 Pinout

UT54LVDS217

48
47

46

45
44

43

42
41

N/C

LVDS GND

1TxIN4

2V

DD

3
4

5GND
6
7

8V

DD

9

10
11

12
13
14

15
16

TxIN6

TxIN5

TxIN7

TxIN8

TxIN9

TxIN10

GND

TxIN11

TxIN12

V

DD

TxIN13
TxIN14

17
18
19

20
21
22
23

24

TxIN15

TxIN17

TxIN16

V

DD

TxIN19

TxIN18

GND

GND

TxIN3
TxIN2

GND

TxIN1

TxIN0

TxOUT0-

40

39
38

37
36
35

34
33

TxOUT0+

TxOUT1-

LVDS GND

TxCLK OUT-

TxOUT1+

TxOUT2-

LVDS V

DD

TxOUT2+

32

31
30

29

28
27
26

25

PWR DWN

TxCLK IN

TxIN20

TxCLK OUT+
LVDS GND
PLL GND

PLL V

DD

PLL GND

Pin Name I/O No.

Description

TxIN I 21

TTL level input

TxOUT+ O 3

Positive LVDS differential data output

TxOUT- O 3

Negative LVDS differential data output

TxCLK IN I 1

TTL level clock input. The rising edge acts
as data strobe. Pin name TxCLK IN

TxCLK
OUT+

O 1

Positive LVDS differential clock output

TxCLK OUT- O 1

Negative LVDS differential clock output

PWR DWN I 1

TTL level input. Assertion (low input) TRI­STATEs the clock and data outputs, ensur­ing low current at power down.

V

DD

I 4

Power supply pins for TTL inputs and logic

GND I 5

Ground pins for TTL inputs and logic

PLL V

DD

I 1

Power supply pins for PLL

PLL GND I 2

Ground pins for PPL

LVDS V

DD

I 1

Power supply pin for LVDS output

LVDS GND I 3

Ground pins for LVDS outputs

TxIN

UT54LVDS217

0
1
2

CMOS/
TTL

18
19
20

TxCLK

PCB

RxOUT

UT54LVDS218

0
1
2

18
19
20

RxCLK

PCB

SHIELD

GND

CLOCK
(LVDS)

DATA
(LVDS)

LVDS CABLE

MEDIA DEPENDENT

Figure 3. UT54LVDS217 Typical Application

3

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and lifetest.

3. Test per MIL-STD-883, Method 1012.

4. For cold spare mode (VDD = VSS), V

I/O

may be 0.3V to the maximum recommended operating VDD + 0.3V.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.3 to 4.0V

V

I/O Voltage on any pin

4

-0.3 to (VDD + 0.3V)

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 2 W

T

J Maximum junction temperature

2

+150°C

Θ

JC Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10mA

SYMBOL PARAMETER LIMITS

V

DD, PLLVDD,

LVDS V

DD

Positive supply voltage 3.0 to 3.6V

T

C

Case temperature range -55 to +125°C

V

IN

DC input voltage 0V to V

DD

4

DC ELECTRICAL CHARACTERISTICS

1

(VDD = 3.3V-0.3V; -55°C < TC < +125°C)

Notes:

1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenc ed to ground.

2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.

3. Guaranteed by characterization.

4. Devices are tested @ 3.6V only.

5. Clock outputs guaranteed by design.

6. Post 100Krad and 300Krad, I

CCZ

= 200µA.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

CMOS/TTL DC SPECIFICATIONS

V

IH

High-level input voltage 2.0 V

DD

V

V

IL

Low-level input voltage GND 0.8 V

I

IH

High-level input current VIN = 3.6V; VDD = 3.6V -10 +10 µA

I

IL

Low-level input current

VIN = 0V; VDD = 3.6V

-10 +10 µA

V

CL

Input clamp voltage ICL = -18mA -1.5 V

I

CS

Cold Spare Leakage current VIN = 3.6V; VDD = V

SS

-20 +20 µA

LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)

V

OD

5

Differential Output Voltage RL = 100Ω (See Figure 14)

250

400 mV

∆V

OD

5

Change in VOD between
complimentary output states

RL = 100Ω (See Figure 14) 35 mV

V

OS

5

Offset Voltage

RL = 100Ω,

1.120

1.410 V

∆V

OS

5

Change in VOS between
complimentary output states

RL = 100Ω 35 mV

I

OZ

4

Output Three-State Current PWR DWN = 0V

V

OUT

= 0V or V

DD

-10 +10 µΑ

I

CSOUT

Cold Spare Leakage Current VIN=3.6V, VDD = V

SS

-20 +20 µΑ

I

OS

2,3

Output Short Circuit Current

V

OUT

+ or V

OUT

-

= 0V

5mA mA

Supply Current

I

CCL

4

Transmitter supply current with
loads

RL = 100Ω all channels

(figure 4)

CL = 5pF, f = 50MHz

65.0 mA

I

CCZ

4,6

Power down current DIN = V

SS

PWR DWN = 0V, f = 0Hz

60.0 µA

Vos

Voh Vol

+

2

---------------------------

=





5

AC SWITCHING CHARACTERISTICS

1

(VDD = 3.0V to 3.6V; TA = -55°C to +125°C)

Notes:

1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6).

2. Guaranteed by characterization.

3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit.

4. Guaranteed by design.

SYMBOL PARAMETER MIN MAX UNIT

LLHT

2

LVDS Low-to-High Transition Time (Figure 5) 1.5 ns

LHLT

2

LVDS High-to-Low Transition Time (Figure 5) 1.5 ns

TPPos0

2

Transmitter Output Pulse Position for Bit 0 (Figure 13) -0.18 0.270 ns

TPPos1

2

Transmitter Output Pulse Position for Bit 1(Figure 13) 1.72 2.17 ns

TPPos2

2

Transmitter Output Pulse Position for Bit 2 (Figure 13) 3.63 4.08 ns

TPPos3

2

Transmitter Output Pulse Position for Bit 3 (Figure 13) 5.53 5.98 ns

TPPos4

2

Transmitter Output Pulse Position for Bit 4 (Figure 13)

7.44

7.89 ns

TPPos5

2

Transmitter Output Pulse Position for Bit 5 (Figure 13) 9.34 9.79 ns

TPPos6

2

Transmitter Output Pulse Position for Bit 6 (Figure 13) 11.25 11.70 ns

TCCS

3

Channel to Channel skew (Figure 7) 0.45 ns

TCIP TxCLK IN Period (Figure 8) 13.3 66.7 ns

TCIH

4

TxCLK IN High Time (Figure 8) 0.35Tcip 0.65Tcip ns

TCIL

4

TxCLK IN Low Time (Figure 8) 0.35Tcip 0.65Tcip ns

TSTC

2

TxIN Setup to TxCLK IN (Figure 8) 1.0

0.5

ns

THTC

2

TxIN Hold to TxCLK IN (Figure 8) 0.7

0.5

ns

TCCD TxCLK IN to TxCLK OUT Delay (Figure 9) 0.5 2.5 ns

TPLLS Transmitter Phase Lock Loop Set (Figure 10) 10 ms

TPDD Transmitter Powerdown Delay (Figure 12) 100 ns

f=75MHz

f=75MHz

f=75MHz
f=75MHz

f=75MHz

f=75MHz
f=75MHz

15MHz
75MHz
15MHz
75MHz

6

AC TIMING DIAGRAMS

TxCLK IN

TxIN

Figure 4. Test Pattern

80%

LLHT LHLT

Vdiff

Vdiff=(TxOUT+) - (TxOUT-)

20%

80%

20%

TxOUT+

100Ω

TxOUT-

5pF

Figure 5. UT54LVDS217 Output Load and Transition Times

90%

TCIT

10%

90%

10%

TXCLK IN

TCIT

Figure 6. UT54LVDS217 Input Clock Transition Time

T

7

TxOUT0

TxOUT1

TxOUT2

TxCLK OUT

TCCS

Vdiff=
0V

TIME

Figure 7. UT54LVDS217 Channel-to-Channel Skew

TxCLK OUT

Vdiff=
0V

TxCLK IN

TCCD

VDD/2

TCIL

TCIP

TCIH

TxCLK IN

VDD/2

TSTC THTC

HOLDSETUP

TxIN 0-20

Figure 8. UT54LVDS217 Setup/Hold and High/Low Times

Figure 9. UT54LVDS217 Clock-to-Clock Out Delay

Notes:

1. Measurements at V

DIFF

= 0V

2. TCCS measured between earliest and latest LVDS edges.

3. TxCLK Differential Low-High Edge.

Sample on L-H Edge

VDD/2

VDD/2

VDD/2 VDD/2

8

POWER DOWN

V

DD

TPLLS

TxCLK IN

TxCLK OUT /

RxCLK IN

Vdiff =
OV

VDD/2

Figure 10. UT54LVDS217 Phase Lock Loop Set Time

TxCLK OUT /

RxCLK IN

Previous Cycle Next Cycle

TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14

TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7

TxIN1-1 TxIN0-1 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0

TxOUT2 /

RxIN2

TxOUT1 /

RxIN1

TxOUT0 /

RxIN0

Figure 11. UT54LVDS217 Parallel TTL Data Inputs Mapped to LVDS Outputs

VDD/2

V

DD

V

DD

9

POWER DOWN

TxCLK IN

TxOUT

THREE-STATE

TPDD

Figure 12. Transmitter Powerdown Delay

TxCLK OUT /

Differential

Previous Cycle Next Cycle

TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14

TxIN8-1 TxIN7-1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7

TxIN1-1 TxIN0-1 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0

TxOUT2 /

(Single ended)

TxOUT1 /

Single ended

TxOUT0 /

Single ended

TPPos0
TPPos1

TPPos2

TPPos3

TPPos4

TPPos5

TPPos6

Figure 13. LVDS Output Pulse Position Measurement

T

CLK

VDD/2

10

Figure 14. Driver VOD and VOS Test Circuit or Equivalent Circuit

D

D

IN

D

OUT-

D

OUT+

20pF

Driver Enabled

Generator

50Ω

RL = 100Ω

V

OD

20pF

11

PACKAGING

Figure 15. 48-Lead Flatpack

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance with MIL-PRF-38535.

4. Lead position and colanarity are not measured.

5. ID mark symbol is vendor option.

6. With solder, increase maximum by 0.003.

6 4

5

6

12

ORDERING INFORMATION

UT54LVDS217 Serializer:

UT 54LVDS217 - * * * * *

Device Type:
UT54LVDS217 Serializer

Access Time:
Not applicable

Package Type:
(U) = 48-lead Flatpack (dual-in-line)

Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither

tested nor guaranteed.

4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.

Radiation neither tested nor guaranteed.

13

UT54LVDS217 Serializer: SMD

5962 -

* * *

Federal Stock Class Designator: No Options

Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si) (contact factory for availability)
(H) = 1E6 rad(Si) (contact factory for availability)

Drawing Number: 01534

Device Type
01 = 50MHz LVDS Serializer (contacat factory)
02 = 75MHz LVDS Serializer

Class Designator:
(Q) = QML Class Q
(V) = QML Class V

Case Outline:
(X) = 48 lead Flatpack (dual-in-line)

Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)

01534

**

Notes:

1.Lead finish (A,C, or X) must be specified.

2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.