UTMC 5962P0053604TXX, 5962P0053604TXC, 5962P0053604TXA, 5962P0053604TUX, 5962P0053604TUC Datasheet

FEATURES

q 20ns maximum (5 volt supply) address access time
q Asynchronous operation for compatibility with industry-

standard 512K x 8 SRAMs

q TTL compatible inputs and output levels, three-state

bidirectional data bus

q Typical radiation performance

- Total dose: 50krads

- >100krads(Si), for any orbit, using Aeroflex UTMC
patented shielded package

- SEL Immune >80 MeV-cm2/mg

- LETTH(0.25) = >10 MeV-cm2/mg

- Saturated Cross Section (cm2) per bit, 5.0E-9

-<1E-8 errors/bit-day, Adams to 90% geosynchronous

heavy ion

q Packaging options:

- 36-lead ceramic flatpack (weight 3.42 grams)

- 36-lead flatpack shielded (weight 10.77 grams)

q Standard Microcircuit Drawing 5962-00536

- QML T and Q compliant part

INTRODUCTION

The QCOTSTM UT9Q512 Quantified Commercial Off-the­Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power

consumption by more than 90% when deselected .

Writing to the devic e i s accomplished by taking Chip Enable
one (E) input LOW and Write Enable (W) inputs LOW.
Data on the eight I/O pins (DQ0 through DQ7) is then written

into the location specified on the address pins (A0 through
A18). Reading from the device is accomplished by taking
Chip Enable one (E) and Output Enable (G) LOW while

forcing Write Enable ( W) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.

The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (E)

HIGH), the outputs are disabled (G HIGH), or during a write
operation (E LOWand W LOW).

Standard Products

QCOTS

TM

UT9Q512 512K x 8 SRAM

Data Sheet

February, 2003

Memory Array

1024 Rows

512x8 Columns

Pre-Charge Circuit

Clk. Gen.

Row Select

A0
A1

A2
A3

A4
A5
A6
A7
A8
A9

I/O Circuit

Column Select

Data

Control

CLK
Gen.

A10

A11

A12

A13

A14

A15

A16

A17

A18

DQ 0 - DQ

7

W

G

E

Figure 1. UT9Q512 SRAM Block Diagram

2

PIN NAMES

DEVICE OPERATION

The UT 9Q512 has three control inputs called Enable 1 (E), Write
Enable (W), and Output Enable (G); 19 address inputs, A(18:0);
and eight bidirectional data lines, DQ(7:0). E Device Enable
controls device selection, active, and standby modes. Asserting
E enables the device, causes I

DD

to rise to its active value, and

decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of W greater than V

IH

(min) and E less than V

IL

(max) defines a read cycle. Read access time is measured from
the latter of Device Enable, Output Enable, or valid address to
valid data output.

SRAM Read Cycle 1, the Address Access in figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t

AVQV

is satisfied. Outputs

remain active throughout the entire cycle. As long as Device
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t

AVAV

).

SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 3b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t

ETQV

is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 3c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
t

GLQV

unless t

AVQV

or t

ETQV

have not been satisfied.

A(18:0) Address
DQ(7:0) Data Input/Output
E Enable
W Write Enable
G Output Enable
V

DD

Power

V

SS

Ground

1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19

Figure 2. UT9Q512 25ns SRAM Pinout (36)

(For both shielded and unshielded packages)

NC
A18
A17
A16
A15
G
DQ7
DQ6
V

SS

V

DD

DQ5
DQ4
A14
A13
A12
A11
A10
NC

A0
A1
A2
A3
A4

E
DQ0
DQ1

V

DD

V

SS

DQ2
DQ3

W
A5
A6
A7
A8
A9

G W E I/O Mode Mode

X

1

X 1 3-state Standby

X 0 0 Data in Write

1 1 0 3-state

Read

2

0 1 0 Data out Read

3

WRITE CYCLE

A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance

state when either G is greater than VIH(min), or when W is less
than VIL(max).

Write Cycle 1, the Write Enable - Controlled Access in figure
4a, is defined by a write terminated by W going high, with E
still active. The write pulse width is defined by t

WLWH

when the

write is initiated by W, and by t

ETWH

when the write is initiated

by E. Unless the outputs have been previously placed in the high­impedance state by G, the user must wait t

WLQZ

before applying

data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.

Write Cycle 2, the Chip Enable - Controlled Access in figure
4b, is defined by a write terminated by E going inactive. The
write pulse width is defined by t

WLEF

when the write is initiated

by W, and by t

ETEF

when the write is initiated by the E going
active. For the W initiated write, unless the outputs have been
previously placed in the high-impedance state

by G, the user must wait t

WLQZ

before applying data to the eight

bidirectional pins DQ(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

Table 2. Radiation Hardness

Design Specifications

1

Notes:

1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.

2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of
Aluminum.

Total Dose 50 krad(Si)

Heavy Ion
Error Rate

2

<1E-8 Errors/Bit-Day

4

ABSOLUTE MAXIMUM RATINGS

1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

V

DD

DC supply voltage -0.5 to 7.0V

V

I/O

Voltage on any pin -0.5 to 7.0V

T

STG

Storage temperature -65 to +150°C

P

D

Maximum power dissipation 1.0W

T

J Maximum junction temperature

2

+150°C

Θ

JC

Thermal resistance, junction-to-case

3

10°C/W

I

I

DC input current

±10 mA

SYMBOL PARAMETER LIMITS

V

DD

Positive supply voltage 4.5 to 5.5V

T

C

Case temperature range (C) screening: -55° to +125°C

(E) screening: -40° to +125°C

V

IN

DC input voltage 0V to V

DD

5

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening) (VDD = 5.0V + 10%)

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IH

High-level input voltage 2.0 V

V

IL

Low-level input voltage 0.8 V

V

OL1

Low-level output voltage IOL = 8mA, VDD =4.5V

0.4

V

V

OL2

Low-level output voltage IOL = 200µA,VDD =4.5V 0.05 V

V

OH1

High-level output voltage IOH = -4mA,VDD =4.5V 2.4 V

V

OH2

High-level output voltage IOH = -200µA,VDD =4.5V 3.2 V

C

IN

1

Input capacitance ƒ = 1MHz @ 0V 10 pF

C

IO

1

Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF

I

IN

Input leakage current VIN = VDD and V

SS, VDD

= VDD (max) -2 2 µA

I

OZ

Three-state output leakage current VO = VDD and V

SS

VDD = VDD (max)
G = VDD (max)

-2 2 µA

I

OS

2, 3

Short-circuit output current VDD = VDD (max), VO = V

DD

VDD = VDD (max), VO = 0V

-90 90 mA

IDD(OP) Supply current operating

@ 1MHz

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

125 mA

I

DD1

(OP) Supply current operating

@40MHz

Inputs: VIL = 0.8V,
VIH = 2.0V
I

OUT

= 0mA

VDD = VDD (max)

180 mA

I

DD2

(SB) Supply current standby

@0MHz

Inputs: VIL = VSS
I

OUT

= 0mA

E = V

DD

- 0.5

VDD = VDD (max)
VIH = VDD - 0.5V

6
6

12

mA
mA

mA

-55°C and 25°C

-40°C and 25°C
125°C