UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT
CURRENT MODE PWM CONTROL
CIRCUITS
DESCRIPTION
The UTC UC3842A/3843A provide the necessary functions
to implement off-line or DC to DC fixed frequency current
mode , controlled switching circuits with a minimal external
part count
FEATURES
*Low external part count.
*Low start up current ( Typical 0.12mA )
*Automatic feed forward compensation
*Pulse-by-Pulse current limiting
*Under-voltage lockout with hysteresis
*Double pulse Suppression
*High current totem pole output to drive MOSFET directly
*Internally trimmed band gap reference
*500kHz operation
BLOCK DIAGRAM
SOP-8
DIP-8
Vcc
7
Vref
8
Internal
VFB
COMP
CURRENT SENSE
RT/CT
Bias
2
1
3
4
1/2Vref
ERROR
AMPLIFIER
5V REF S/R
Vref
Good
Logic
1/3Vref
OSCILLATOR
1V
CURRENT
SENSE
COMPARATOR
U.V.L.O
R
PWM
LATCH
S
GND
5
Vcc
7
OUTPUT
6
GND
5
ABSOLUTE MAXIMUM RATINGS(Ta=25°C)
PARAMETER SYMBOL VALUE UNIT
Supply Voltage(Low Impedance Source) VCC 30 V
Supply Voltage(Icc<30mA) Vcc Self Limiting V
Output Current ( Peak ) Io +-1 A
Output Energy(capacity Load) 5
Analog Inputs(pin 2,3) VI(ANA) -0.3 ~ +6.3 V
Error Amplifier Output Sink Current ISINK(EA) 10 mA
at T
Power Dissipation PD DIP-8
SOP-8
amb<=25°C 1.0
at T
amb<=25°C 0.5
Lead Temperature( Soldering 10 Sec ) Tlead 300
UTC UNISONIC TECHNOLOGIES CO., LTD.
µJ
W
W
°C
QW-R103-002,A
1
UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT
A
(continued)
PARAMETRER SYMBOL VALUE UNIT
Storage Temperature Tstg -65 ~ +150
Note 1: Ta>25°C, PD derated with 8mW/°C.
ELECTRICAL CHARACTERISTICS(0°C <=Ta<=70°C,VCC=15V,RT=10kΩ,CT=3.3nF,unless otherwise
specified)
Reference Section
Output Voltage VREF
Line Regulation
Load Regulation
Temperature Stability (Note 2) 0.2 0.4
Total Output Variation Line, Load, Temp(note 2) 4.82 5.18 V
Output Noise Voltage Vosc
Long Term Stability
Output Short Circuit ISC -30 -100 -180 mA
Oscillator Section
Initial Accuracy f
Voltage Stability
Temperature Stability Tmin<=TA<=Tmax(note 2) 5 %
Amplitude Vosc Vpin 4 peak to peak 1.7 V
Error Amplifier Section
Input Voltage VI(EA) Vpin 1=2.5V 2.42 2.50 2.58 V
Input Bias Current IBIAS -0.3 -2
AVOL 2 <=Vo<=4V 60 90 dB
Unity Gain Bandwidth
PSRR I2<=Vcc<=25V 60 70 dB
Output Sink Current Isink Vpin 2=2.7V,Vpin 1=1.1V 2 6 mA
Output Source Current Isource Vpin 2=2.3V,Vpin 1=5V -0.5 -0.8 mA
Vout High VOH
Vout Low VOL Vpin 2=2.7V,Vpin 1=1.1V 0.7 1.1 V
Current Sense section
Gain GV (note 3,4) 2.85 3 3.15 V/V
Maximum Input signal VI(MAX) Vpin 1=5V( note 3) 0.9 1 1.1 V
PSRR 12<=Vcc<=25V 70 dB
Input Bias Current IBIAS -2 -10
Delay to Output Vpin 3=0 to 2V 150 300 ns
Output Section
Output Low Level VOL Isink=20mA 0.1 0.4 V
Isink=200mA 1.5 2.2 V
Output High Level VOH Isource=20mA 13 13.5 V
Isource=200mA 12 13.5 V
Rise Time tR
Fall Time tF
Under-Voltage Lockout Output Section
Start Threshold VTH(ST) UTC3842A 14.5 16 17.5 V
UTC3843A 7.8 8.4 9 V
Min. Operating Voltage VOPR(min)
UTC3843A 7 7.6 8.2 V
PWM Section
Maximum Duty Cycle D(MAX) 95 97 100 %
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Tj=25°C,Io=1mA
REF
∆V
REF
∆V
10Hz<=f<=10kHz,Tj=25°C (note 2)
∆f/∆Vcc
12<=VIN<=25V 6 20 mV
1<=Io=20mA 6 25 mV
Ta=25°C,1000Hrs(note 2)
Tj=25°C
12<=Vcc<=25V 0.2 1 %
Tj=25°C (note 2)
Vpin 2=2.3V, RL=15kΩ to GND
Tj=25°C,C
Tj=25°C,C
L=1nF(note 2)
L=1nF(note 2)
fter Turn On
UTC3842A
4.9 5 5.1 V
50 uV
5 25 mV
47 52 57 kHz
0.7 1 MHz
5 6 V
50 150 ns
50 150 ns
8.5 10 11.5
°C
mV/°C
µA
µA
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R103-002,A
2
UTC UC3842A / 3843A LINEAR INTEGRATED CIRCUIT
Minimum Duty Cycle D(MIN) 0 %
Total Standby Current
Start-up Current IST 0.12 0.3 mA
Operating Supply Current ICC(opr) Vpin 2=Vpin 3=0V 11 17 mA
Vcc Zener Voltage Vz Icc=25mA 34 V
note 2:These parameters, although guaranteed ,are not 100% tested in production.
note 3:Parameters measured at trip point of latch with Vpin 2=0.
note 4:Gain defined as:
note 5:Adjust Vcc above the start threshold before setting at 15V.
OPEN-LOOP LABORATORY TEST FIXTURE
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
∆
Vpin 1
A= ; 0<=Vpin3<=0.8V
∆
Error Amp
Adjust
Vpin 3
Ω
RT
4.7k
Ω
Adjust
Isense
4.7k
5k
Ω
1
Ω
100k
2
3 6
4 5
CT
8
7
Vref
F
A
µ
0.1
F
µ
1k
Ω
0.1
/ 1W
Vcc
OUTPUT
High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used
to sample the oscillator waveform and apply an adjustable Ramp to Pin 3.
UNDER-VOLTAGE LOCKOUT
Icc
Vcc
7
ON/OFF Command
Von=16V
Voff=10V
to rest of IC
<15mA
<1mA
VonVoff
Vcc
During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to
GND with a bleeder resistor to prevent activating the power switch with output leakage currents.
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R103-002,A
3
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