UTC TL074 LINEAR INTEGRATED CIRCUIT
LOW NOISE QUAD J-FET
OPERATIONAL AMPLIFIER
DESCRIPTION
The UTC TL074 is a high speed J-FET input quad
operational amplifier. It incorporates well matched,
high voltage J-FET and bipolar transistors in a
monolithic integrated circuit. The device features high
slew rates, low input bias and offset current, and low
offset voltage temperature coefficient.
FEATURES
*Low power consumption
*Wide common-mode (up to vcc+ ) and differential
voltage range
*Low input bias and offset current
*Low noise en = 15nV / √ Hz(typ)
*Output short-circuit protection
*High input impedance J-FET input stage
*Low harmonic distortion:0.01%(typ)
*Internal frequency compensation
*Latch up free operation
*High slewrate:13V/µs(typ)
SOP-14
DIP-14
PIN CONFIGURATIONS
UTC UNISONIC TECHNOLOGIES CO., LTD. 1
QW-R105-005,A
UTC TL074 LINEAR INTEGRATED CIRCUIT
SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS(Ta=25°C )
Supply Voltage (note 1) Vcc +-18 V
Input Voltage (note 2) Vi +-15 V
Differential Input Voltage (note 3) Vid +-30 V
Power Dissipation Ptot 680 mW
Output Short-Circuit Duration (Note 4) Infinite
Operating Free Air Temperature Toper 0 to 70
Storage Temperature Tstg 5 to 150
NOTES: 1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of
PARAMETER SYMBOL VALUE UNIT
°C
°C
the supply voltages where the zero reference level is the midpoint between Vcc- and Vcc+.
2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts,
whichever is less.
3. Differential voltages are at the non-inverting input terminal with respect to the inverting input terminal.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be
limited to ensure that the dissipation rating is not exceeded.
UTC UNISONIC TECHNOLOGIES CO., LTD. 2
QW-R105-005,A
UTC TL074 LINEAR INTEGRATED CIRCUIT
UTC TL074C ELECTRICAL CHARACTERISTICS( Vcc=+-15V, Ta=25°C, unless otherwise
specified)
PARAMETER SYMBOL MIN TYP MAX UNIT
Input Offset Voltage(Rs=50Ω), Ta=25°C
Tmin<=Ta<=Tmax
Temperature Coefficient of Input Offset
Voltage
Input Offset Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Bias Current*
Ta=25°C
Tmin<=Ta<=Tmax
Input Common Mode Voltage Vicm +-11 -12~+15 V
Output Voltage Swing(RL=10kΩ)
Ta=25°C, RL=2kΩ,
Ta=25°C, RL=10kΩ
Tmin<=Ta<=Tmax, RL=2kΩ
Tmin<=Ta<=Tmax, RL=10kΩ
Large Signal Voltage Gain(RL=2kΩ, Vo=+-
10V) Ta=25°C
Tmin<=Ta<=Tmax
Gain Bandwidth Product(Ta=25°C, RL=10kΩ,
f=100kHz, Vin=10mV, CL=100pF)
Input Resistance Ri
Common Mode Rejection Ratio(RS=50Ω)
Ta=25°C
Tmin<=Ta<=Tmax
Supply Voltage Rejection Ratio(RS=50Ω)
Ta=25°C
Tmin<=Ta<=Tmax
Supply Current( no load)
Ta=25°C
Tmin<=Ta<=Tmax
Channel Separation(Av=100, Ta=25°C)
Output Short-circuit Current
Ta=25°C
Tmin<=Ta<=Tmax
Slew Rate(Vi=10V, RL=2kΩ, CL=100pF,
Ta=25°C, unity gain)
Rise Time(Vi=20mV, RL=2kΩ, CL=100pF,
Ta=25°C, unity gain)
Overshoot Factor(Vi=20mV, RL=2kΩ,
CL=100pF, Ta=25°C, unity gain)
Total Harmonic Distortion(Av=20dB, f=1kHz
RL=2kΩ, CL=100pF, Ta=25Ω, Vo=2Vpp)
Phase Margin 45 Degrees
Equivalent Input Noise Voltage(RS=100Ω,
f=1KHz)
*The Input bias currents are junction leakage currents, which approximately double for every 10°C increase in the
junction temperature.
Vio
Dvio 10
Iio
Iib
Vopp
10
12
10
12
Avd
25
15
GBP 2 3 MHz
CMR
70
70
SVR
70
70
Icc
V01/V02 120 dB
Ios
10
10
SR 8 13
tr 0.1
Kov 10 %
THD 0.01 %
en 15
3 10
13
5 100
10
30 200
20
12
13.5
200 V/mV
1012
86
86
1. 4 2. 5
2.5
40 60
60
mV
¦ÌV/¡æ
pA
nA
pA
nA
dB
dB
mA
mA
V/µs
µs
V
Ω
UTC UNISONIC TECHNOLOGIES CO., LTD. 3
QW-R105-005,A
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