United Electronic Industries DNA-IRIG-650, DNR-IRIG-650 User Manual

DNA/DNR-IRIG-650

—

User Manual

IRIG-A, B, E and G Timing Generation

and Synchronization board for the

PowerDNA Cube and PowerDNR RACKtangle

Release 4.6

© Copyright 1998-2019 United Electronic Industries, Inc. All rights reserved.

March 2019

PN Man-DNx-IRIG-650-319

Information furnished in this manual is believed to be accurate and reliable. However, no responsibility
is assumed for its use, or for any infringement of patents or other rights of third parties that may result
from its use.

All product names listed are trademarks or trade names of their respective companies.

See the UEI website for complete terms and conditions of sale:

http://www.ueidaq.com/cms/terms-and-conditions/



Contacting United Electronic Industries

Mailing Address:

27 Renmar Avenue
Walpole, MA 02081
U.S.A.

For a list of our distributors and partners in the US and around the world, please contact a member of our
support team:

Support:

Telephone: [phone]
Fax: [phone]

Also see the FAQs and online “Live Help” feature on our web site.

Internet Support:

Support:

Website: www.ueidaq.com
FTP Site: ftp://ftp.ueidaq.com

[e-mail]

Product Disclaimer:

WARNING!

DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES, INC. AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

Products sold by United Electronic Industries, Inc. are not authorized for use as critical components in
life support devices or systems. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness. Any attempt to purchase any United Electronic
Industries, Inc. product for that purpose is null and void and United Electronic Industries Inc. accepts
no liability whatsoever in contract, tort, or otherwise whether or not resulting from our or our
employees' negligence or failure to detect an improper purchase.

Specifications in this document are subject to change without notice. Check with UEI for
current status.

DNA/DNR-IRIG-650 IRIG Timing Layer

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Contents i

Table of Contents

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Organization of Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Layer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Technical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.7 Layer Connectors and Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 2 Programming with the High Level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Creating a Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Configuring the Resource String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Configuring Time Keeper Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.2 IRIG Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.3 IRIG Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.4 GPS Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.5 Driving the TTL outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Configuring the timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4 Reading data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5 Cleaning-up the Session. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 3 Programming with the Low Level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Low-level Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Low-level Programming Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 Time Keeper Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.3 Output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.4 Assigning TTL outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.5 Enabling and disabling subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.6 Event programming (sync & async) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.7 GPS programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.8 Calibrating the precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.9 Custom PLL frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DNA/DNR-IRIG-650 IRIG Timing Layer

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Figures ii

List of Figures

Chapter 1 – Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1-1 Simplified Block Diagram of the IRIG-650 .................................................................... 5

1-2 Functional Diagram of DNx-IRIG-650 board................................................................. 6

1-3 Pinout for the DNx-IRIG-650 series layer ..................................................................... 9

A-1 Pinout, photo, and schema of DNA-CBL-650 accessory ............................................ 50

A-2 Photo of DNA-ACC-650 break-out board and BNC-650............................................. 51

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Chapter 1 Introduction

This document outlines the feature set and use of the DNR- and DNA-IRIG-650
layer. The IRIG-650 Timing Generation and Synchronization board is a module
for the UEI PowerDNA I/O Cube (DNA-IRIG-650) and the DNR-1G HalfRACK
and RACKtangle chassis (DNR-IRIG-650). The DNR version is electronically
identical to the DNA version except that the DNR version is designed to plug into
a RACKtangle backplane instead of a Cube chassis.

This module may be used to capture Inter-range Instrumentation Group (IRIG)
data when the Cube or RACKtangle is slaved to an external master timing
device. It also provides IRIG outputs that allow the Cube or RACKtangle to serve
as master time keeper for the system.

The DNx-IRIG-650 provides inputs for standard analog, modulated IRIG signals
as well as non-modulated DC (DCLS or NRZ) and Manchester II inputs. In
addition to the IRIG inputs, the board also allows the user to provide an external
10 MHz master clock and/or a 1 PPS synchronization pulse. A generic digital
input may also be used to directly capture event timing.

The DNx-IRIG-650 can also be configured as an IRIG source which will provide
timing and synchronization for other devices in the system. The board provides
both modulated analog and digital IRIG outputs as well as 10 MHz and 1 PPS
synchronization and timing (DCLS/Manchester II) signals.

The boards also include a built-in GPS interface. UEI recommends the use of
high gain, active GPS antennas, such as the Symmetricom AT575-142 or
equivalent.

DNA/DNR-IRIG-650 IRIG Timing Layer

Chapter 1 1

Introduction

1.1 Organization
of Manual

This DNx IRIG-650 User Manual is organized as follows:

• Chapter 1 Introduction

This chapter provides an overview of DNx-IRIG-650 Timing Board features,
device architecture, connectivity, and logic. This chapter also describes var
ious inputs and outputs.

• Chapter 2 Programming with the High-Level API

This chapter provides an overview of the how to use Framework to create a
session, configure the session for the various types of inputs and outputs,
and how to interpret results.

• Chapter 3 Programming with the Low-Level API

This chapter refers the reader to a Reference API that defines low-level func­tions and commands for configuring and using the IRIG-650 series layer.

• Appendix A Accessories

This appendix provides a list of accessories available for the board.

•Index

This is an alphabetical listing of the topics covered in this manual.

-

DNA/DNR-IRIG-650 IRIG Timing Layer

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Chapter 1 2

Introduction

Manual Conventions

To help you get the most out of this manual and our products, please note that
we use the following conventions:



Tips are designed to highlight quick ways to get the job done or to reveal
good ideas you might not discover on your own.

NOTE: Notes alert you to important information.

CAUTION! Caution advises you of precautions to take to avoid injury, data loss,
and damage to your boards or a system crash.

Text formatted in bold typeface generally represents text that should be entered

verbatim. For instance, it can represent a command, as in the following
example: “You can instruct users how to run setup using a command such as

setup.exe.”

Text formatted in fixed typeface generally represents source code or other text
that should be entered verbatim into the source code, initialization, or other file.

Examples of Manual Conventions



Before plugging any I/O connector into the Cube or RACKtangle, be
sure to remove power from all field wiring. Failure to do so may
cause severe damage to the equipment.

Usage of Terms

Throughout this manual, the term “Cube” refers to either a PowerDNA Cube
product or to a PowerDNR RACKtangle
applicable. The term DNR is a specific reference to the RACKtangle, DNA to the

PowerDNA I/O Cube, and DNx to refer to both.

rack mounted system, whichever is

DNA/DNR-IRIG-650 IRIG Timing Layer

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Chapter 1 3

Introduction

1.2 Layer
Features

The DNx-IRIG-650 layer has the following features:

• IRIG-A, B, E and G output allows IRIG-650 to provide timing signals

• IRIG-A, B, E and G input allows IRIG-650 to synchronize with external

IRIG-A, B, E and G sources

• Modulated or DC level inputs and outputs

• 1 PPS output

• Event input captures timing to UTC (Coordinated Universal Time)

• Direct GPS input (active antenna)

• 10 MHz, 1 ppm time base or slaved to external 10 MHz

Protocols Supported:
IRIG-A: A00x, ABx

IRIG-B: B00x, B12x,B IEEE 1344, B TrueTime
IRIG-E: E00x, E11x, E12x
IRIG-G: G00x, G14x

Time Source:

The IRIG-650’s time keeper can be synchronized with the following sources:

• IRIG AM-modulated input timecode

• IRIG DCLS (i.e. NRZ-L code) or Manchester II code

• GPS signal (sync’d with GPS 1 PPS clock, time derived from GPRMC string)

• Precise external 1PPS (local time should be set by the user)

Inputs:

• AM (timecode), AMIn, DCLS, MII (Manchester II)

• GPS RFIn

• 1 PPS (TTL0, TTL1 Line)

• External 10 MHz (TTL0)

• External events (TTL-1u or SYNCx lines)

Outputs:

• Time Code: AM (AMOut), DCLS (TTL-OutX), Manchester II

• 10 PPS, 100 PPS (TTL-OutX, SYNCx)

• 1MHz, 5 MHz, 10 MHz (TTL-OutX, SYNCx)

• Custom PLL frequency (1Hz -1 MHz, 4 digits accurate)

• 1 PPS, 1 PPM, 1PPM (TTL-OutX, SYNCx)

DNA/DNR-IRIG-650 IRIG Timing Layer

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Inputs

IRIG Analog inputs A, B, E and G types supported

Modulation ratio 3:1 to 6:1

Input amplitude 500 mV to 5 V P-P (AC coupled)

Input impedance > 10 k Ω

IRIG-B DC inputs 3.3/5 V logic compliant

10 MHz input 3.3/5 V logic compliant

40% to 60% duty cycle

1 PPS input 3.3 and 5 V logic compliant

GPS

Antenna configuration

0OMZBctiveBOUFOOBTBSFTVQQPSUFE

Position (Velocity) accuracy 1.8 m (0.1 m/S) rms

UTC time accuracy ± 50 nS rms

Outputs

IRIG Output types A, B, E and G types supported

Analog output 3:1 ratio,

4 V P-P output (50 ohm)

Digital output high voltage 1.1 V - 50 Ω (min)

2.4V - 1 Meg Ω (min)

Digital output low voltage 0.3 V - 50 Ω (max)

0.7V - 1 Meg Ω (max)

Sync and Clock outputs TTL/CMOS compatible

Output timing signal selection Std 1 & 10 PPS/PPM plus custom

Output clock selection 1, 5 and 10 MHz plus custom freqs.

On-Board Clock

Frequency 10 MHz

Initial accuracy 50 PPB

Temperature stability 50 PPB over full temp range

Time stability 300 PPB per year

Output Voltage TTL/CMOS compatible

General

Power consumption 2W

Operating range Tested -40 to +85 °C

Isolation 350 Vrms between all IRIG signals and

the chassis. (GPS is not isolated)

Humidity range 0-95%, non-condensing

Vibration IEC 60068-2-6

IEC 60068-2-64

5 g, 10-500 Hz, sinusoidal
5 g (rms), 10-500Hz, broad-band random

Shock IEC 60068-2-27

50 g, 3 ms half sine, 18 shocks @ 6
orientations
30 g, 11 ms half sine, 18 shocks @ 6
orientations

Altitude to 70,000 feet

Chapter 1 4

Introduction

1.3 Technical

The technical specifications of the DNA/DNR-IRIG-650 IRIG Timing Layer.

Specification

Table 1-1. Technical Specifications

DNA/DNR-IRIG-650 IRIG Timing Layer

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DB-62 (female)
62-pin I/O connector

RDY LED
STS LED

DNA bus
connector

DB-62 (female)
62-pin I/O connector

RDY LED
STS LED

DNR bus
connector

32-bit 66-MHz Internal bus

On-Board

FPGA

20 MHz High

Precision VETCXO

Digital Calibration

D/A

Programmable

PLL

Input

Buffers

Output
Drivers

AM Input

Circuitry

DC/AC

AM Output

Circuitry

GPS

Interface

AM Output

Isolation

Logic Level Outputs

Logic Level Inputs

RF Inputs

"DUJWF Antenna

50 ppb initial accuracy

1.4 Indicators Indicators of the layers are labelled in the pictures below:

Chapter 1 5

Introduction

1.5 Simplified
Block
Diagram

The figure below shows a simplified block diagram of the layer’s architecture:

Figure 1-1. Simplified Block Diagram of the IRIG-650

DNA/DNR-IRIG-650 IRIG Timing Layer

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PLL
100 MHz

PLL

DNA Bus SYNC lines

16-bit ADC

AM2NRZ

NRZ2TIME

MII2NRZ

Time Decoder

UART

GPS Receiver

CLI Logic

RFIn0

RFIn1

In0

In1

In2
In3
In4

GPSIn

Out0

Out1
Out2

Out3

Output MUX

Time Assembler

Carrier Generator

14-bit DAC

AMOut

1 PPS: source

Event detector/recorder

Input CL FIFO

Aux D/A --

clock fine tuning

precise
clock
source
20 MHz

Event Generator

Time Keeper

AMIn

InputsOutputs

66 MHz

timestamp&event

±50ppb

detector

decoder

with FIFO
and pattern
detection

maintains the present
time even in absence
of sync pulses

initial
accuracy

Chapter 1 6

Introduction

1.6 Functional
Description

The following is a functional block diagram of The DNx-IRIG-650 IRIG Timing
Generation and Synchronization Board.

Figure 1-2. Functional Diagram of DNx-IRIG-650 board

DNA/DNR-IRIG-650 IRIG Timing Layer

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Chapter 1 7

Introduction

The IRIG input time code can be received from one of the following sources:

• AM-modulated signal acquired by the 16-bit ADC and processed by the

AM2NRZ module. This module automatically detects the zero crossing,
adjusts the zero level, extracts the high- (mark) and low- (space) ampli
tude ratio and generates the resulting NRZ-L (i.e. DCLS) code.

• Manchester II encoded signal processed by the MII2NRZ module. You

must select the correct carrier for the NRZ data extraction to work.

• Direct NRZ input; where the input signal is direct-current level shifted

(DCLS) signal which is pulse-width coded but is not AM-modulated.

• A forced initial time setup from the DNA host, immediate, and on 1PPS

edges

NOTE: The encoding “non-return to zero, level (NRZ-L)” is synonymous with

“direct-current level shift (DCLS)” encoded signals

A 1PPx (e.g. 1PPS) input “on-time pulse” can be sourced from NRZ time code.

If an NRZ-encoded time code is not available, an external 1PPS signal can be
delivered from a PowerDNx SYNC line, an external input, or the GPS input.

-

NRZ information is down-converted by the NRZ2TIME module to create time
characters: “Px” (position identifier), “0” (logic 0), “1” (logic 1), plus idle charac­ters. In most time codes, the IDLE character is not used, and if present, it usually
indicates a lost carrier signal.

After the input data stream is parsed into time characters, the characters are
processed by the Time Decoder module to: extract an “on-time” pulse, copy
incoming data into double-buffered time messages, validate these messages
using a validation table. Each validated message is further processed to extract
time information, which is then copied into timing registers.

The current time is maintained in the Time Keeper module, which receives time
from the Time Decoder and keeps track of the time and/or date increments. If the
current time does not match the time received from the decoder, an interrupt is
generated. When this occurs, the time received from the decoder is then
accepted as the valid current time.

In hardware the Time Keeper module always maintains a time that is 1 second
ahead of the time just received - but the software does correct the returned time.
The reason for this is that the time code received from the Time Assembler mod­ule is known to be about 1 time frame behind its own “on-time” pulse.

If an external time source is not available, the Time Keeper module maintains
time based on internal or external 1 PPS pulses and the initial time set by the
host, or based on the last valid time recovered from the time source. The 1PPS
time interval that is used for the flywheel counter should pass strict validation
prior to use, and in case of lost or invalid input data, requires at least two periods
of valid 1 PPS signal prior to use. By default, 1 PPS valid interval is set to ±50µs. 
The flywheel takes in the 100MHz clock and synchronizes to it on 1PPS pulse.
The 100MHz base clock of the IRIG-650 is generated by a PLL on the FPGA
that multiplies the output of a very high precision 20MHz voltage controlled,
temperature compensated oscillator with ±50ppb frequency stability and
maximum drift of ±500ppb, the majority of which will happen within the first year
of operation and can be compensated by the in-factory calibration which uses a
Rubidium Standard source.

DNA/DNR-IRIG-650 IRIG Timing Layer

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Chapter 1 8

Introduction

The phase noise specification of the 20MHz oscillator is:

PHASE NOISE:10Hz OFFSET: -105dBc/Hz

100Hz OFFSET: -125dBc/Hz

1kHz OFFSET: -135dBc/Hz

10kHz OFFSET: -145dBc/Hz

The Time Keeper module can use either raw binary seconds or binary-coded
decimal (BCD) seconds/minutes/hours from the input code to read the current
time.

The Time Assembler module accepts the current time from the Time Keeper and
uses it to create an output time code with Manchester II, AM, and DCLS coding.
(Note that the output format does not have to be the same format as an input.)

In addition to the time keeping & generating functionality described above, the
IRIG-650 also provides event recording and event generating functions.

Event recording allows you to timestamp and store locations of up to four

events from the following event sources:

• SYNC bus lines of the Cube or RACKtangle

• External inputs

• Errors (lost synchronization inputs, invalid 1 PPS, etc.)

• Start/stop trigger broadcast commands

The above recorded events may be streamed into the output FIFO, which allows
you to synchronize data acquired by any other DNR/DNA boards with time that
is accurately kept by the IRIG-650 layer. The above recorded events can also be
routed to TTL or SYNCx lines.

Event generation allows creation of one-time or repeatable events based on

the precise time that is maintained by the IRIG-650 layer. The maximum recom­mended rate of events is 100 kHz and the maximum resolution is 10 nsec.

Event generation includes a digital PLL mode that generates a configurable
number of pulses per period (2MHz max), designed to adjust its period to a
1PPS source from the TimeKeeper or from a TTL input.

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62

43

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

2

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

x
x
x
x
x
x
x
x
x

ISGND

AM-IN

ISGND
ISGND

TTL-OUT3

ISGND
ISGND

TTL-OUT2

ISGND

TTL-OUT0

(RF0) EXTCLK-IN

ISGND

(RF1) EXTTRIG-IN

ISGND
ISGND

TTL-IN2

ISGND

TTL-IN1
TTL-IN0

ISGND

x

GND
GND
GND

GPS-IN

GND
GND
GND

x

x

x

x

x

x

x

x

x

ISGND

ISGND

AM-OUT

TTL-OUT1

ISGND

ISGND

TTL-IN4

TTL-IN3

ISGND

ISGND

x

GND

GND

GND

GND

x

DCLS_IN0/
DCLS_IN1/

Chapter 1 9

Introduction

1.7 Layer
Connectors
and Wiring

The figure below illustrates the pinout of the IRIG-650.

Figure 1-3. Pinout for the DNx-IRIG-650 series layer



Capable of attaching to the 62-pin connector are the plug-in break-out board or
the DNA-CBL-650 cable, which is listed in the appendix. The following signals
are brought out to the female BNC connectors on the DNA-CBL-650:

• AM-IN: IRIG AM Input (pin 37)

• AM-OUT: IRIG AM Output (pin 14)

• DCLS-IN: ExtClk-Input (pin 53)

• GPS-IN: GPS antenna input (pin 46)

The remaining signals are brought out to a 37-pin, Female connector at the end
of the DNA-CBL-650 as shown in the appendix. This cable may be plugged into
a DNA-STP-37 screw terminal panel or other panel. Please note that 12 of these
signals are twisted pairs with their respective grounds as shown in the appendix.

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Date: March 2019 DNx-IRIG-650 Chap2x.fm

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Programming with the High Level API

Chapter 2 10

Chapter 2 Programming with the High Level API

This section describes how to control the DNx-IRIG-650 using the UeiDaq
Framework High Level API.

UeiDaq Framework is object oriented and its objects can be manipulated in the
same manner from different development environments such as Visual C++,
Visual Basic or LabVIEW.

The following section focuses on the C++ API, but the concept is the same no
matter what programming language you use.

Please refer to the “UeiDaq Framework User Manual” for more information on
use of other programming languages.

2.1 Creating a
Session

// create a session object

CUeiSession irigSession;

2.2 Configuring
the Resource
String

2.2.1 Configuring

Time Keeper
Input

The Session object controls all operations on your PowerDNA device. There­fore, the first task is to create a session object:

UeiDaq Framework uses resource strings to select which device, subsystem
and channels to use within a session. The resource string syntax is similar to a
web URL:

<device class>://<IP address>/<Device Id>/<Subsystem><Channel list>



For PowerDNA and RACKtangle, the device class is pdna.
The IRIG-650 is programmed using the subsystem irig (letter-case insensitive).

For example, the following resource string selects IRIG input line 0 on device 1
at IP address 192.168.100.2: “pdna://192.168.100.2/Dev1/Irig0”

Use the Session object’s method “CreateIRIGTimeKeeperChannel” to
configure the time keeper channel and parameters associated with the channel.

The following sample code shows how to configure the time keeper channel of
a IRIG-650 set as device 1:

// Configure the time keeper

CUeiIRIGTimeKeeperChannel* pTKChannel =
irigSession.CreateIRIGTimeKeeperChannel(
"pdna://192.168.100.2/Dev1/Irig0",
UeiIRIG1PPSInternal,
autoFollow);

DNA/DNR-IRIG-650 IRIG Timing Layer

Tel: [phone] www.ueidaq.com Vers: 4.6
Date: March 2019 DNx-IRIG-650 Chap2x.fm

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Programming with the High Level API

It configures the following parameters:

• 1PPS source:The 1PPS signal source, that can be any of the following

values:

1PPS Source Value Description

Chapter 2 11

UeiIRIG1PPSInternal

UeiIRIG1PPSInputTimeCode

UeiIRIG1PPSGPS

UeiIRIG1PPSRFIn

UeiIRIG1PPSExternalTTL0

UeiIRIG1PPSExternalTTL1

UeiIRIG1PPSExternalTTL2

UeiIRIG1PPSExternalTTL3

UeiIRIG1PPSExternalSync0

UeiIRIG1PPSExternalSync1

1PPS signal is generated internally with
precision oscillator

1PPS signal is derived from input timecode

1PPS signal is derived from GPS

1PPS signal is derived from signal 
connected on RF input

External 1PPS signal is connected to TTL0
input pin

External 1PPS signal is connected to TTL1
input pin

External 1PPS signal is connected to TTL2
input pin

External 1PPS signal is connected to TTL3
input pin

External 1PPS signal is connected to
SYNC0 bus line

External 1PPS signal is connected to
SYNC1 bus line

UeiIRIG1PPSExternalSync2

UeiIRIG1PPSExternalSync3

• Auto-follow: If selected, external 1PPS source does not deliver pulses

(because of a break in timecode transmission, for example). The Time
keeper can switch to internal timebase when externally derived one is
not available.

In addition you can set additional parameters using the channel object methods
(under LabVIEW use property node):

• Nominal Value enabled: Select whether to use nominal period (i.e.

100E6 pulses of 100MHz base clock) or the period measured by time
keeper (it measures and averages number of base clock cycles
between externally derived 1PPS pulses when they are valid).

// enable nominal value

pTKChannel->EnableNominalValue(true);

External 1PPS signal is connected to
SYNC2 bus line

External 1PPS signal is connected to
SYNC3 bus line

-

-

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• Sub PPS enabled: Select whether external timebase is slower than

1PPS or is not derived from the timecode.

// Disable sub PPS

pTKChannel->EnableSubPPS(false);

• Initial time: The initial time loaded in time keeper.

// Initial Time

tUeiANSITime now;…
pTKChannel->SetInitialTime(now)

DNA/DNR-IRIG-650 IRIG Timing Layer

Chapter 2 12

Programming with the High Level API

2.2.2 IRIG Output Use the method CreateIRIGOutputChannel() to configure the time code

output on your IRIG-650.

// configure the time code output

CUeiIRIGOutputChannel* pOutChannel =
irigSession.CreateIRIGOutputChannel(
"pdna://192.168.100.2/Dev1/Irig0",
timeCodeformat);

It configures the following parameters:

• Timecode Format: the format used to generate the time code.

– UeiIRIGTimeCodeFormatA: IRIG-A
– UeiIRIGTimeCodeFormatB: IRIG-B
– UeiIRIGTimeCodeFormatE_100Hz: IRIG-E 100Hz
– UeiIRIGTimeCodeFormatE_1000Hz: IRIG-E 1000Hz
– UeiIRIGTimeCodeFormatG: IRIG-G

In addition you can set the following parameter using the channel object
methods (under LabVIEW use property node):

• Start when input is valid: If selected, the output time coder waits for

the input time decoder to receive a valid time code before starting.

// start when input is valid

pOutChan->EnableStartWhenInputValid(true);

DNA/DNR-IRIG-650 IRIG Timing Layer

Tel: [phone] www.ueidaq.com Vers: 4.6
Date: March 2019 DNx-IRIG-650 Chap2x.fm

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Chapter 2 13

Programming with the High Level API

2.2.3 IRIG Input Use the method CreateIRIGInputChannel() to configure the time code

input on your IRIG-650.

// configure the time code input

CUeiIRIGInputChannel* pInChannel =
irigSession.CreateIRIGOutputChannel(
"pdna://192.168.100.2/Dev1/Irig0",
decoderInput,
timeCodeformat);

It configures the following parameters:

• Decoder Input Type: The source of the incoming timecode

– UeiIRIGDecoderInputAM: Time code is provided as an AM

signal

– UeiIRIGDecoderInputManchesterRF0:

Time code is provided as a Manchester II code on RF input 0

– UeiIRIGDecoderInputManchesterRF1:

Time code is provided as a Manchester II code on RF input 1

– UeiIRIGDecoderInputManchesterIO0:

Time code is provided as a Manchester II code on I/O input 0

– UeiIRIGDecoderInputManchesterIO1:

Time code is provided as a Manchester II code on I/O input 1

– UeiIRIGDecoderInputNRZRF0:

Time code is provided as a NRZ code on RF input 0

– UeiIRIGDecoderInputNRZRF1:

Time code is provided as a NRZ code on RF input 1

– UeiIRIGDecoderInputNRZIO0:

Time code is provided as a NRZ code on I/O input 0

– UeiIRIGDecoderInputNRZIO1:

Time code is provided as a NRZ code on I/O input 1

– UeiIRIGDecoderInputGPS :

Time code is taken from GPS NMEA message

• Timecode Format: the format used to generate the time code.

In addition you can set the following parameters using the channel object
methods (under LabVIEW use property node):

• Idle character: Determines whether idle character in the timing byte

stream are accepted.

// disable idle character

pInChan->EnableIdleCharacter(false);

// Enable single P0 marker

pInChan->EnableSingleP0Marker(true);

• Single P0 Marker: Determines whether to use only one marker P0 in

the timing byte stream.