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US1050
5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURESFEATURES
Guaranteed < 1.3V Dropout at Full Load
Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-in Thermal Shutdown
APPLICATIONSAPPLICATIONS
Low Voltage Processor Applications such as :
P54C,P55C,Cyrix M2,
POWER PC,AMD
GTL+ Termination
PENTIUM PRO, KLAMATH
Low Voltage Memory Termination Applications
Standard 3.3V Chip-Set and Logic Applications
TYPICAL APPLICATIONTYPICAL APPLICATION
DESCRIPTIONDESCRIPTION
The US1050 product is a low dropout three terminal adjustable regulator with minimum of 5A output current
capability. This product is specifically designed to provide well regulated supply for low voltage IC applications
such as Pentium P54C,P55C as well as GTL+
termination for Pentium Pro and Klamath pro-
cessor applications . The US1050 is also well suited for
other processors such as Cyrix,AMD and Power
PCapplications. The US 1050 is guaranteed to have
<1.3V drop out at full load current making it ideal to
provide well regulated outputs of 2.5V to 3.6V with 4.75V
to 7V input supply.
C1
1500uF
Vin
3
Vout
Adj
2
1
R1
121
R2
205
US1050
1050app1-1.1
Typical Application of US1050 in a 5V to 3.38V regulator designed
to meet the Intel P54C Processors.
Notes: Pentium P54C,P55C ,Klamath,Pentium Pro,VRE,are trade marks of Intel Corp.Cyrix M2 is trade mark of Cyrix Corp.
Power PC is trade mark of IBM Corp.
3.38V / 5A
C2
2x 1500uF
PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION
Tj (°C) 3 PIN PLASTIC 3 PIN PLASTIC 2 PIN PLASTIC 3 PIN PLASTIC
TO220 (T) TO263 (M) POWER FLEX (P) TO252 (D)
0 TO 150 US1050CT US1050CM US1050CP US1050CD
Rev. 1.3
10/27/00
2-33
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US1050
ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................................. 7V
Power Dissipation ............................................ Internally Limited
Storage Temperature Range .............................. -65°C TO 150°C
Operating Junction Temperature Range .................. 0°C TO 150°C
PACKAGE INFORMATIONPACKAGE INFORMATION
3 PIN PLASTIC TO220 ( T ) 3 PIN PLASTIC TO263 ( M ) 2 PIN PLASTIC POWER FLEX ( P ) 3 PIN PLASTIC TO252 ( D )
Tab is
Vout
FRONT VIEW
4
Tab is
Vout
FRONT VIEW
4
3
Vin
1
Adj
3
Vin
1
Adj
Tab is
Vout
FRONT VIEW
3
2
1
Vin
Vout
Adj
Tab is
Vout
FRONT VIEW
3
Vin
2
Vout
1
Adj
θJT=2.7°C/W θJA=60°C/W θJA=35°C/W for 1" Square pad θJA=70°C/W for 1" Square pad θJA=70°C/W for 0.5" Sq pad
ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,Cin=1uF,Cout=10uF,and Tj=0 to 150°C.Typical
values refer to Tj=25°C.
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage VREF Io=10mA,Tj=25°C,(Vin-Vo)=1.5V 1.243 1.250 1.257 V
Io=10mA, (Vin-Vo)=1.5V 1.237 1.250 1.263
Line Regulation Io=10mA,1.3V<(Vin-Vo)<7V 0.2 %
Load Regulation (note 1) Vin=3.3V,Vadj=0,10mA<Io<5A 0.4 %
Dropout Voltage
(note 2) ∆VO Note 2 , Io=5A 1.1 1.3 V
Current Limit Vin=3.3V,dVo=100mV 5.1 A
Minimum Load Current Vin=3.3V,Vadj=0V 5 10 mA
(note 3)
Thermal Regulation 30 mS PULSE,Vin-Vo=3V,Io=5A 0.01 0.02 %/W
Ripple Rejection f=120HZ ,Co=25uF Tan
Io=2.5A,Vin-Vo=3V 60 70 dB
Adjust Pin Current IADJ Io=10mA,Vin-Vo=1.5V,Tj=25
Io=10mA,Vin-Vo=1.5V 55 120 uA
Adjust Pin Current Change Io=10mA,Vin-Vo=1.5V,Tj=25 0.2 5 uA
Temperature Stability Vin=3.3V,Vadj=0V,Io=10mA 0.5 %
Long Term Stability Tj=125°C,1000 Hrs 0.3 1 %
RMS Output Noise Tj=25°C 10hz<f<10khz 0.003 %Vo
Note 1 : Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data.
Note 2 : Drop-out voltage is defined as the minimum
differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output
Note 3 : Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically maintains this current.
voltage drops 1% below its nominal value.
2-34
Rev. 1.3
10/27/00
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US1050
PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 Adj A resistor divider from this pin to the Vout pin and ground sets the output voltage.
2 Vout The output of the regulator. A minimum of 10uF capacitor must be connected
from this pin to ground to insure stability.
3 Vin The input pin of the regulator. Typically a large storage capacitor is connected
from this pin to ground to insure that the input voltage does not sag below the
minimum drop out voltage during the load transient response. This pin must
always be 1.3V higher than Vout in order for the device to regulate properly.
BLOCK DIAGRAMBLOCK DIAGRAM
Vin 3
+
CURRENT
LIMIT
THERMAL
SHUTDOWN
Figure 1 - Simplified block diagram of the US1050
APPLICATION INFORMATIONAPPLICATION INFORMATION
Introduction
The US1050 adjustable Low Dropout (LDO) regulator is
a 3 terminal device which can easily be programmed
with the addition of two external resistors to any voltages within the range of 1.25 to 5.5 V.This regulator
unlike the first generation of the 3T regulators such as
LM117 that required 3V differential between the input
and the regulated output,only needs 1.3V differential to
maintain output regulation. This is a key requirement for
today’s microprocessors that need typically 3.3V supply and are often generated from the 5V supply. Another
major requirement of these microprocessors such as
the Intel P54C is the need to switch the load current
from zero to several amps in tens of nanoseconds at
2 Vout
1.25V
1050blk1-1.0
the processor pins ,which translates to an approximately
300 to 500 nS current step at the regulator . In addition,
the output voltage tolerances are also extremely tight
and they include the transient response as part of the
specification.For example Intel VRE specification calls
for a total of ±100mV including initial tolerance,load regu-
lation and 0 to 4.6A load step.
The US1050 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage , reducing the overall system cost with the
need for fewer output capacitors.
+
1 Adj
Rev. 1.3
10/27/00
2-35