UBS Axcera LU1000AT User Manual

UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

Chapter 4

Circuit Descriptions

4.1 (A2) Modulator Module
(1301929; Appendix B)

NOTE: Not used in a translator system.

4.1.1 Analog Modulator Board
(1301797; Appendix B)

The board takes the audio and video
inputs and produces a modulated visual
IF + aural IF output.

Main Audio and Aural IF portion of
the board

The analog modulator board takes each
of the three possible audio inputs and
provides a single audio output.

4.1.1.1 MONO, Balanced Audio Input

The first of the three possible baseband
inputs to the board is a 600-Ω, balanced­audio input (0 to +10 dBm) that enters
through jack J41A, pins 10A (+), 12A
(GND), and 11A (-), and is buffered by
U11A and U11B. Diodes CR9, CR10,
CR12 and CR13 protect the input to U11A
and U11B if an excessive signal level is
present on the input. The outputs of
U11A and U1B are applied to differential
amplifier U11C. U11C eliminates any
common mode signals (hum) on its input
leads. A pre-emphasis of 75 ms is
provided by R97, C44, and R98 and can
be eliminated by removing jumper W6 on
J22. The signal is then applied to
amplifier U11D whose gain is controlled
by jumper W7 on J23. Jumper W7 on
jack J23 is positioned according to the
input level of the audio signal (0 or +10
dBm). If the input level is approximately
0 dBm, the mini-jumper should be in the
high gain position between pins 1 and 2
of jack J23. If the input level is
approximately +10 dBm, the mini­jumper should be in low gain position
between pins 2 and 3 of jack J23. The
balanced audio is then connected to
buffer amplifier U12A whose input level is

determined by the setting of the MONO,
balanced audio gain pot R110, accessed
through the front panel. The output of the
amplifier stage is wired to the summing
point at U13C, pin 9.

4.1.1.2 STEREO, Composite Audio Input

The second possible audio input to the
board is the composite audio (stereo) input
that connects to the board at J41A Pin 14A
(+) and J41A Pin 13A (-).

NOTE: For the transmitter to operate using
the composite audio input the Jumper W1
on J4 must be between Pins 2 and 3, the
Jumper W2 on J6 must be between Pins 2
and 3 and the Jumper W4 on J5 must be
between Pins 1 and 2. These jumpers
connect the composite audio to the rest of
the board.

Jumper W14 on jack J26 provides a 75Ω-
input impedance when the jumper is
between pins 1 and 2 and a high
impedance when it is between pins 2 and

3. Diodes CR17, CR18, CR20 and CR21
protect the input stages of U14A and U14B
if an excessive signal level is applied to the
board. The outputs of U14A and U14B are
applied to differential amplifier U13A,
which eliminates common mode signals
(hum) on its input leads. The composite
input signal is then applied to amplifier
U13B; whose gain is controlled by the
STEREO, composite audio gain pot R132,
accessed through the front panel. The
composite audio signal is then connected
to the summing point at U13C, pin 9.

4.1.1.3 SAP/PRO, Subcarrier Audio Input

The third possible input to the board is the
SAP/PRO, SCA audio input at J41A pin
16A(+) and 17A(-). The SCA input has an
input matching impedance of 75Ω that can
be eliminated by removing jumper W15
from pins 1 and 2 of J28. The SCA input is
bandpass filtered by C73, C74, R145, C78,
C79, and R146 and is fed to buffer

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

amplifier U13D. The amplified signal is
then applied though the SAP/PRO, SCA
gain pot R150, accessed through the
front panel, to the summing point at pin
9 of U13C.

4.1.1.4 Audio Modulation of the

4.5 MHz VCO

The Mono balanced audio, or the Stereo
composite audio, or the SAP/PRO SCA
buffered audio signal, is fed to the
common junction of resistors R111,
R130, and R152 that connect to pin 9 of
amplifier U13C. The output audio signal
at pin 8 of U13C is typically .8 Vpk-pk at
a ±25-kHz deviation for Mono balanced
audio or .8 Vpk-pk at ±75-kHz deviation
for Stereo composite audio as measured
at Test Point TP1. This audio deviation
signal is applied to the circuits containing
the 4.5 MHz aural VCO U16. A sample of
the aural deviation level is amplified,
detected by U15A and U15B, and
connected to J41A pin 5A on the board.
This audio-deviation level is connected to
the front panel display on the
Control/Power Supply Assembly.

The audio from U13C is connected thru
C71, a frequency response adjustment,
to varactor diodes, CR24 to CR27, that
frequency modulates the audio signal
onto the generated 4.5-MHz signal by
U16. U16 is the 4.5-MHz VCO that
generates the 4.5-MHz continuous wave
(CW) signal. The output frequency of the

4.5 MHz signal is maintained and
controlled by the correction voltage
output of the U21 PLL integrated circuit
(IC), at “N”, that connects to the varactor
diodes. The audio-modulated, 4.5-MHz
signal is fed through the emitter follower
Q13 to the amplifiers U17A and U17B.
The amplified output of U17A is
connected to a 4.5-MHz filter and then to
U17B. The output of U17B is connected
to the 4.5-MHz output sample jack at J29
and through the Jumper W4 on J5 pins 1
& 2, “J”, to the I input of the mixer Z1.

4.1.1.5 Phase Lock Loop (PLL) Circuit

A sample of the signal from the 4.5-MHz
aural VCO at the output of Q13, “M”, is
applied to PLL IC U21 at pin 1 the F

in

connection. In U21, the signal is divided
down to 50 kHz and is compared to a 50­kHz reference signal. The reference signal
is a divided-down sample of the 45.75-MHz
visual IF signal that is applied to the
oscillator-in connection at Pin 27 on the
PLL chip. These two 50-kHz signals are
compared in the IC and the fV, and fR is
applied to the differential amplifier U18A.
The output of U18A, “N”, is fed back
through CR28 and C85 to the 4.5-MHz VCO
IC U16; this sets up a PLL circuit. The

4.5-MHz VCO will maintain the extremely
accurate 4.5-MHz separation between the
visual and aural IF signals; any change in
frequency will be corrected by the AFC
error voltage.

PLL chip U21 also contains an internal lock
detector that indicates the status of the
PLL circuit. When U21 is in a "locked"
state, pin 28 is high. If the 4.5-MHz VCO
and the 45.75-MHz oscillator become
"unlocked," out of the capture range of the
PLL circuit, pin 28 of U21 will go to a logic
low and cause the LED DS5 to light red.
The Aural Unlock LED is viewed through
the front panel of the Assembly. An Aural
unlock, PLL Unlocked, output signal from
Q16 is also applied to jack J41B pin 1B.

Sync tip clamp and the visual and
aural modulator portions of the board

The sync tip clamp and modulator portion
of the board is made up of four circuits:
the main video circuit, the sync tip clamp
circuit, the visual modulator circuit and the
aural modulator circuit.

The clamp portion of the board maintains a
constant peak of sync level over varying
average picture levels (APL). The
modulator portion of the board contains
the circuitry that generates an amplitude­modulated vestigial sideband visual IF
signal output that is made up of the
baseband video input signal (.5 to 1 Vpk­pk) modulated onto a 45.75-MHz IF carrier

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

frequency. The visual IF signal and the
aural IF signal are then combined in the
diplexer circuit to produce the visual IF +
aural IF output, “G”, that is connected to
J41C pin 28C the Combined IF output of
the board.

4.1.1.6 Main Video Signal Path
(Part 1 of 2)

The baseband video input connects to the
board at J41A pins 19A (-), “W”, and 20A
(+), “V”. The +, “V” and -, “W”, video
inputs are fed to Diodes CR1 to CR4 that
form a voltage-limiter network in which,
if the input voltages exceed the supply
voltages for U2B, the diodes conduct,
preventing damage to U2B. CR1 and CR3
conduct if the input voltage exceeds the
negative supply and CR2 and CR4
conduct if the input voltage exceeds the
positive supply voltage. The baseband
video input connects to the non-inverting
and inverting inputs of U2B, a differential
amplifier that minimizes any common­mode problems that may be present on
the incoming signal

The video output of U2B is connected
through the Video Gain pot R42,
accessed through the front panel, to the
amplifier U2A. The output of U2A
connects to the delay equalizer circuits

4.1.1.7 Delay Equalizer Circuits

The delay equalizer circuits provide a
delay to the video signal, correction to
the frequency response, and
amplification of the video signal.

The video output of U2A is wired to the
first of four delay-equalizing circuits that
shape the video signal to the FCC
specification for delay equalization or to
the shape needed for the system. The
board has been factory-adjusted to this
FCC specification and should not be
readjusted without the proper
equipment.

Resistors R53, R63, R61, and R58 adjust
the sharpness of the response curve
while inductors GD1, GD2, GD3, and GD4

adjust the position of the curve. The group
delayed video signal at the output of U3A
is split with a sample connected to J8 on
the board that can be used for testing
purposes of the Post Video Delay signal.
The other portion of the video signal
connects through the Jumper W5 on J9
pins 2 and 3. The video is slit with one
part connecting to a sync tip clamp circuit
and the other part to the main video
output path through R44. A sample of the
video at “P” connects to U32 and U33 that
provide a zero adjust and a 1 Volt output
level, which connects at “T” to J41A pin 3A.
This video level is wired to the
Control/Power Supply assembly.

4.1.1.8 Sync Tip Clamp Circuit

The automatic sync tip clamp circuit is
made up of U6A, Q8, U5C, and associated
components. The circuit begins with a
sample of the clamped video that buffered
by U3A, which is split off from the main
video path that connects to U6A. The level
at which the tip of sync is clamped, to

-1.04 VDC as set by the voltage-divider
network, R77, R78, R75, R76 and R80
connected to U6A. If the video level
changes, the sample applied to U6A
changes. The voltage from the clamp
circuit that is applied to the summing
circuit at the base of Q8 will change; this
will bring the sync tip level back to

-1.04 VDC. Q8 will be turned off and on
according to the peak of sync voltage level
that is applied to U6A. The capacitors C35
and C24, in the output circuit of Q8, will
charge or discharge to the new voltage
level. This will bias U5C more or less,
through the front panel MANUAL/AUTO
CLAMP switch, SW1, when it is in the Auto
Clamp-On position, between pins 2 and 3.
In AUTO CLAMP, U5C will increase or
decrease its output, as needed, to bring
the peak of sync back to the correct level.
The voltage level is applied through U5C to
U2A. In the Manual CLAMP position, SW1
in manual position, between pins 1 and 2,
the adjustable resistor R67 provides the
manual clamp bias adjustment for the
video that connects to U5C. This level is
set at the factory and is not adjustable by
the customer. In Manual clamp the peak

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

of sync auto clamp circuit will not
automatically be clamped to the pre set
level.

4.1.1.9 Main Video Signal Path
(Part 2 of 2)

A sample of the clamped video output
from the group delay circuitry at the
junction of R44, R62 and R300 is
connected to a white clipper circuit
consisting of Q1 and associated circuitry.
The base voltage of Q1 is set by the
voltage divider network consisting of R1,
R9 and R5. R5 is variable and sets the
level of the white clipper circuit to
prevent video transients from over
modulating the video carrier.

The clamped video output of amplifier
U3A is split with one part connected
through R35 to J8 that provides a sample
of the Post Video Delay Signal.

The other clamped video path from U3A
is through jumper W5 on J9 pins 2 & 3
through R44 to a sync-stretch circuit that
consists of Q3 and Q4. The sync-stretch
circuit contains R19, which adjusts the
Sync Stretch Magnitude (amount), R11,
which adjusts the Sync Stretch Cut-In
and R6, which adjusts the Sync Clipping
point. This sync-stretch adjustment
should not be used to correct for output
sync problems, but it can be used for
video input sync problems. The output of
the sync-stretch circuit is amplified by
U31A and connected, “K”, to pin 5, the I
input of Mixer Z2, the Visual IF Mixer.

4.1.1 10 45.75 MHz Oven Oscillator
Circuit

The oven oscillator portion of the board
generates the visual IF CW signal at

45.75 MHz for NTSC system "M" usage.

The +12 VDC needed to operate the
oven is applied through jack J30 pin 1 on
the crystal oven HR1. The oven is preset
to operate at 60° C. The oven encloses
the 45.75 MHz crystal Y1 and stabilizes
the crystal temperature. The crystal is
the principal device that determines the

operating frequency and is the most
sensitive in terms of temperature stability.

Crystal Y1 operates in an oscillator circuit
consisting of transistor Q24 and its
associated components. Feedback that is
provided by a voltage divider, consisting of
C173, L38 and R295, is fed to the base of
Q24 through C169. This circuitry operates
the crystal in a common-base amplifier
configuration using Q24. The operating
frequency of the oscillator is maintained by
a PLL circuit, which consists of ICs U20 and
U22 and associated components, whose
PLL output connects to R293 in the crystal
circuit.

The oscillator circuit around Q24 has a
regulated voltage, +6.8 VDC, which is
produced from the +12 VDC by a
combination of dropping resistor R261,
diodes CR37 and CR38 and Zener diode
VR2. The output of the oscillator at the
collector of Q24 is capacitively coupled
through C165 to the base of Q23. The
small value of C165, 15 pF, keeps the
oscillator from being loaded down by Q23.
Q23 is operated as a common-emitter
amplifier stage whose bias is provided
through R259 from the +12 VDC line. The
output of Q23, at its collector, is connected
to an emitter-follower transistor stage,
Q21. The output of Q21 at its emitter is
split. One path connects to the input of
the IC U20 in the PLL circuit. The other
path is through R270 to establish an
approximate 50-ohm source impedance
through C166 to the Pin 1 contact of the
relay K2. The 45.75 MHz connects through
the closed contacts 0of K2 to a splitter
network consisting of L31 and L32.

NOTE: The relay contacts for the internally
generated 45.75 MHz signal will be closed
unless an external IF signal, such as the IF
for offset and precise frequency 45.74 or

45.76 MHz, connects to the board. The
external IF CW Input connects at J41A pin
32A and is connected to J19 and through
the external cable assembly W10 back to
the board at J20. The external IF CW input
is split on the board. One branch connects
through C157 to a buffer amplifier Q20 to
the K2 relay at pin 14. The other path is

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

through C152 to the amplifier U23A. The
output of U23A is split with one part
connecting to Q26 that shuts down the

45.75 MHz oscillator. Another path
connects to Q25 the conducts and lights
the LED DS7, Alternate IF, viewed on the
front panel. The final path connects
through R268 to Q22 that is biased on
and energizes the relay, K2. The
external IF CW Input at contact 14 now
connects through the closed contact to
the splitter network consisting of L31 and
L32.

Either the internal or external CW IF from
the K2 relay is split with one path
through L31 to the amplifier U28 to the L
input of Z1 the Aural IF Mixer. The other
path is through L32 to the amplifier U29
to the L input of Z2 the Visual IF Mixer.

4.1.1.11 Visual Modulator Circuit

The video signal is heterodyned in mixer
Z2 with the visual IF CW signal (45.75
MHz). The visual IF CW signal from L32
of the splitter connects to U29, where it
is amplified and wired to pin 1, the L
input of mixer Z2. Adjustable capacitor
C168 and resistor R275 are set up to add
a small amount of incidental carrier
phase modulation (ICPM) correction to
the output of the mixer stage to
compensate for any non-linearities
generated by the mixer.

The modulated 45.75-MHz RF output of
mixer Z2, at pin 4 the R output, is
amplified by U30 and is fed to J17
through W8, the external cable
assembly, “WB”, to J13 on the board.
J17 is the visual IF loop-through output
jack that is normally jumpered to J13 on
the board. The modulated visual IF
through J13 connects to J41C pin 17C
the Visual IF Output of the board.

4.1.1.12 Aural Modulator Circuit

The 4.5 MHz aural modulated signal is
heterodyned in mixer Z1 with the 45.75
MHz IF CW signal. The mixer Z1
heterodynes the aural-modulated, 4.5­MHz signal with the 45.75-MHz CW signal

to produce the modulated 41.25-MHz aural
IF signal. The audio modulated 4.5 MHz
from 4.5 MHz VCO IC U16 connects, “J”, to
the I input at pin 5 of Z1. The visual IF CW
signal from L31 of the splitter connects to
U28, where it is amplified and wired to pin
1, the L input of mixer Z1. The R output of
the mixer at pin 4 is fed to a bandpass
filter, consisting of L18-L21, L25-L28 and
C136, C137 and C142-144, that is tuned to
pass only the modulated 41.25-MHz aural
IF signal. The filtered 41.25 MHz is fed to
the amplifier U27. The amplified 41.25­MHz signal is connected by a coaxial cable,
W9, from J21, “WC”, to J18 on the board.
The modulated 41.25-MHz aural IF signal
from J18 is connected to J41C pin 6C the
Aural IF Output of the board.

4.1.1.13 Combining the 45.75 MHz Visual
IF and 41.25 MHz Aural IF Signals

The Visual IF connects back to the board at
J41C pin 3C, through a Visual IF jumper
cable connected to the rear chassis of the
exciter/driver. IF processing equipment
can be connected in place of the jumper if
needed. The visual IF is connected to J12,
through jumper W7, “WA”, to J14. The
visual IF is amplified by U24 and filtered by
FL1 with T1 and T2 providing isolation.
The filtered IF is amplified by U25 and
adjusted in level by R214 before it is
connected to a summing circuit at the
common connection of L16 and L17.

The Aural IF connects back to the board at
J41C pin 23C, through an Aural IF jumper
cable connected to the rear chassis of the
exciter/driver. IF processing equipment
can be connected in place of the jumper if
needed. The aural IF, “F”, is connected
through C132, R234, R235 and adjusted in
level by R243 before it is connected to a
summing circuit at the common connection
of L17 and L16.

The Aural IF and Visual IF signals are
combined through L16 and L17. The
frequency response of the combined 41.25
MHz + 45.75 MHz signal is set by R238
and R239 and associated components. The
corrected combined IF signal is amplified
by U25 and connected to a splitter

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

matching network consisting of T3 and
T4. One part of signal connects to J10,
the 41.25 MHz + 45.75 MHz sample
output jack, located on the front panel.
The other part, “G”, connects to J41C pin
28C the Combined IF Output of the
board.

4.1.1.14 Voltage Requirements

The ±12 VDC needed for the operation of
the board enters through jack J41A pins
25A (+12 VDC) and 26A (-12 VDC). The
+12 VDC is filtered by L6, L7, and C27
before it is connected to the rest of the
board. The +12 VDC also connects to U7,
a 5-volt regulator IC, that provides +5
VDC to the rest of the board.

The -12 VDC is filtered by L5, C16, and
C17 before it is connected to the rest of
the board.

4.2 (A3) IF Processor Module
Assembly (1301938; Appendix B)

The IF from the 8 VSB modulator enters
the module and the signal is pre­corrected as needed for amplitude
linearity correction, Incidental Carrier
Phase Modulation (ICPM) correction and
frequency response correction.

The Module contains the following board.

4.2.1 IF Processor Board (1301977;
Appendix B)

The automatic level control (ALC) portion
of the board provides the ALC and
amplitude linearity correction of the IF
signal. The ALC adjusts the level of the IF
signal that controls the output power of
the transmitter.

The IF from the 8 VSB modulator enters
the board at J1B pin 32B. If the
(optional) receiver tray is present, the IF
input (-6 dBm) from the 8 VSB
modulator tray connects to the
modulated IF input jack J1C Pin 21C. The
modulated IF input connects to relay K3
and the receiver IF input connects to

relay K4. The two relays are controlled by
the Modulator Select command that is
connected to J1C Pin 14C on the board.
Modulator select enable/disable jumper
W11 on J29 controls whether the
Modulator Select command at J1C Pin 14C
controls the operation of the relays. With
jumper W11 on J29 between pins 1 and 2,
the Modulator Select command at J1C Pin
14C controls the operation of the relays;
with jumper W11 on J29, pins 2 and 3, the
modulator is selected all of the time.

4.2.1.1 Modulator Selected

With the modulator selected, J1C-14C low,
this shuts off Q12 and causes Pin 8 on the
relays to go high that causes relays K3 and
K4 to de-energize. When K4 is de­energized, it connects the receiver IF input
at J1C-21C, if present, to a 50Ω load.
When K3 is de-energized, it connects the
modulator IF input at J1B-32B to the rest
of the board; Modulator Enable LED DS5
will be illuminated.

4.2.1.2 External Modulated IF Selected

With the External Modulated IF selected,
J1C-14C high, this turns on Q12 and
makes pin 8 on the relays low that causes
the relays K3 and K4 to energized. When
K4 is energized, it connects the receiver IF
input at J at J1C-21C, if present, to the
rest of the board. When K3 is energized, it
connects to the modulator IF input at J1B­32B to a 50Ω load. The Modulator Enable
LED DS5 will not be illuminated.

4.2.1.3 Main IF Signal Path (Part 1 of 3)

The selected IF input (-6 dBm average)
signal is split, with one half of the signal
entering a bandpass filter that consists of
L3, L4, C4, L5, and L6. This bandpass filter
can be tuned with C4 and is substantially
broader than the IF signal bandwidth. It is
used to slightly steer the frequency
response of the IF to make up for any
small discrepancies in the frequency
response in the stages that precede this
point. The filter also serves the additional
function of rejecting unwanted frequencies
that may occur if the tray cover is off and

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

the tray is in a high RF environment. (If
this is the case, the transmitter will have
to be serviced with the tray cover off in
spite of the presence of other RF signals).
The filtered IF signal is fed through a pi­type matching pad consisting of R2, R3,
and R4 to the pin-diode attenuator circuit
consisting of CR1, CR2, and CR3.

4.2.1.4 Input Level Detector Circuit

The other part of the split IF input is
connected through L2 and C44 to U7. U7
is an IC amplifier that is the input to the
input level detector circuit. The amplified
IF is fed to T4, which is a step-up
transformer that feeds diode detector
CR14. The positive-going detected signal
is then low-pass filtered by C49, L18, and
C50. This allows only the positive digital
peaks to be applied through emitter
follower Q1. The signal is then connected
to detector CR15 to produce a peak
digital voltage that is applied to op-amp
U9A. There is a test point at TP3 that
provides a voltage-reference check of the
input level. The detector serves the dual
function of providing a reference that
determines the input IF signal level to
the board and also serves as an input
threshold detector.

The input threshold detector prevents the
automatic level control from reducing the
attenuation of the pin-diode attenuator to
minimum, the maximum signal output, if
the IF input to the board is removed. The
ALC, input loss cutback, and the
threshold detector circuits will only
operate when jumper W2 on jack J5 is in
the Enabled position, between pins 2 and

3. Without the threshold detector, and
with the pin-diode attenuator at
minimum, the signal will overdrive the
stages following this board when the
input is restored.

As part of the threshold detector
operation, the minimum IF input level at
TP3 is fed through detector CR15 to op­amp IC U9A, pin 2. The reference voltage
for the op-amp is determined by the
voltage divider that consists of R50 and
R51, off the +12 VDC line. When the

detected input signal level at U9A, pin 2,
falls below this reference threshold,
approximately 10 dB below the normal
input level, the output of U9A at pin 1 goes
high, toward the +12 VDC rail. This high is
connected to the base of Q2 that is forward
biased and creates a current path. This
path runs from the -12 VDC line and
through red LED DS1, the input level fault
indicator, which lights, resistor R54, and
transistor Q2 to +12 VDC. The high from
U9A also connects through diode CR16 and
R52, to U24D pin 12, whose output at pin
14 goes high. The high connects through
the front panel accessible ALC Gain pot
R284 and the full power set pot R252 to
U24C Pin 9. This high causes U24C pin 8
to go low. A power raise/lower input from
the Control/Monitoring Module connects to
J42C pin 24C and is wired to Q14. This
input will increase or decrease the value of
the low applied to U24B and therefore
increase or decrease the power output of
the transmitter.

The low connects to U24B pin 5 whose
output goes low. The low is wired to U24A
pin2 whose output goes high. The high is
applied to U10A, pin 2, whose output goes
low. The low connects through the switch
SW1, if it is in the auto gain position, to
the pin-diode attenuator circuit, CR1, CR2
& CR3. The low reverse biases them and
cuts back the IF level, therefore the output
level, to 0. When the input signal level
increases above the threshold level, the
output power will increase, as the input
level increases, until normal output power
is reached.

The digital input level at TP3 is also fed to
a pulse detector circuit, consisting of IC
U8, CR17, Q3, and associated components,
and then to a comparator circuit made up
of U9C and U9D. The reference voltage for
the comparators is determined by a
voltage divider consisting of R243, R65,
R66, and R130, off the -12 VDC line. When
the input signal level to the detector at TP3
falls below this reference threshold, which
acts as a loss-of-digital peak detector
circuit, the output of U9C and U9D goes
towards the -12 VDC rail and is split, with
one part biasing on transistor Q5. A current

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UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

path is then established from the +12
VDC line through Q5, the resistors R69
and R137, and the red LED DS3, input
loss indicator, which is illuminated. When
Q5 is on, it applies a high to the gate of
Q6. This causes it to conduct and apply a
modulation loss pull-down output to
J42C, pin 7C, which is applied to the
front panel display on the
Control/Monitor module.

The other low output of U9C and U9D is
connected through CR18, CR19 & CR20
to jack J5. Jumper W2 on J5, in the
Cutback Enable position, which is
between pins 2 and 3, connects the low
to the base of Q4 that is now forward­biased. NOTE: If jumper W2 is in the
Disable position, between pins 1 and 2,
the auto cutback will not operate. With
Q4 biased on, a negative level
determined by the setting of cutback
level pot R71 is applied to U24D, pin 12.
The level is set at the factory to cut back
the output to approximately 25%. The
output of U24D at pin 14 goes low and is
applied through the power adjust pot to
U24C, pin 9, whose output goes low.

The low connects to U24B, pin 5, whose
output goes low. The low then connects
to U24A, pin 2, whose output goes high.
The high is applied to U10A, pin 2, whose
output goes low. The low connects
through the switch SW1, if it is in the
auto gain position, to the to the pin-diode
attenuator circuit, CR1, CR2 & CR3. The
low reverse biases them and cuts back
the level of the output to approximately
25%.

4.2.1.5 Pin-Diode Attenuator Circuit

The input IF signal is fed to a pin-diode
attenuator circuit that consists of CR1,
CR2 & CR3. Each of the pin diodes
contains a wide intrinsic region; this
makes the diodes function as voltage­variable resistors at this intermediate
frequency. The value of the resistance is
controlled by the DC bias supplied to the
diode. The pin diodes are configured in a
pi-type attenuator configuration where
CR1 is the first shunt element, CR3 is the

series element, and CR2 is the second
shunt element. The control voltage, which
can be measured at TP1, originates either
from the ALC circuit when the switch SW1
is in the ALC Auto position, between pins 2
and 3, or from pot R87 when SW1 is in the
Manual Gain position, between pins 1 and

2.

In the pin diode attenuator circuit,
changing the amount of current through
the diodes by forward biasing them
changes the IF output level of the board.
There are two extremes of attenuation
ranges for the pin-diode attenuators. In
the minimum attenuation case, the
voltage, measured at TP1, approaches the
+12 VDC line. There is a current path
created through R6, through series diode
CR3, and finally through R9 to ground. This
path forward biases CR3 and causes it to
act as a relatively low-value resistor. In
addition, the larger current flow increases
the voltage drop across R9 that tends to
turn off diodes CR1 and CR2 and causes
them to act as high-value resistors. In this
case, the shunt elements act as a high
resistance and the series element acts as a
low resistance to represent the minimum
loss condition of the attenuator (maximum
signal output). The other extreme case
occurs as the voltage at TP1 is reduced and
goes towards ground or even slightly
negative. This tends to turn off (reverse
bias) diode CR3, the series element,
causing it to act as a high-value resistor.
An existing fixed current path from the
+12 VDC line, and through R5, CR1, CR2,
and R9, biases series element CR3 off and
shunt elements, diodes CR1 and CR2, on,
causing them to act as relatively low-value
resistors. This represents the maximum
attenuation case of the pin attenuator
(minimum signal output). By controlling
the value of the voltage applied to the pin
diodes, the IF signal level is maintained at
the set level.

4.2.1.6 Main IF Signal Path (Part 2 of 3)

When the IF signal passes out of the pin­diode attenuator through C11, it is applied
to modular amplifier U1. This device
contains the biasing and impedance-

LX Series, Rev. 0 4-8

UHF Analog Driver/Transmitter Chapter 4, Circuit Descriptions

matching circuits that makes it operate
as a wide-band IF amplifier. The output
of U1 connects to J40 that is jumpered to
J41. The J40 jack is available, as a
sample of the pre-correction IF for
troubleshooting purposes and system
setup. The IF signal is connector to a
splitter Z1 that has an in phase output
and a 90° Quadrature output, which are
then connected to the linearity corrector
portion of the board.

4.2.1.7 Amplitude and Phase
Pre-Correction Circuits

The linearity corrector circuits use three
stages of correction, two adjust for any
amplitude non-linearities and one for
phase non-linearities of the output signal.
Two of the stages are in the in phase
amplitude pre-correction path and one
stage is in the quadrature phase pre­correction path. Each stage has a
variable threshold control adjustment,
R211 and R216, in the in phase path,
and R231, in the quadrature path, that
determines the point at which the gain is
changed for that stage.

Two reference voltages are needed for
the operation of the corrector circuits.
The Zener diode VR3, through R261,
provides the +6.8 VDC reference. The
VREF is produced using the path through
R265 and the diodes CR30 and CR31.
They provide a .9 VDC reference, which
temperature compensates for the two
diodes in each corrector stage.

The first corrector stage in the in phase
path operates as follows. The in phase IF
signal is applied to transformer T6, which
doubles the voltage swing by means of a
1:4 impedance transformation. Resistors
R222 and R225 form an L-pad that
lowers the level of the signal. The input
signal level when it reaches a certain
level causes the diodes CR24 and CR25
to turn on, generating current flow that
puts them in parallel with the L-pad.
When the diodes are put in parallel with
the resistors, the attenuation through the
L-pad is lowered, causing signal stretch.

The signal is next applied to amplifier U17
to compensate for the loss through the
L-pad. The breakpoint, or cut-in point, for
the first corrector is set by controlling
where CR24 and CR25 turn on. This is
accomplished by adjusting the threshold
cut-in resistor R211. R211 forms a
voltage-divider network from +6.8 VDC to
ground. The voltage at the wiper arm of
R211 is buffered by the unity-gain
amplifier U16B. This reference voltage is
then applied to R215, R216, and C134
through L44 to the CR24 diode. C134
keeps the reference from sagging during
the vertical interval. The .9 VDC reference
voltage is applied to the unity-gain
amplifier U16D. The reference voltage is
then connected to diode CR25 through
choke L45. The two chokes L44 and L45
form a high impedance for RF that serves
to isolate the op-amp ICs from the IF.

After the signal is amplified by U17, it is
applied to the second corrector stage in the
in phase path through T7. These two
correctors and the third corrector stage in
the quadrature path operate in the same
fashion as the first. All three corrector
stages are independent and do not interact
with each other.

The correctors can be disabled by moving
jumper W12 on J30 to the Disable position,
between pins 1 and 2, this moves all of the
breakpoints past the greatest peaks of
digital so that they will have no affect.

The pre-distorted IF signal in the in phase
path, connects to an op amp U18 whose
output level is controlled by R238. R238
provides a means of balancing the level of
the amplitude pre-distorted IF signal that
then connects to the combiner Z2.

The pre-distorted IF signal in the
quadrature path connects to op amp U20
and then step up transformer T9, next op
amp U21 and step up transformer T10 and
finally op amp U22 whose output level is
controlled by R258. R258 provides a
means of balancing the level of the Phase
pre-distorted IF signal that then connects
to the combiner Z2.

LX Series, Rev. 0 4-9