UBS Axcera 425A User Manual

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

Chapter 3

Circui t Des c riptions

3.1 (A4) High-Band VHF Exciter
(1070901; Appendix C)

3.1.1 (A4) Aural IF Synthesizer
Board, 4.5 MHz (1265-1303;
Appendix D)

The aural IF synthesizer board amplifies
each of the three possible audio i nputs
and the amplifier circuits that supply the
single audio output. The balanced audio
or the composite audio input is connected
to the board while the subcarrier audio
(SCA) input can be connected at the
same time as either of the other two
inputs. The board has the 4.5-MHz
voltage-controlled oscillator (VCO) and
the aural modulation circuitry that
produces the modulated 4.5-MHz output.
The board also contains a phase lock loop
(PLL) circuit that maintains the precise

4.5-MHz separation between the aural
(41.25 MHz) and the v isual (45.75 MHz)
IF frequencies.

3.1.1.1 Balanc ed Audio Input

The first of the three possible baseband
inputs to the board is a 600Ω-balanced
audio input (+10 dBm) that enters
through jack J2, pins 1 (+), 2 (GND), and
3 (-), and is buffered by U1B and U1C.
Diodes CR1 to CR4 protect the input
stages of U1B and U1C if an excessive
sig nal le ve l is pr e s en t on th e inp u t lea d s
of jack J2. The outputs of U1B and U1C
are applied to differential amplifier U1 A;
U1A eliminate s the common mode
signals (hum) on its input leads. A
pre-emphasis of 75 ms is provided by
R11, C11, and R10 and can be eliminated
by removing jumper W5 on J5. The signal
is then applied to amplifier U1D whose
gain is controlled by jumper W3 on J11.
Jumper W3 on jack J11 is positioned
ac co rd ing to th e i np ut le vel of t he audio
signal (0 or +10 dBm). If the input level
is approximately 0 dBm, the mini-jumper
should be in the high gain position

between pins 1 and 2 of jack J 11. If the
input level is approximately +10 dBm,
the mini-jumper should be in low gain
position between pins 2 and 3 of jack
J11. The balanced audio is then
connected to buffer amplifier U2A whose
input level is determined b y the se tting of
balanced audio gain pot R13. The output
of the amplifier stage is wired to the
summing point at U2D, pin 13.

3.1.1.2 Composite Audio Input

The second possible audio input to the
board is the composite audio (stereo)
input at BNC jacks J3 and J13. The two
jacks are loop-through connected; as a
result, the audio can be used in another
application by connecting the unused
jack and removing W4 from J12. Jumper
W4 on jack J12 provides a 75Ω-input

impedance when the jumper is between
pins 1 and 2 of jack J12 and a high
impedance when it is between pins 2 and

3. Diodes CR9 to CR12 protect the input
stages of U6A and U6B if an excessive
signal level is applied to the board. The
outputs of U6A and U6B are applied to
differential amplifier U2C, which
eliminates common mode signals (hum)
on its input leads. The composite input
signal is then applied to amplifier U2B;
the gain of this amplifier is controlled by
composite audio gain pot R17. The
composite audio signal is connected to
the summing point at U2D, pin 13.

3.1.1.3 Sub carrier Audio Input

The third possible input to the board is
the SCA input at BNC jack J4. The SCA
input has an input impedance of 75Ω that
can be eliminated by removing jumper
W2 from pins 1 and 2 of J14. The SCA
input is bandpass filtered by C66, C14,
R22, C15, C67, and R23 and is fed to
buffer amplifier U3A. The amplified signal
is then applied though SCA gain pot R24
to the summing point at pin 13 of U2D.

425A, Rev. 0 3-1

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

3.1.1.4 Audio Modulation of the VCO

The balanced audio, or the composite
audio and/or the SCA-buffered audio
signals, are fed to the common junction
of resistors R14, R20, and R27 that
connect to pin 13 of amplifier U2D. The
output audio signal at pin 14 of U2D is
typically .8 Vpk-pk at a ±25-kHz
deviation for balanced or .8 Vpk-pk at
±75-kHz deviation for composi t e as
measured at TP1. This signal is applied to
VCO U10. A sample of the deviation level
is amplified, detected by U7A and U7B,
and connected to J10 on the board. This
audio-deviation level is connected to the
front panel meter th rough the transmitter
control board.

The audio is connec ted to CR13 to CR16;
these are varactor diodes that frequency
modulate the audio signal onto the
generated 4.5-MHz signal in U10. U10 is
the 4.5-MHz VCO tha t generates the 4.5­MHz continuous wave (CW ) signal. The
output frequency of this signal is
maintained and controlled by the
correction voltage output of U5 PLL IC.
The audio-modulated, 4.5-MHz signal is
fed to amplifiers U11A and U11B. The
outp ut of U11B is connected to the 4.5­MHz output jacks at J7 and J8.

3.1.1.5 Pha se Lock Loop (PLL) Circuit

A sample of the signal from the 4.5-MHz
aural VCO at the output of U11A is
applied to PLL IC U5 at the F

in

connection. In U5, the signal is divided
down to 50 kHz and is com pared to a 50­kHz reference signal. The reference
signal is a divided-down sample of the
visual IF, 45.75-MHz signal that is
applied to the oscil lator-in connection on
the PLL chip through jack J6 on the
board. These two 50-kHz signals are
compared in the IC and the fV, and fR is
applied to the differential amplifier U3B.
The output of U3B is fed back through
CR17 to the 4.5-MHz VCO IC U10; this
sets up a PLL circuit. The 4.5-MHz VCO
will maintain the extremely accurate 4.5­MHz separation between the visual and

aural IF signals; any change in frequency
will be corrected by the AFC error
voltage.

PLL chip U5 also contains an internal lock
detecto r that indicates the status of the
PLL ci rc u it. When U5 is in a "locked "
state, pin 28 goes high and causes the
green LED DS1 to illuminate. I f the 4.5­MHz VCO and the 45.75-MHz oscillato r
become "unlocked," out of the capture
range of the PLL circuit, pin 28 of U5 will
go to a logic low and cause the red LED
DS2 to light. A mute output signal from
Q3 (unlock mute) will be applied to jack
J9. This mute is connected to the
transmitter contro l board.

3.1.1.6 Voltage Requirements

The ±12 VDC needed for the operation of
the board enters through jack J1. The
+12 VDC is connected to J1-3 and
filtered by L2, C3, and C4 before it is
connected to the rest of the board. The

-12 VDC is connected to J1-5 and filtered
by L1, C1, and C2 before it is connected
to the rest of the board. +12 VDC is
connected to U8 and U9; these are 5-volt
reg ulat or ICs that provide the voltage to
the U10 and U5 ICs.

3.1.2 (A5) Sync Tip Clamp/
Modul ator Board (1265-1302;
Appendix D)

The sync tip clamp/modulator board can
be divided into five circuits: the main
video circuit, the sync tip clamp circuit,
the visual modulator circuit, the aural IF
mixer circuit, and the diplexer circuit.

The sync tip clamp/modulator board
takes the baseband video or 4.5-MHz
composite input that is connected to the
video input jack (either J1 or J2, which
are loop-through connected), and
produces a modulated visual IF + aural
IF output at output jack J20 on the
board. The clamp portion of the board
maintains a constant peak of sync level
over varying average picture levels
(APL). The modulator portion of the

425A, Rev. 0 3-2

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

board contains the circuitry that
generates an amplitude-modulated
vestigial sideband visual IF signal output
that is made up of the baseband video
input signal (1 Vpk-pk) modulated onto
an externally generated 45.75-MHz IF
carrier frequency. The visual IF signal
and the aural IF signal are then
com bined in the diplexer circuit to
produce the visual IF + aural IF output
that is connected to J20, the IF output
jack of the board.

3.1.2.1 Main Video Signal Path (Part 1 of

2)

The baseband video or the 4.5-MHz
composite input connects to the b oard at
J2. J2 is loop-through connected to J1
and terminated to 75 watts if jumper W4
is on jack J3. With jumper W4 removed,
the input can be connected to another
transmitter throu gh J1; J1 is loop­through connected to J2.

Test point TP1 is provided to monitor the
level of the input. The input is f ed to the
non-inverting and inverting inputs of
U1 A, a differential amplifier that
minimizes any common-mode hum that
may be present on the incoming signal.
Diodes CR1 to CR4 form a voltage- limiter
netw ork in wh ic h, if the inp ut volta g es
exceed the supply voltages for U1A, the
diodes conduc t, preventing damage to
U1A. CR1 and CR3 conduct if the input
voltage exceeds the negative supply and
CR2 and CR4 conduct if the input voltage
exceeds the p ositive supply voltage.

The video output of U1A is connected to
J22 on the board. Normally, the video at
J22 is jumpered to J27 on the board. If
the 4.5-MH z comp os ite input ki t is
purchased, the 4.5-MHz composite signal
at J22 connects to the external composite

4.5-MHz filter board and the 4.5-MHz
bandpass filter board. These two boards
provide the video-only signal to J27 and
the 4.5-MHz intercarrier signal to J28
from the 4.5-MHz composite input. The
video through the video gain pot R12

(adjusted for 1 Vpk-pk at TP2) connects
to amplifier U1B.

The output of U1B, if the delay equalizer
board is present in the tray, connects the
video from J6, pin 2, to the external
delay equalizer board and back to the
sync tip clamp/modulator board at J6,
pin 4. If the delay equalizer is not
present, the video connects through
jumper W1 on J5, pins 1 and 2. The
delay equalizer board plugs directly to J6
on the sync tip clamp/modulator board.
The video from J6, pin 4, is then
connected through jumper W1 on J5,
pins 2 and 3, to the amplifier Q1. The
output of Q1 connects to Q2; the base
voltage of Q2 is set by the DC offset
voltage output of the sync tip clamp
circuit.

3.1.2.2 Sync Tip Clamp Circuit

The automatic sync tip clamp circuit is
made up of U4A, Q7, U3B, and
associated components. The circuit
begins with a sample of the clamped
video that is split off from the main v ideo
path at the emitter of Q3. The video
sample is buffered by U3A and connected
to U4A. The level at which the tip of sync
is clamped, approximately -1.04 VDC as
measured at TP 2, is set by the voltage­divider network connected to U4A. If the
video level changes, the sample applied
to U4A changes. If jumper W7 on J4 is in
the Clamp-On position, the voltage from
the clamp circuit tha t is applied to the
summing circuit at the base of Q2 will
change; this will bring the sync tip level
back to approximately -1.04 VDC. Q7 will
be turned off and on according to the
peak of s ync voltage level that is applied
to U4A. The capacitors C14, C51, C77,
and C41 will charge or discharge to the
new voltage level, which biases U3B
more or less, through jumper W7 on J4
in the Auto Clamp -On pos ition. U3 will
increase or decrease its output, as
needed, to bring the peak of sync back to
the correct level as set by R152 and R12.
This vo l ta g e le v el is ap p l ied th rough U3B
to Q2. In the Manual position, j umper W7

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500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

on J4 is in the Clamp-Off position,
between pins 1 and 2, and adjustable
resistor R41 provides the manual clamp
bias adjustment for the video that
connects to Q2.

Jumper W6 on jack J35 must be in the
Normal position, between pins 2 and 3,
for the clamp ci rcuit to operate with a
normal non-scrambled signal. If a
scrambled signal is used, the tray is
operated with jumper W6 in the Encoded
position, connected between pins 1 and

2. The clamp circuit is set by adjusting
depth of modulation pot R152 for the
correct depth of modulation as measured
at TP2.

Depending on the input video level, the
waveform as measured at TP2 may not
be 1 Vpk-pk. If W7 on J4 is moved to the
Clamp-Off (Manual) position, between
pins 1 and 2, the clamp level is adjusted
by R41 and will not automatically be
clamped to the set level. The output of
buffer amplifier U3A drives the sync tip
clamp circuit consisting of differential
amplifier U4A, FET Q 7, and b uffer
amplifier U3B. U4A is biased by R124,
R125, R184, R152, and R126 so that the
clamped voltage level at peak of sync is
approximately -1.04 VDC as measured at
TP2.

3.1.2.3 Main Video Signal Path (Part 2 of

2)

The clamped video from Q2 is connected
to white clipper circuit Q3. Q3 is adjusted
with R20 and set to prevent video
transients from overmodulating the video
carrier. The clamped video is connected
to sync clipper circuit Q4 (adjusted by
R24); Q4 limits t he sync to -40 IRE units.
The corrected video connects to emitte r
follower Q4 whose output is wired to
unity gain amplifier U2A and provides a
low-impedance, clamped video output at
pin 1.

3.1.2.4 Visual Modulator Circuit

The clamped video signal from U2A is
split. One part connects to a metering
circuit, consisting of U20 and associated
components, that produces a video
output sample at J8-6 and connects
through the transmitter contro l boa rd to
the front panel meter for monitoring. The
other clamped video path from U2A is
through a sync-stretch circuit that
consists of Q5 and Q6. The sync-stretch
circuit contains R48; R48 adjusts the
sync stretch magnitude (amount) and
R45 adjusts the cut-in. This sync-stretch
adjustment should not be used to correct
for output sync problems, but it can be
used for video input sync problems. The
output of the sync-stretch circuit
connects to pin 5, the I input of mixer
Z1.

The video signal is heterodyned in mixer
Z1 with the visual IF CW signal (45.75
MHz). The visual IF CW signal enters the
board at jack J15 and is connected to U9,
where it is amplified and wired to pin 1,
the L input of mixer Z1. The adjustable
capacitor C78 and resistor R53 are set up
to add a small amount of inciden tal
carrier phase modulation (ICPM)
correction to the output of the mixer
stage to compensate for any non­linearities generated by the mixer.

The modulated 45.75- MHz RF output of
mixer Z1 is amplified by U5 and is fed to
double-sideband visual IF output jack
J18. The level of this output jack is
adjusted by R70. J18 is the visual IF
loop-th r ough outp ut jack that is normally
jumpered to J19 on the board. If the
optional visual IF loop-through kit is
purchased, the visual is connected out of
the board to any external IF processor
trays.

After any external processing, the
modulated visual IF, double-sideband
signal re-enters the board through J19.
The visual IF from J19 is amplified by
U10 and U11 and routed through the
vestigial sideband filter network,

425A, Rev. 0 3-4

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

consisting of T1, FL1, and T2, and
produces a vestigial sideband visual IF
signal output. The filtered vestigial
sideband visual IF is amplified by U7 and
connected to a T-type attenuator. R62
can be adjusted to set the visual IF gain;
this is the amount of visual IF signal that
is coupled to amplifier IC U8. R63 and
C30 are adjusted for the best VSBF
frequency response. The amplified IF
signal is fed to the input of the diplexer
circuit that consists of R76, L13, and L12.
A detected voltage sample of the visual
IF is available at test point TP5.

3.1.2.5 41. 25-MHz Aural IF Circuit

On this board, the 41.25-MHz aural IF is
created by mixing the modulated 4.5­MHz a u ra l interca r ri e r sign a l, p rod uc e d
by the aural IF synthesizer board or from
the composite 4.5-MHz filter board, with
the 45.75-MHz CW signal produced by
the 45.75-MHz IF carrier oven oscillator
board. The modulated 4.5-MHz aural
intercarrier signal enters the board at J14
or J28 and is connected to IF relay K1.
Jumper W3 on J7 determines whether
the 4.5-MHz used by the board is
internally generat ed or from an external
source. With jumper W3 connected
between pins 2 and 3, the 4.5 MHz from
the aural IF synthesizer board or from
the 4.5- M H z comp o site i np ut is
connected to mixer Z2. If an external

4.5-MHz signal is used, it enters the
board at J12 and is fed through gain pot
R88 to amplifier IC U13A. The amplified

4.5 MHz is then connected to J7 and, if
jumper W3 is between pins 1 and 2, the

4.5-MHz signal from the external source
is connected to the mixer. Mixer Z2
heterodynes the aural-modulated, 4.5­MHz signal with the 45.75-MHz CW signal
to produce the modulated 41.25-MHz
aural IF signal.

For normal ope ration, the 41.25-MHz
signal is jumpered by a coaxial cable
from J16 to J17 on the board. If the
(optional ) aural IF loop-through kit is
purchased, the 41.25-MHz signal is
connected to the rear of the tray, to
which any processing trays can be
connected, and then back to jack J17 on
the board. The modulated 41.25-MHz
aural IF signal f rom J17 is connected
through amplifier ICs U15 and U16. The
amplified output is connected to the
attenuator-matching circuit that is
adjusted by R85. R85 increases or
decreases the level of the 41.25 MHz that
sets the A/V rat io for the diplexer circuit.
The diplexer circuit takes the modulated

45.75-MHz vis ual IF and the modulated
aural IF and combines them to produce
the 45.75-MHz + 41.25-MHz IF output.
The combined 45.75-MHz + 41.25-MHz
IF signal is amplified by U12 and
connected to combined IF output jack
J20 on the board. A sample of the
combined IF output is provided at J21 on
the board. If a NICAM input is used, it
connects to J36 on the board. The level
of the NICAM signal is set by R109 before
it is fed to the diplexer circuit consisting
of L28, L29, and R115. This circuit
combines the NICAM signal with the

45.75-MHz vis ual IF + 41.25-MHz aural
IF signal.

3.1.2.6 Operational Voltages

The +12 VDC needed to operate the
transmitter control bo ard enters the
board at J23, pin 3, and is filtered by
L26, L33, and C73 before it is fed to the
rest of the board.

The -12 VDC needed to operate the
board enters the board at J23, pin 5, and
is filtered by L27 and C74 before being
fed to the rest of the board.

The output of the mixer is fed to a
bandpass filter that is tuned to pass only
the modulated 41.25-MHz aural IF signal
that is fed to jack J16, the 41.25-MHz
loop-through out jack of the board.

425A, Rev. 0 3-5

3.1.3 (A6) Delay Equalizer Board
(1227-1204; Appendix D)

The delay equalizer board provides a
delay to the video signal, correction to

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

the frequency response, and
amplification of the video signal.

The video signal enters the board at J1-2
and is connected to a pi-type, low-pass
filter consisting of C16, L7, and C17. This
filter eliminates any unwanted higher
frequencies from entering the board. The
output of the filter is connected to
amplifier stage U1; the gain is controlled
by R29. The video output of the amplifier
stage is wired to the first of four delay­equalizing circuits that shape the video
signal to the FCC specification for delay
equalization or to the desired shape
needed for the system. The board has
been factory-adjusted to this FCC
specification and should not be
readjusted without the proper
equipment.

Resistors R7, R12, R17, and R22 adjust
the sharpness of the response curve
while inductors L1, L2, L3, and L4 adjust
the position of the curve. With a delay
equalizer test generator signal or a sine
x/x video test pattern input, the resistors
and inductors can be adjusted, while
monitoring a Tektronix VM700 test
measurement set, until the desired FCC
delay equalization curve or system curve
is attained. The delay-equalized video
signal is connected to J1-4, the video
output of the board. A sample of the
delayed video signal is connected to J2
on the board and can be used for testing
purposes.

The ±12 VDC needed to operate the
board enters the board at J1. The +12
VDC connects to J1-9, which is filtered by
L5 and C11 before it is directed to the
rest of the board. The -12 VDC connects
to J1-6, which is filtered by L6 and C12
before it is directed to the rest of the
board.

The +12 VDC is applied through jack J10
to crystal oven HR1, which is pre set to
operate at 60° C. The oven encloses
crystal Y1 and stabilizes the crystal
temperature. The c rystal is the principal
device tha t determ ines th e operat ing
frequency and is the most sensitive in
terms of temperature stabi lity.

Crystal Y1 operates in an oscillator circuit
consisting of transisto r Q1 and its
associated components. Feedback is
provided through a capacito r-voltage
divider, consisting of C5 and C6, that
operates the crystal in a common-base
amplifier configuration using Q1. The
operat ing frequency of the oscillator can
be adjusted by variable capacitor C17.
The oscillator circuit around Q1 has a
separate regulated voltage, 6.8 VDC,
which is produced by a combination of
dropping resistor R4 and zener diode
VR1. The output of the oscillator at the
collector of Q1 is capacitively coupled
through C8 to the base of Q2. The small
value of C8, 10 pF, keeps the oscil lator
from being loaded down by Q2.

Q2 is operated as a common-emitter
amplifier stage whose bias is provided
through R8 from the +12 VDC line. The
output of Q2, at its collector, is split
between two emitter-follower transistor
stages, Q3 and Q4. The output of Q3 is
taken from its emitter through R11 to
establish an approximate 50-ohm source
impedance through C11 to J3, the main
output jack. This 45.75-MHz signa l is a t
about the +5 dBm power level. In most
systems, this output is either directed to
a visual modulator board or to some
splitting and amplifying arrangement that
distributes the visual IF carrier for other
needs. The second output from the
collector of Q2 is fed to the base of Q4,
the emitte r follow er trans isto r.

3.1.4 (A7) IF Carrier Oven Oscillator
Board (1191-1404; Appendix D)

The IF carrier oven oscillator board
generates the visual IF CW signal at

45.75 MHz for NTSC system "M" usage.

425A, Rev. 0 3-6

Q4 drives two different output circuits.
One output is directed through voltage
dividers R14 and R15 to jack J2 and is
meant to be fed to a frequency counter.
While monitoring J2 the oscillator can be
set exactly on the operating frequency

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

(45.75 MHz) by adjusting C17. The
output at J2 is at a power level of
approximately -2 dBm, which is sufficient
to drive most frequency counters. The
other output of Q4 connects to prescaler
chip U1, which divides the signal by 15.
The output of U1 is applied to U2, a
programmable divider IC. U2 is
programmed through pins 11 to 20 to
divide by 61. This results in a 50-kHz
signal at pin 9 that is available as an
output at J1. The output of 50 kHz is
generally used in systems where the
visual IF carrier oven oscillator is used as
the reference for a PLL circuit; an
example of this is when the PLL circuit
uses the aura l IF synthesizer board and
the aural VCO. The 50-kHz CMOS output
at jack J1 is not capable of achieving
enou g h dr iv e le ve l f o r a lo ng coa x ial
ca b le leng th. As a res u lt, w he n a lo ng
coaxia l cable is needed, the output at
jack J5 is utilized. The push-pull
transistor stage Q5 and Q6, along with
em itter resistor R18, provide a large-load
output capability at J5.

The stages U1, U2, Q5, and Q6 are
powered by +5.1 VDC, which is obtained
by using the +12 VDC line voltage, and
voltage-dropping resistor R16 and zener
diode VR2.

the (optio nal) rec e iv e r tray is pre sent,
the visual + aural IF input (0 dBm) from
the receiver tray connects to receiver IF
input jack J1. The modulator IF input
connects to relay K3 and the receiver IF
input connec ts to relay K4. T he two
relays are controlled by t he Modulator
Select command that is connected to J30
on the board. Modulator select
enable/disable jumper W11 on J29
controls whether the Modulator Sele ct
command at J30 controls the operation of
the relays or not. With jumper W11 on
J29, pins 1 and 2, the Modulat or Select
command at J30 controls the operation of
the relays; with jumper W11 on J29, pins
2 and 3, the modulator is selected all of
the time.

3.1.5.1 Modulator Selected

With the modulator selected, J11-10 and
J11-28 on the rear of the UHF exciter
tray are connected together; this makes
J30 lo w and ca us es re la ys K3 and K4 to
de-ene rgize. Wh en K4 is de-ene rgi zed, it
connects the receiver IF input at J1, if
present, to 50 watts. When K3 is de­energized, it connects the modulator IF
input at J32 to the rest of the board;
Modulator Enable LED DS5 will be
illuminated.

The +12 VDC power is applied to the
board through jack J4, pin 3, and is
isolated from the RF signals which may
oc c ur in th e +1 2 VDC l in e through th e
use of RF choke L2 a nd filter capacitor
C10.

3.1.5 (A8) ALC Board, NTSC (1265­1305; Appendix D)

The automatic level c ontrol (ALC) board
provides the ALC and amplitude linearity
correction of the IF signal. The ALC
adjusts the level of the IF signal through
the board to control the output power of
the transm itte r.

The visual + aural IF input (0 dBm)
signal from the modulator enters the
board at modulator IF input jack J32. If

425A, Rev. 0 3-7

3.1.5.2 Receiver Selected

With the receiver selected, which is J11­10 and J11-28 on the rear of the UHF
exciter tray (connected to J30 on the
board) not connected together, relays K3
and K4 are energized. When K4 is
energized, it connects the receiver IF
input at J1, if present, to the rest of the
board. When K3 is energized, it connects
to the modulator IF input at J32 to 50
watts; Modulator Enable LED DS5 will be
illuminated.

3.1.5.3 Main IF Signal Path (Part 1 of 3)

The selecte d visual + aural IF input (0
dBm) signal is split, with one half of the
signal entering a bandpass filter that
consists of L3, L4, C4, L5, and L6. This

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

bandpass filter can be tuned with C4 and
is substantially broader than the IF signal
bandwidth. It is used to slightly steer the
frequency resp onse of the IF to make up
for any small discrepancies in the
frequency response in the stages that
precede this point. The filter also serves
the additional function of rejecting
unwanted frequenc ies that may occur if
the tray cover is off and the tray is in a
high RF environment (if this is the c ase,
the transmitter will have to be serviced
with the tray cover off in spite of the
presence of other RF signals). The
filtered IF signal is fed through a pi-type
matching pad consisting of R2, R3, and
R4 to the pin-diode attenuator circuit
consisting of CR1, CR2, and CR3.

3.1.5.4 Input Level Detector Circuit

The other part of the split IF input is
connected through L2 and C44 to U7; U7
is an IC amplifier that is the input to th e
input level detector circuit. The amplified
IF is fed to T4; T4 is a step-up
transformer that feeds diode detector
CR14. The positive-going detected signal
is then low-pas s filtered by C49, L18, and
C50. This allows only the video with
positive sync to be applied through
emitter follower Q1. The sig nal is then
connected to detector CR15 to produce a
peak-sync voltage that is applied to op­amp U9A. There is a test point at TP3
that provides a voltage reference check
of the input level. The dete ctor serves
the dual function of providing a reference
that determines the input IF signal level
to the board and also serves as an input
threshold detector.

The input threshold detector prevents the
automatic level control from reducing the
attenuation of the pi n-diode at tenuator to
minimum (the maximum signal) if the IF
input to the board is removed. The ALC,
video loss cutback, and the threshold
detector circuits will only operate when
jumper W3 on jack J6 is in the Auto
position, between pins 1 and 2. Without
the threshold detector, and with the pin­diode attenuator at minimum, when the

signal is restored it will overdrive the
stages following this board.

As part of the threshold detector
operation, the minimum IF input level at
TP3 is fed through detector CR15 to op­amp IC U9A, pin 2. The reference voltage
for the op-amp is determined by the
voltage divider that consists of R50 and
R51 (off the +12 VDC line). When the
detected-input signal level at U9A, pin 2,
falls below this re ference t hreshold
(approximately 10 dB below the normal
input level), th e output of U9A at pin 1
goes to the +12 VDC rail. This high is
connected to the base of Q2. At this
point, Q2 is forward biased and creates a
current path from the -12 VDC line and
through red LED DS1, the input level
fault indicator, which becomes lit, resistor
R54, and transistor Q2 to +12 VDC. The
high from U9A also connects through
diode CR16 to U9B, pin 5, who se output
at pin 7 goes high. The high connects
through range adjust pot R74 to J20,
which connects to the front panel­mounted power adjust pot. This high
connects to U10A, pin 2, and causes it to
go low at output U10A, pin 1. The low is
applied through jumper W3 on J6 to the
pin-diode attenuator circuit that cuts
back the IF level and, therefore, the
output power le vel, to 0. When the input
signal level increases above the threshold
level, the output power will raise, as the
input level increases, until normal output
power is reached.

The video input level at TP3 is also fed to
a sync-separator circuit, consisting of IC
U8, CR17, Q3, and associated
components, and then to a com parator
circuit made up of U9C and U9D. The
reference voltage for the comparators is
determined by a voltage divider
consisting of R129, R 64, R65, R66, and
R130 (off the -12 VDC line). When the
input signal level to the detector at TP3
falls below this re ference t hreshold,
which acts as a loss of sync detector
circuit, the output of U9C and U9D goes
towards the -12 VDC rail and is spl it, with
one part biasing on transistor Q5. A

425A, Rev. 0 3-8

500-Watt UHF Transmitter Chapter 3, Circuit Descriptions

curren t path is then established from the
+12 VDC li ne through Q5, the resistors
R69, R137, and the red LED DS3 (video
loss indicator), which becomes lit. When
Q5 is on, it applies a high to the gates of
Q6 a nd Q7. This causes them to conduct
and apply video loss fault pull-down
outputs to J18, pins 5 and 2.

The other low output o f U9C and U9D is
connected through CR20 to jack J5.
Jumper W2 on J5, in the Cutback Enable
position (between pins 2 and 3),
connects the low to the base of the
forward-biased Q4. If jumper W2 is in
the Disable position, between pins 1 and
2, the auto cutback will not operate. With
Q4 biased on, a level determi ned by the
se tting of cutback leve l pot R71, which is
set at the factory to cut back the output
to approximately 25%, is applied to U9B,
pin 5. The output of U9B at pin 7 goes
low and is applied through the power
adjust pot to U10A, pin 2, whose output
goes low. This low is applied t o the pin­diode attenuator to cut back the level of
the output to approxim ately 25%.

3.1.5.5 Pin- Diode Attenuator Circuit

The input IF signal is fed to a pin-diode
attenuator circuit that consists of CR1 to
CR3. Each of the pin diodes contain a
wide intrinsic region; this makes the
diodes function as voltage-var iable
resistors at this intermediate frequency.
The value of the resistance is controlled
by the DC bias supplied to the diode. The
pin diodes are configured in a pi-type
attenuator configuration where CR1 is
the first shunt e lement, CR3 is the series
element, and CR2 is the second shunt
element. The control voltage, which can
be measured at TP1, origina tes either
from the ALC circuit when jumper W3 on
J6 is in the ALC Auto posit ion, between
pins 1 and 2, or from pot R87 when the
jumper is in the Manual Gain position.

On the pin-diode attenuator circuit, a
current path exists from J6 through R6
and then through the diodes of the pin
attenuator. Changing the amount of

current through the diodes by forward
biasing them changes the IF output level
of the board. There are two extremes of
attenuation ranges for the pin-diode
attenuators. In the minimum attenuation
case, the voltage, m easured at TP1,
approaches the +12 VDC line. There is a
current path created through R6, through
series diode CR3, and f inally through R9
to ground. This path forward biases CR3
and causes it to act as a relatively low­value resistor. In addition, the larger
current flow increases the voltage drop
across R9 that tends to turn off diodes
CR1 and CR2 and causes them to act as
high-value resistors. In this case, the
shunt elements act as a high resistance
and the s eries element acts as a low
resistance to represent the minimum loss
condition of the attenuator (maximum
signal output). The other extreme case
occurs as the voltage at TP1 is reduced
and goes towards ground or even slightly
negative. This tends to turn off (reverse
bias) diode CR3, the series element,
causing it to act as a high-value resistor.
An existing fixed cur rent path from the
+12 VDC line, and through R5, CR1,
CR2, and R9, biases series element CR3
off and shunt elements, diodes CR1 and
CR2 on, causing them to a ct as relatively
low-va lue resis to rs. T his rep resen ts the
maximum attenuation case of the pin
attenuator (minimum signal output). By
controlling the value of the voltage
applied to the pin diodes, the IF signal
level is maintained at the set level.

3.1.5.6 Main IF Signal Path (Part 2 of 3)

When the IF signal passes out of the pin­diode attenuato r throug h C11, it is
applie d to modular amplifier U1. This
device includes within it the biasing and
impedance matching circuits that makes
it operate as a wide-band IF amplifier.
The output of U1 is available, as a
sample of the pre-correction IF for
troubleshooting purposes and system
setup, at jack J2. The IF signal is then
connected to the linearity corrector
portion of the board.

425A, Rev. 0 3-9