Ublox TOBY-R2 Series, TOBY-R200-02B, TOBY-R202-02B, TOBY-R200-82B, TOBY-R200-42B System Integration Manual

Abstract

This document describes the features and the system integration of TOBY-R2 series multi-mode
cellular modules. These modules are a complete, cost efficient and performance optimized LTE
Cat 1 / 3G / 2G multi-mode solution covering up to four LTE bands, up to four 3G UMTS/HSPA bands
and up to four 2G GSM/EGPRS bands in the compact TOBY LGA form factor.

www.u-blox.com

UBX-16010572 - R10

TOBY-R2 series

Multi-mode LTE Cat 1 modules with 2G/3G fallback

System integration manual

TOBY-R2 series - System integration manual

Title

TOBY-R2 series

Subtitle

Multi-mode LTE Cat 1 modules with 2G/3G fallback

Document type

System integration manual

Document number

UBX-16010572

Revision and date

R10

30-Aug-2019

Disclosure restriction

Product status

Corresponding content status

Functional sample

Draft

For functional testing. Revised and supplementary data will be published later.

In development /
Prototype

Objective specification

Target values. Revised and supplementary data will be published later.

Engineering sample

Advance information

Data based on early testing. Revised and supplementary data will be published later.

Initial production

Early production information

Data from product verification. Revised and supplementary data may be published later.

Mass production /
End of life

Production information

Document contains the final product specification.

Product name

Type number

Modem version

Application version

PCN reference

Product status

TOBY-R200

TOBY-R200-02B-00

30.31

A01.01

UBX-17006265

End of life

TOBY-R200-02B-01

30.31

A02.00

UBX-17048314

End of life

TOBY-R200-02B-02

30.31

A02.01

UBX-18018067

End of life

TOBY-R200-02B-03

30.31

A02.02

UBX-18057549

End of life

TOBY-R200-02B-04

30.33

A02.02

UBX-19011731

Mass production

TOBY-R200-42B-00

30.53

A01.00

UBX-19039698

Engineering sample

TOBY-R200-82B-00

30.53

A01.00

UBX-19039698

Engineering sample

TOBY-R202

TOBY-R202-02B-00

30.31

A01.01

UBX-17006265

End of life

TOBY-R202-02B-01

30.31

A02.00

UBX-17048314

End of life

TOBY-R202-02B-02

30.31

A02.01

UBX-18018067

End of life

TOBY-R202-02B-03

30.31

A02.02

UBX-18057549

End of life

TOBY-R202-02B-04

30.33

A02.02

UBX-19011731

Mass production

TOBY-R202-02B-34

30.33

A02.03

UBX-19039777

Mass production

u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent
documents, visit www.u-blox.com.
Copyright © u-blox AG.

Document information

This document applies to the following products:

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Contents

Document information ................................................................................................................................ 2

Contents .......................................................................................................................................................... 3

1 System description ............................................................................................................................... 7

1.1 Overview ........................................................................................................................................................ 7

1.2 Architecture ................................................................................................................................................. 9

1.3 Pin-out ......................................................................................................................................................... 10

1.4 Operating modes ....................................................................................................................................... 14

1.5 Supply interfaces ...................................................................................................................................... 16

1.5.1 Module supply input (VCC) ............................................................................................................. 16

1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 24

1.5.3 Generic digital interfaces supply output (V_INT) ....................................................................... 25

1.6 System function interfaces .................................................................................................................... 26

1.6.1 Module power-on .............................................................................................................................. 26

1.6.2 Module power-off .............................................................................................................................. 28

1.6.3 Module reset ...................................................................................................................................... 31

1.6.4 Module / host configuration selection .......................................................................................... 31

1.7 Antenna interface ..................................................................................................................................... 32

1.7.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 32

1.7.2 Antenna detection interface (ANT_DET) ..................................................................................... 34

1.8 SIM interface .............................................................................................................................................. 34

1.8.1 SIM interface ..................................................................................................................................... 34

1.8.2 SIM detection interface ................................................................................................................... 34

1.9 Data communication interfaces ............................................................................................................ 35

1.9.1 UART interface .................................................................................................................................. 35

1.9.2 USB interface ..................................................................................................................................... 46

1.9.3 DDC (I2C) interface ............................................................................................................................ 49

1.9.4 SDIO interface ................................................................................................................................... 51

1.10 Audio ............................................................................................................................................................ 52

1.10.1 Digital audio over I2S interface ....................................................................................................... 52

1.11 Clock output ............................................................................................................................................... 53

1.12 General Purpose Input/Output ............................................................................................................... 53

1.13 Reserved pins (RSVD) .............................................................................................................................. 53

1.14 System features ........................................................................................................................................ 54

1.14.1 Network indication ........................................................................................................................... 54

1.14.2 Antenna supervisor .......................................................................................................................... 54

1.14.3 Jamming detection .......................................................................................................................... 54

1.14.4 Dual stack IPv4/IPv6 ......................................................................................................................... 54

1.14.5 TCP/IP and UDP/IP ............................................................................................................................ 55

1.14.6 FTP ....................................................................................................................................................... 55

1.14.7 HTTP .................................................................................................................................................... 55

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1.14.8 SSL / TLS ............................................................................................................................................ 55

1.14.9 Bearer Independent Protocol .......................................................................................................... 57

1.14.10 AssistNow clients and GNSS integration .................................................................................... 57

1.14.11 Hybrid positioning and CellLocate® ............................................................................................... 58

1.14.12 Wi-Fi integration ............................................................................................................................... 60

1.14.13 Firmware update Over AT (FOAT) ................................................................................................. 60

1.14.14 Firmware update Over The Air (FOTA) ......................................................................................... 60

1.14.15 Smart temperature management ................................................................................................ 61

1.14.16 Power saving ...................................................................................................................................... 63

2 Design-in ................................................................................................................................................ 64

2.1 Overview ...................................................................................................................................................... 64

2.2 Supply interfaces ...................................................................................................................................... 65

2.2.1 Module supply (VCC) ........................................................................................................................ 65

2.2.2 RTC supply output (V_BCKP) ......................................................................................................... 79

2.2.3 Generic digital interfaces supply output (V_INT) ....................................................................... 81

2.3 System functions interfaces .................................................................................................................. 82

2.3.1 Module power-on (PWR_ON) .......................................................................................................... 82

2.3.2 Module reset (RESET_N) ................................................................................................................. 83

2.3.3 Module / host configuration selection .......................................................................................... 84

2.4 Antenna interface ..................................................................................................................................... 85

2.4.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 85

2.4.2 Antenna detection interface (ANT_DET) ..................................................................................... 92

2.5 SIM interface .............................................................................................................................................. 94

2.5.1 Guidelines for SIM circuit design ................................................................................................... 94

2.5.2 Guidelines for SIM layout design ................................................................................................... 99

2.6 Data communication interfaces .......................................................................................................... 100

2.6.1 UART interface ................................................................................................................................ 100

2.6.2 USB interface ................................................................................................................................... 105

2.6.3 DDC (I2C) interface .......................................................................................................................... 107

2.6.4 SDIO interface ................................................................................................................................... 111

2.7 Audio interface ......................................................................................................................................... 112

2.7.1 Digital audio interface ..................................................................................................................... 112

2.8 General Purpose Input/Output .............................................................................................................. 116

2.9 Reserved pins (RSVD) ............................................................................................................................. 117

2.10 Module placement ................................................................................................................................... 117

2.11 Module footprint and paste mask ........................................................................................................ 118

2.12 Thermal guidelines .................................................................................................................................. 119

2.13 ESD guidelines ......................................................................................................................................... 120

2.13.1 ESD immunity test overview ........................................................................................................ 120

2.13.2 ESD immunity test of TOBY-R2 series reference designs ...................................................... 121

2.13.3 ESD application circuits ................................................................................................................. 121

2.14 Schematic for TOBY-R2 series module integration ......................................................................... 123

2.14.1 Schematic for TOBY-R2 series module “x2” product version ................................................ 123

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2.15 Design-in checklist .................................................................................................................................. 124

2.15.1 Schematic checklist ....................................................................................................................... 124

2.15.2 Layout checklist .............................................................................................................................. 125

2.15.3 Antenna checklist ........................................................................................................................... 125

3 Handling and soldering .................................................................................................................... 126

3.1 Packaging, shipping, storage and moisture preconditioning ........................................................ 126

3.2 Handling .................................................................................................................................................... 126

3.3 Soldering ................................................................................................................................................... 127

3.3.1 Soldering paste ............................................................................................................................... 127

3.3.2 Reflow soldering .............................................................................................................................. 127

3.3.3 Optical inspection ........................................................................................................................... 128

3.3.4 Cleaning ............................................................................................................................................ 128

3.3.5 Repeated reflow soldering ............................................................................................................ 129

3.3.6 Wave soldering ................................................................................................................................ 129

3.3.7 Hand soldering ................................................................................................................................ 129

3.3.8 Rework .............................................................................................................................................. 129

3.3.9 Conformal coating .......................................................................................................................... 129

3.3.10 Casting .............................................................................................................................................. 129

3.3.11 Grounding metal covers ................................................................................................................ 130

3.3.12 Use of ultrasonic processes ......................................................................................................... 130

4 Approvals .............................................................................................................................................. 131

4.1 Product certification approval overview .............................................................................................. 131

4.2 US Federal Communications Commission notice ............................................................................ 132

4.2.1 Safety warnings review the structure ........................................................................................ 132

4.2.2 Declaration of Conformity ............................................................................................................. 132

4.2.3 Modifications ................................................................................................................................... 133

4.3 Innovation, Science, Economic Development Canada notice ........................................................ 134

4.3.1 Declaration of Conformity ............................................................................................................. 134

4.3.2 Modifications ................................................................................................................................... 134

4.4 European Conformance CE mark ........................................................................................................ 136

5 Product testing .................................................................................................................................. 137

5.1 u-blox in-series production test ........................................................................................................... 137

5.2 Test parameters for OEM manufacturer ........................................................................................... 138

5.2.1 “Go/No go” tests for integrated devices .................................................................................... 138

5.2.2 RF functional tests ......................................................................................................................... 138

Appendix ..................................................................................................................................................... 140

A Migration between TOBY-L2 and TOBY-R2 ............................................................................ 140

A.1 Overview .................................................................................................................................................... 140

A.2 Pin-out comparison between TOBY-L2 and TOBY-R2 .................................................................... 142

A.3 Schematic for TOBY-L2 and TOBY-R2 integration .......................................................................... 145

B Glossary ................................................................................................................................................ 146

Related documents .................................................................................................................................. 149

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Revision history ......................................................................................................................................... 150

Contact ......................................................................................................................................................... 151

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Model

Region

Radio Access

Technology

Positioning

Interfaces

Audio

Features

Grade

LTE bands

1

UMTS bands GSM bands

GNSS via modem AssistNow Software CellLocate® UART USB 2.0

SDIO * DDC (I

2C)

GPIOs Analog audio Digital audio Network indication VoLTE Antenna supervisor Rx Diversity Jamming detection Embedded TCP/UDP stack Embedded HTTP, FTP, SSL FOTA

Dual stack IPv4 / IPv6 Standard Professional Automotive

TOBY-R200-02B

North

America

2,4

5,12

850,900

1900,2100

Quad

■ ■ ■

1 1 1 1 9

● ● ● ● ● □ ● ● ● ● ●

TOBY-R200-42B

Global

1,2,4

5,8,12

850,900

1900,2100

Quad

● ● ●

1 1 1 1 9

● ● ● □ ● ● ● ● ●

TOBY-R200-82B

Global

1,2,4

5,8,12

850,900

1900,2100

Quad

● ● ●

1 1 1 1 9

● ● ● □ ● ● ● ● ●

TOBY-R202-02B

North

America

2,4

5,12

850,1900

■ ■ ■

1 1 1 1 9

● ● ● ● ● □ ● ● ● ● ●

● = Supported by all FW version ■ = Supported by "TOBY-R2xx-02B-01" FW version onwards □ = Supported by future FW version * = HW ready

1

1 System description

1.1 Overview

The TOBY-R2 series comprises LTE Cat 1 / 3G / 2G multi-mode modules supporting up to six LTE
bands, up to four 3G UMTS/HSPA bands and up to four 2G GSM/(E)GPRS bands for voice and/or data
transmission in the small TOBY LGA form-factor (35.6 x 24.8 mm, 152-pin), easy to integrate in
compact designs:

 TOBY-R200 are designed for worldwide operation on LTE, 3G and 2G networks, and primarily in

North America

 TOBY-R202 are designed primarily for operation in North America, on LTE and 3G networks

TOBY-R2 series modules are form-factor compatible with u-blox SARA, LISA and LARA cellular
module families and are pin-to-pin compatible with u-blox TOBY-L cellular module families: this
facilitates easy migration from the u-blox GSM/GPRS, CDMA, UMTS/HSPA, and LTE high data rate
modules, maximizes the investments of customers, simplifies logistics, and enables very short
time-to-market.

The modules are ideal for applications that are transitioning to LTE from 2G and 3G, due to the long
term availability and scalability of LTE networks.

With a range of interface options and an integrated IP stack, the modules are designed to support a
wide range of data-centric applications. The unique combination of performance and flexibility make
these modules ideally suited for medium speed M2M applications, such as smart energy gateways,
remote access video cameras, digital signage, telehealth and telematics.

TOBY-R2 series modules include product versions supporting Voice over LTE (VoLTE) and voice over
3G / 2G (CSFB) for applications that require voice, such as security and surveillance systems.

Table 1 summarizes the main features and interfaces of TOBY-R2 series modules.

Table 1: TOBY-R2 series main features summary

LTE band 12 is a superset including band 17: LTE band 12 is supported along with Multi-Frequency Band Indicator feature

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4G LTE

3G UMTS/HSDPA/HSUPA

2G GSM/GPRS/EDGE

3GPP Release 9
Long Term Evolution (LTE)
Evolved UTRA (E-UTRA)
Frequency Division Duplex (FDD)
DL Rx Diversity

3GPP Release 9
High Speed Packet Access (HSPA)
UMTS Terrestrial Radio Access (UTRA)
Frequency Division Duplex (FDD)
DL Rx diversity

3GPP Release 9
Enhanced Data rate GSM Evolution (EDGE)
GSM EGPRS Radio Access (GERA)
Time Division Multiple Access (TDMA)
DL Advanced Rx Performance Phase 1

Band support2:
 TOBY-R200-02B:

o Band 12 (700 MHz)3
o Band 5 (850 MHz)
o Band 4 (1700 MHz)
o Band 2 (1900 MHz)

 TOBY-R200-42B, TOBY-R200-82B:

o Band 12 (700 MHz)

3

o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 4 (1700 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)

 TOBY-R202:

o Band 12 (700 MHz)3
o Band 5 (850 MHz)
o Band 4 (1700 MHz)

o Band 2 (1900 MHz)

Band support:
 TOBY-R200-02B:

o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)

 TOBY-R200-42B, TOBY-R200-82B:

o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)

 TOBY-R202:

o Band 5 (850 MHz)
o Band 2 (1900 MHz)

Band support:
 TOBY-R200-02B:

o GSM 850 MHz
o E-GSM 900 MHz
o DCS 1800 MHz
o PCS 1900 MHz

 TOBY-R200-42B, TOBY-R200-82B:

o GSM 850 MHz
o E-GSM 900 MHz
o DCS 1800 MHz
o PCS 1900 MHz

LTE Power Class
Class 3 (23 dBm)

UMTS/HSDPA/HSUPA Power Class
Class 3 (24 dBm)

GSM/GPRS (GMSK) Power Class

 Class 4 (33 dBm) for GSM/E-GSM band
 Class 1 (30 dBm) for DCS/PCS band

EDGE (8-PSK) Power Class

 Class E2 (27 dBm) for GSM/E-GSM band
 Class E2 (26 dBm) for DCS/PCS band

Data rate
LTE category 1:

up to 10.3 Mb/s DL, 5.2 Mb/s UL

Data Rate
 HSDPA category 8:

up to 7.2 Mb/s DL

 HSUPA category 6:

up to 5.76 Mb/s UL

Data Rate4
 GPRS multi-slot class 335, CS1-CS4,

up to 107 kb/s DL, up to 85.6 kb/s UL

 EDGE multi-slot class 335, MCS1-MCS9,

up to 296 kb/s DL, up to 236.8 kb/s UL

2

3

4

5

Table 2 summarizes cellular radio access technology characteristics and features of the modules.

Table 2: TOBY-R2 series LTE, 3G and 2G characteristics summary

TOBY-R2 series modules, except for the "42" / "82" product versions, provide Voice over LTE (VoLTE)
as well as Circuit-Switched-Fall-Back (CSFB) audio capability.

TOBY-R2 modules support all the E-UTRA channel bandwidths for each operating band according to 3GPP TS 36.521-1 [20]:

 Band 12: 1.4 MHz, 3 MHz, 5 MHz, 10 MHz
 Band 5: 1.4 MHz, 3 MHz, 5 MHz, 10 MHz
 Band 4: 1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, 20 MHz
 Band 2: 1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, 20 MHz

LTE band 12 is a superset that includes band 17
GPRS/EDGE multi-slot class determines the number of timeslots available for upload and download and thus the speed at

which data can be transmitted and received, with higher classes typically allowing faster data transfer rates.

GPRS/EDGE multi-slot class 33 implies a maximum of 5 slots in DL (Rx) and 4 slots in UL (Tx) with 6 slots in total.

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Cellular

Base-band

Processor

Memory

Power Management Unit

26 MHz

32.768 kHz

ANT1

RF

Transceiver

ANT2

V_INT (I/O)

V_BCKP (RTC)

VCC (Supply)

SIM

USB

GPIO

Power On

External Reset

PAs

LNAsFilters

Filter

s

Duplexer

Filters

PAs

LNAsFilter

s

Filter

s

Duplexer

Filters

LNAsFilter

s

Filters

LNAsFiltersFilter

s

Switch

Switch

DDC(I2C)

SDIO

UART

Digital audio (I2S)

ANT_DET

Host Select

1.2 Architecture

Figure 1 summarizes the internal architecture of TOBY-R2 series modules.

Figure 1: TOBY-R2 series modules simplified block diagram

TOBY-R2 series modules internally consists of the RF, Baseband and Power Management sections
here described with more details than the simplified block diagrams of Figure 1.

RF section

The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF
switches.

Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port
(ANT1) of the module via power amplifier (PA), SAW band pass filters band, specific duplexer and
antenna switch.

Dual receiving paths are implemented according to LTE Receiver Diversity radio technology supported
by the modules as LTE category 1 User Equipment: incoming signal is received through the primary
(ANT1) and the secondary (ANT2) antenna input ports which are connected to the RF transceiver via
specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.

 RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx,

down-conversion and demodulation of the dual RF signals for Rx. The RF transceiver contains:

o Single chain high linearity receivers with integrated LNAs for multi band multi-mode operation,
o Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM,
o RF synthesizer,
o VCO.

 Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
 RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx

path

 SAW duplexers and band pass filters separate the Tx and Rx signal paths and provide RF filtering
 26 MHz voltage-controlled temperature-controlled crystal oscillator generates the clock reference

in active-mode or connected-mode.

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Function

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

70,71,72

I

Module supply input

VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.

See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.

GND

2, 30, 32,
44, 46, 69,
73, 74, 76,
78, 79, 80,
82, 83, 85,
86, 88-90,
92-152

N/A

Ground

GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.

V_BCKP

3

I/O

RTC supply
input/output

V_BCKP = 1.8 V (typical) generated by internal regulator
when valid VCC supply is present.
See section 1.5.2 for functional description.

See section 2.2.2 for external circuit design-in.

V_INT

5 O Generic digital
interfaces supply
output

V_INT = 1.8 V (typical) generated by internal DC/DC
regulator when the module is switched on.

Test-Point for diagnostic access is recommended.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.

System

PWR_ON

20 I Power-on input

Internal 10 k pull-up resistor to V_BCKP.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.

RESET_N

23 I External reset input

Internal 10 k pull-up resistor to V_BCKP.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.

HOST_SELECT0

26

I/O

Selection of module/
host configuration

Not supported.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.

Baseband and power management section

The Baseband and Power Management section is composed of the following main elements:
 A mixed signal ASIC, which integrates

o Microprocessor for control functions
o DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths
o Memory interface controller
o Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces
o Interfaces to RF transceiver ASIC

 Memory system, which includes NAND flash and LPDDR2 RAM
 Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
 Voltage sources for external use: V_BCKP and V_INT
 Hardware power on
 Hardware reset
 Low power idle-mode support
 32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can

be set by enable power saving configuration using the AT+UPSV command.

1.3 Pin-out

Table 3 lists the pin-out of the TOBY-R2 series modules, with pins grouped by function.

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Function

Pin Name

Pin No

I/O

Description

Remarks

HOST_SELECT1

62

I/O

Selection of module/
host configuration

Not supported.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.

Antennas

ANT1

81

I/O

Primary antenna

Main Tx / Rx antenna interface.
50  nominal characteristic impedance.
Antenna circuit affects RF performance and end-device

compliance with required certification schemes.
See section 1.7 for functional description / requirements.
See section 2.4 for external circuit design-in.

ANT2

87 I Secondary antenna

Rx only for Rx diversity.
50  nominal characteristic impedance.
Antenna circuit affects RF performance and end-device

compliance with required certification schemes.
See section 1.7 for functional description / requirements
See section 2.4 for external circuit design-in.

ANT_DET

75 I Antenna detection

ADC for antenna presence detection function
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.

SIM

VSIM

59 O SIM supply output

VSIM = 1.8 V / 3 V output as per connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.

SIM_IO

57

I/O

SIM data

Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_CLK

56 O SIM clock

3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.

SIM_RST

58 O SIM reset

Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.

UART

RXD

17 O UART data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW
update by u-blox EasyFlash tool and diagnostic.

Test-Point and series 0  for diagnostic recommended.
See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

TXD

16 I UART data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW
update by u-blox EasyFlash tool and diagnostic.

Internal active pull-up to V_INT.
Test-Point and series 0  for diagnostic recommended.
See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

CTS

15 O UART clear to send
output

1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.

RTS

14 I UART ready to send
input

1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.

DSR

10

O

UART data set ready
output

1.8 V, Circuit 107 in ITU-T V.24.
See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

RI

11

O

UART ring indicator
output

1.8 V, Circuit 125 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.

DTR

13

I

UART data terminal
ready input

1.8 V, Circuit 108/2 in ITU-T V.24.
Internal active pull-up to V_INT.
Test-Point and series 0  for diagnostic recommended.
See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DCD

12

O

UART data carrier
detect output

1.8 V, Circuit 109 in ITU-T V.24.
Test-Point and series 0  for diagnostic recommended.
See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

USB

VUSB_DET

4 I USB detect input

VBUS (5 V typical) USB supply generated by the host must
be connected to this input pin to enable the USB interface.

If the USB interface is not used by the Host Processor,
Test-Point for diagnostic / FW update is recommended
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.

USB_D-

27

I/O

USB Data Line D-

USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0)
30  nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors
as required by the USB 2.0 specifications [6] are part of
the USB pin driver and need not be provided externally.
If the USB interface is not used by the Host Processor,
Test-Point for diagnostic / FW update is recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.

USB_D+

28

I/O

USB Data Line D+

USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0)
30  nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors
as required by the USB 2.0 specifications [6] are part of
the USB pin driver and need not be provided externally.
If the USB interface is not used by the Host Processor,
Test-Point for diagnostic / FW update is recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.

DDC

SCL

54 O I2C bus clock line

1.8 V open drain, for communication with I2C-slave devices
No internal pull-up.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.

SDA

55

I/O

I2C bus data line

1.8 V open drain, for communication with I2C-slave devices
No internal pull-up.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.

SDIO

SDIO_D0

66

I/O

SDIO serial data [0]

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

SDIO_D1

68

I/O

SDIO serial data [1]

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

SDIO_D2

63

I/O

SDIO serial data [2]

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

SDIO_D3

67

I/O

SDIO serial data [3]

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

SDIO_CLK

64 O SDIO serial clock

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_CMD

65

I/O

SDIO command

Not supported by “02” / "42" / "82" product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

Audio

I2S_TXD

51

O /
I/O

I2S transmit data /
GPIO

I2S transmit data output, alternatively settable as GPIO.
I2S interface not supported by "42" / "82" product versions.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.

I2S_RXD

53

I /
I/O

I2S receive data /
GPIO

I2S receive data input, alternatively configurable as GPIO.
I2S interface not supported by "42" / "82" product versions.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.

I2S_CLK

52

I/O /
I/O

I2S clock /
GPIO

I2S serial clock, alternatively configurable as GPIO.
I2S interface not supported by "42" / "82" product versions.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.

I2S_WA

50

I/O /
I/O

I2S word alignment /
GPIO

I2S word alignment, alternatively configurable as GPIO.
I2S interface not supported by "42" / "82" product versions.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.

Clock
output

GPIO6

61 O Clock output

1.8 V configurable clock output.
See section 1.11 for functional description.
See section 2.7 for external circuit design-in.

GPIO

GPIO1

21

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.

GPIO2

22

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.

GPIO3

24

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.

GPIO4

25

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.

GPIO5

60

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.

Reserved

RSVD

6

N/A

Reserved pin

This pin must be connected to ground.
See sections 1.13 and 2.9

RSVD

18, 19

N/A

Reserved pin

Test-Point for diagnostic access is recommended.
See sections 1.13 and 2.9

RSVD

1, 7-9, 29,
31, 33-43,
45, 47-49,
77, 84, 91

N/A

Reserved pin

Leave unconnected.
See sections 1.13 and 2.9

Table 3: TOBY-R2 series module pin definition, grouped by function

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General Status

Operating Mode

Definition

Power-down

Not-powered Mode

VCC supply not present or below operating range: module is switched off.

Power-off Mode

VCC supply within operating range and module is switched off.

Normal operation

Idle mode

Module processor core runs with 32 kHz reference generated by the internal oscillator.

Active mode

Module processor core runs with 26 MHz reference generated by the internal oscillator.

Connected mode

RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.

Mode

Description

Transition between operating modes

Not-Powered

Module is switched off.
Application interfaces are not
accessible.

When VCC supply is removed, the modules enter not-powered mode.
When in not-powered mode, the modules cannot be switched on by
PWR_ON, RESET_N or RTC alarm
When in not-powered mode, the modules can be switched on by
applying VCC supply (see 1.6.1) so that the modules switch from
not-powered to active-mode

Power-Off

Module is switched off: normal
shutdown by an appropriate power-off
event (see 1.6.2).
Application interfaces are not
accessible.

When the modules are switched off by an appropriate switch-off
event (see 1.6.2), the modules enter power-off mode from
active-mode.
When in power-off mode, the modules can be switched on by
PWR_ON, RESET_N or an RTC alarm.
When in power-off mode, the modules enter not-powered mode by
removing VCC supply.

Idle

Module is switched on with application
interfaces temporarily disabled or
suspended: the module is temporarily
not ready to communicate with an
external device by means of the
application interfaces as configured to
reduce the current consumption.
The module enters the low power idle­mode whenever possible if power saving
is enabled by AT+UPSV (see u-blox AT
commands manual [2]) reducing current
consumption (see 1.5.1.5).
The CTS output line indicates when the
UART interface is disabled/enabled due
to the module idle/active-mode
according to power saving and HW flow
control settings (see 1.9.1.3, 1.9.1.4).

Power saving configuration is not
enabled by default: it can be enabled by
AT+UPSV (see the u-blox AT commands
manual [2]).

The modules automatically switch from the active-mode to low power
idle-mode whenever possible if power saving is enabled (see sections

1.5.1.5, 1.9.1.4, 1.9.2.4 and u-blox AT commands manual [2], AT+UPSV

command).
The modules wake up from low power idle-mode to active-mode in the

following events:
 Automatic periodic monitoring of the paging channel for the

paging block reception according to network conditions (see

1.5.1.5, 1.9.1.4)

 Automatic periodic enable of the UART interface to receive / send

data, with AT+UPSV=1 (see 1.9.1.4)

 Data received over UART, according to HW flow control (AT&K)

and power saving (AT+UPSV) settings (see 1.9.1.4)

 RTS input set ON by the host DTE, with HW flow control disabled

and AT+UPSV=2 (see 1.9.1.4)

 DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4)
 USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2)
 The connected USB host forces a remote wakeup of the module as

USB device (see 1.9.2.4)

 The connected u-blox GNSS device forces a wakeup of the module

using the GNSS Tx data ready function over GPIO3 (see 1.9.3)

 The connected SDIO device forces a wakeup of the module as

SDIO host (see 1.9.4)

 A preset RTC alarm occurs (see u-blox AT commands manual [2],

AT+CALA)

1.4 Operating modes

TOBY-R2 series modules have several operating modes. The operating modes are defined in Table 4
and described in detail in Table 5, providing general guidelines for operation.

Table 4: TOBY-R2 series modules operating modes definition

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Mode

Description

Transition between operating modes

Active

Module is switched on with application
interfaces enabled or not suspended:
the module is ready to communicate
with an external device by means of the
application interfaces unless power
saving configuration is enabled by
AT+UPSV (see 1.9.1.4, 1.9.2.4 and u-blox
AT commands manual [2]).

When the modules are switched on by an appropriate power-on event
(see 1.6.1), the module enter active-mode from not-powered or
power-off mode.
If power saving configuration is enabled by the AT+UPSV command,
the module automatically switches from active to idle-mode
whenever possible and the module wakes up from idle to active-mode
in the events listed above (see idle-mode to active-mode transition
description above).

When a RF Tx/Rx data or voice connection is initiated or when RF
Tx/Rx is required due to a connection previously initiated, the module
switches from active to connected-mode.

Connected

RF Tx/Rx data connection is in progress.
The module is prepared to accept data
signals from an external device unless

power saving configuration is enabled by
AT+UPSV (see sections 1.9.1.4, 1.9.2.4
and u-blox AT commands manual [2]).

When a data or voice connection is initiated, the module enters
connected-mode from active-mode.

Connected-mode is suspended if Tx/Rx data is not in progress, due to
connected discontinuous reception and fast dormancy capabilities of
the module and according to network environment settings and
scenario. In such case, the module automatically switches from
connected to active mode and then, if power saving configuration is
enabled by the AT+UPSV command, the module automatically
switches to idle-mode whenever possible. Vice-versa, the module
wakes up from idle to active mode and then connected mode if RF
Tx/Rx is necessary.

When a data connection is terminated, the module returns to the
active-mode.

Switch ON:

• Apply VCC

If power saving is enabled
and there is no activity for
a defined time interval

Any wake up event described
in the module operating

modes summary table above

Incoming/outgoing call

or other dedicated device

network communication

No RF Tx/Rx in progress, Call

terminated, Communication

dropped

Remove VCC

Switch ON:

• PWR_ON

• RTC alarm

• RESET_N

Not

powered

Power off

ActiveConnected Idle

Switch OFF:

• AT+CPWROFF

• PWR_ON

Table 5: TOBY-R2 series modules operating modes description

Figure 2 describes the transition between the different operating modes.

Figure 2: TOBY-R2 series modules operating modes transitions

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72

VCC

71

VCC

70

VCC

TOBY-R202

Power

Management

Unit

Memory

Baseband

Processor

Transceiver

RF PMU

LTE/3G PAs

72

VCC

71

VCC

70

VCC

TOBY-R200

Power

Management

Unit

Memory

Baseband

Processor

Transceiver

RF PMU

LTE/3G/2G PAs

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input.

The VCC pins are internally connected to the RF power amplifier and to the integrated Power
Management Unit: all supply voltages needed by the module are generated from the VCC supply by
integrated voltage regulators, including V_BCKP Real Time Clock supply, V_INT digital interfaces
supply and VSIM SIM card supply.

During operation, the current drawn by the TOBY-R2 series modules through the VCC pins can vary
by several orders of magnitude. This ranges from the pulse of current consumption during GSM
transmitting bursts at maximum power level in connected-mode (as described in section 1.5.1.2) to
the low current consumption during low power idle-mode with power saving enabled (as described in
section 1.5.1.5).

TOBY-R200 modules provide separate supply inputs over the three VCC pins:
 VCC pins #71 and #72 represent the supply input for the internal RF power amplifier, demanding

most of the total current drawn of the module when RF transmission is enabled during a
voice/data call

 VCC pin #70 represents the supply input for the internal baseband Power Management Unit and

the internal transceiver, demanding minor part of the total current drawn of the module when RF
transmission is enabled during a voice/data call

Figure 3 provides a simplified block diagram of TOBY-R2 series modules internal VCC supply routing.

Figure 3: TOBY-R2 series modules internal VCC supply routing simplified block diagram

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Item

Requirement

Remark

VCC nominal voltage

Within VCC normal operating range:

3.30 V min. / 4.40 V max

RF performance is guaranteed when VCC PA voltage is
inside the normal operating range limits.

RF performance may be affected when VCC PA voltage is
outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is
inside the extended operating range limits.

VCC voltage during
normal operation

Within VCC extended operating range:

3.00 V min. / 4.50 V max

VCC voltage must be above the extended operating range
minimum limit to switch-on the module.
The module may switch-off when the VCC voltage drops
below the extended operating range minimum limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.

VCC average current

Support with adequate margin the highest
averaged VCC current consumption value
in connected-mode conditions specified in
TOBY-R2 data sheet [1].

The maximum average current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Sections 1.5.1.2, 1.5.1.3 and 1.5.1.4 describe current
consumption profiles in 2G, 3G and LTE connected-mode.

VCC peak current

Support with margin the highest peak
VCC current consumption value in
connected-mode conditions specified in
TOBY-R2 data sheet [1]

The specified maximum peak of current consumption
occurs during GSM single transmit slot in 850/900 MHz
connected-mode, in case of mismatched antenna.

Section 1.5.1.2 describes 2G Tx peak/pulse current.

VCC voltage drop
during 2G Tx slots

Lower than 400 mV

Supply voltage drop values greater than recommended
during 2G TDMA transmission slots directly affect the RF
compliance with applicable certification schemes.

Figure 5 describes supply voltage drop during 2G Tx slots.

VCC voltage ripple
during 2G/3G/LTE Tx

Noise in the supply has to be minimized

High supply voltage ripple values during LTE/3G/2G RF
transmissions in connected-mode directly affect the RF
compliance with applicable certification schemes.

Figure 5 describes supply voltage ripple during RF Tx.

VCC under/over-shoot
at start/end of Tx slots

Absent or at least minimized

Supply voltage under-shoot or over-shoot at the start or
the end of 2G TDMA transmission slots directly affect the
RF compliance with applicable certification schemes.

Figure 5 describes supply voltage under/over-shoot

1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions

to properly design a VCC supply circuit compliant with the requirements listed in Table 6.

⚠ The VCC supply circuit affects the RF compliance of the device integrating TOBY-R2 series

modules with applicable required certification schemes as well as antenna circuit design.
Compliance is met by fulfilling the requirements for the VCC supply summarized in Table 6.

Table 6: Summary of VCC modules supply requirements

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Time [ms]

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200 mA

60-120 mA

1900 mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

60-120 mA

10-40 mA

0.0

1.5

1.0

0.5

2.0

Time [ms]

undershoot

overshoot

ripple

drop

Voltage [mV]

3.8 V

(typ)

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5.1.2 VCC current consumption in 2G connected-mode

When a GSM call is established, the VCC module current consumption is determined by the current
consumption profile typical of the GSM transmitting and receiving bursts.

The peak of current consumption during a transmission slot is strictly dependent on the RF
transmitted power, which is regulated by the network (the current base station). The transmitted
power in the transmit slot is also the more relevant factor for determining the average current
consumption.

If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands, at the maximum
RF power level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current
consumption can reach an high peak (see the “Current consumption” section in the TOBY-R2 series
data sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of
1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple
Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current
consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output
power specifications.

During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts
and is low in the inactive unused bursts.

Figure 4 shows an example of the module current consumption profile versus time in 2G single-slot

mode.

Figure 4: VCC current consumption profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)

Figure 5 illustrates VCC voltage profile versus time during a 2G single-slot call, according to the

relative VCC current consumption profile described in Figure 4.

Figure 5: VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)

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Time [ms]

RX

slot

unused

slot

TX
slot

TX

slot

TX

slot

TX

slot

MON

slot

unused

slot

RX

slot

unused

slot

TX

slot

TX

slot

TX

slot

TX

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200mA

60-130mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

1600 mA

0.0

1.5

1.0

0.5

2.0

When a GPRS connection is established, more than one slot can be used to transmit and/or more than
one slot can be used to receive. The transmitted power depends on network conditions, which set the
peak current consumption, but following the 3GPP specifications the maximum Tx RF power is
reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as
can be in case of a 2G single-slot call.

The multi-slot transmission power can be further reduced by configuring the actual Multi-Slot Power
Reduction profile with the dedicated AT command, AT+UDCONF=40 (see the u-blox AT commands
manual [2]).

If the module transmits in GPRS class 12 in the 850 or 900 MHz bands, at the maximum RF power
control level, the current consumption can reach a quite high peak but lower than the one achievable
in 2G single-slot mode. This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a
periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to 2G
TDMA.

If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, the current consumption
figures are quite less high than the one in the low bands, due to 3GPP transmitter output power
specifications.

Figure 6 reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or 900

MHz bands, with 4 slots used to transmit and 1 slot used to receive.

Figure 6: VCC current consumption profile during a 2G GPRS/EDGE multi-slot connection (4 TX slots, 1 RX slot)

In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current
profile, so the image shown in Figure 6, representing the current consumption profile in GPRS class
12 connected mode, is valid for the EDGE class 12 connected mode as well.

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Time

[ms]

3G frame

10 ms

(1 frame = 15 slots)

Current [mA]

Current consumption value

depends on TX power and

actual antenna load

170

mA

1 slot

666 µs

850
mA

0

300

200

100

500

400

600

700

1.5.1.3 VCC current consumption in 3G connected mode

During a 3G connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA).

The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a
maximum rate of 1.5 kHz.

There are no high current peaks as in the 2G connection, since transmission and reception are
continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA
implemented in the 2G case.

In the worst scenario, corresponding to a continuous transmission and reception at maximum output
power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins
is considerable (see the “Current consumption” section in TOBY-R2 series data sheet [1]). At the
lowest output RF power (approximately 0.01 µW or –50 dBm), the current drawn by the internal power
amplifier is strongly reduced. The total current drawn by the module at the VCC pins is due to
baseband processing and transceiver activity.

Figure 7 shows an example of current consumption profile of the module in 3G WCDMA/ HSPA

continuous transmission mode.

Figure 7: VCC current consumption profile versus time during a 3G connection (TX and RX continuously enabled)

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Time

[ms]

Current [mA]

Current consumption value

depends on TX power and

actual antenna load

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Frame

(10 ms)

0

300

200

100

500

400

600

700

1.5.1.4 VCC current consumption in LTE connected-mode

During an LTE connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation used in LTE radio access technology.

The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate
of power change can reach a maximum rate of 2 kHz.

The current consumption profile is similar to that in 3G radio access technology. Unlike the 2G
connection mode, which uses the TDMA mode of operation, there are no high current peaks since
transmission and reception are continuously enabled in FDD.

In the worst scenario, corresponding to a continuous transmission and reception at maximum output
power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins
is considerable (see the “Current consumption” section in TOBY-R2 series data sheet [1]). At the
lowest output RF power (approximately 0.1 µW or –40 dBm), the current drawn by the internal power
amplifier is strongly reduced and the total current drawn by the module at the VCC pins is due to
baseband processing and transceiver activity.

Figure 8 shows an example of the module current consumption profile versus time in LTE

connected-mode. Detailed current consumption values can be found in TOBY-R2 series data sheet [1].

Figure 8: VCC current consumption profile versus time during LTE connection (TX and RX continuously enabled)

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~50 ms

IDLE MODE ACTIVE MODE IDLE MODE

Active Mode

Enabled

Idle Mode

Enabled

2G case: 0.44-2.09 s
3G case: 0.61-5.09 s

LTE case: 0.27-2.51 s

IDLE MODE

~50 ms

ACTIVE MODE

Time [s]

Current [mA]

Time [ms]

Current [mA]

RX

Enabled

0

100

0

100

1.5.1.5 VCC current consumption in cyclic idle/active mode (power saving enabled)

The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV
command (see the u-blox AT commands manual [2]). When power saving is enabled, the module
automatically enters the low power idle-mode whenever possible, reducing current consumption.

During low power idle-mode, the module processor runs with 32 kHz reference clock frequency.

When the power saving configuration is enabled and the module is registered or attached to a
network, the module automatically enters the low power idle-mode whenever possible, but it must
periodically monitor the paging channel of the current base station (paging block reception), in
accordance to the 2G/3G/LTE system requirements, even if connected-mode is not enabled by the
application. When the module monitors the paging channel, it wakes up to the active-mode, to enable
the reception of paging block. In between, the module switches to low power idle-mode. This is known
as discontinuous reception (DRX).

The module processor core is activated during the paging block reception, and automatically switches
its reference clock frequency from 32 kHz to the 26 MHz used in active-mode.

The time period between two paging block receptions is defined by the network. This is the paging
period parameter, fixed by the base station through broadcast channel sent to all users on the same
serving cell:

 For 2G RAT, the paging period can vary from 470.8 ms (DRX = 2, length of 2 x 51 2G frames = 2 x 51

x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms)

 For 3G RAT, the paging period can vary from 640 ms (DRX = 6, i.e. length of 2

6

3G frames = 64 x

10 ms) up to 5120 ms (DRX = 9, length of 29 3G frames = 512 x 10 ms).

 For LTE RAT, the paging period can vary from 320 ms (DRX = 5, i.e. length of 2

5

LTE frames = 32 x

10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms).

Figure 9 illustrates a typical example of the module current consumption profile when power saving is

enabled. The module is registered with network, automatically enters the low power idle-mode and
periodically wakes up to active-mode to monitor the paging channel for the paging block reception.
Detailed current consumption values can be found in TOBY-R2 series data sheet [1].

Figure 9: VCC current consumption profile with power saving enabled and module registered with the network: the module
is in low-power idle-mode and periodically wakes up to active-mode to monitor the paging channel for paging block reception

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ACTIVE MODE

2G case: 0.44-2.09 s

3G case: 0.61-5.09 s

LTE case: 0.32-2.56 s

Paging period

Time [s]

Current [mA]

Time [ms]

Current [mA]

RX

Enabled

0

100

0

100

1.5.1.6 VCC current consumption in fixed active-mode (power saving disabled)

When power saving is disabled, the module does not automatically enter the low power idle-mode
whenever possible: the module remains in active-mode. Power saving configuration is by default
disabled. It can also be disabled using the AT+UPSV command (see u-blox AT commands manual [2]
for detail usage).

The module processor core is activated during idle-mode, and the 26 MHz reference clock frequency
is used. It would draw more current during the paging period than that in the power saving mode.

Figure 10 illustrates a typical example of the module current consumption profile when power saving

is disabled. In such case, the module is registered with the network and while active-mode is
maintained, the receiver is periodically activated to monitor the paging channel for paging block
reception. Detailed current consumption values can be found in TOBY-R2 series data sheet [1].

Figure 10: VCC current consumption profile with power saving disabled and module registered with the network: active-mode
is always held and the receiver is periodically activated to monitor the paging channel for paging block reception

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Baseband
Processor

70

VCC

71

VCC

72

VCC

3

V_BCKP

Linear

LDO

Power

Management

TOBY-R2 series

32 kHz

RTC

1.5.2 RTC supply input/output (V_BCKP)

The V_BCKP pin of TOBY-R2 series modules connects the supply for the Real Time Clock (RTC). A
linear LDO regulator integrated in the Power Management Unit internally generates this supply, as
shown in Figure 11, with low current capability (see the TOBY-R2 series data sheet [1]). The output of
this regulator is always enabled when the main module voltage supply applied to the VCC pins is within
the valid operating range.

Figure 11: TOBY-R2 series RTC supply (V_BCKP) simplified block diagram

The RTC provides the module time reference (date and time) that is used to set the wake-up interval
during the low power idle-mode periods, and is able to make available the programmable alarm
functions.

The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid
range (specified in the “Input characteristics of Supply/Power pins” table in TOBY-R2 series data
sheet [1]). The RTC can be supplied from an external back-up battery through the V_BCKP, when the
main module voltage supply is not applied to the VCC pins. This lets the time reference (date and time)
run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to
the module.

Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC
is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).

The RTC has very low current consumption, but is highly temperature dependent. For example,
V_BCKP current consumption at the maximum operating temperature can be higher than the typical
value at 25 °C specified in the “Input characteristics of Supply/Power pins” table in the TOBY-R2 series
data sheet [1].

If V_BCKP is left unconnected and the module main supply is not applied to the VCC pins, the RTC is
supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to
provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid
range. This has no impact on cellular connectivity, as all the module functionalities do not rely on date
and time setting.

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Baseband
Processor

70

VCC

71

VCC

72

VCC

5

V_INT

Switching

Step-Down

Power

Management

TOBY-R2 series

Digital I/O

1.5.3 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the TOBY-R2 series modules is connected to an internal 1.8 V supply with
current capability specified in the TOBY-R2 series data sheet [1]. This supply is internally generated
by a switching step-down regulator integrated in the Power Management Unit and it is internally used
to source the generic digital I/O interfaces of the cellular module, as described in Figure 12. The output
of this regulator is enabled when the module is switched on and it is disabled when the module is
switched off.

Figure 12: TOBY-R2 series generic digital interfaces supply output (V_INT) simplified block diagram

The switching regulator operates in Pulse Width Modulation (PWM) mode for greater efficiency at
high output loads and it automatically switches to Pulse Frequency Modulation (PFM) power save
mode for greater efficiency at low output loads. The V_INT output voltage ripple is specified in the
TOBY-R2 series data sheet [1].

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Baseband
processor

20

PWR_ON

TOBY-R2 series

3

V_BCKP

Power-on

Power

management

Power-on

10k

1.6 System function interfaces

1.6.1 Module power-on

When the TOBY-R2 series modules are in the not-powered mode (switched off, i.e. the VCC module
supply is not applied), they can be switched on as following:

 Rising edge on the VCC input to a valid voltage for module supply, i.e. applying module supply: the

modules switch on if the VCC supply is applied, starting from a voltage value of less than 2.1 V,
with a rise time from 2.3 V to 2.8 V of less than 4 ms, reaching a proper nominal voltage value
within VCC operating range.

Alternately, in case for example the fast rise time on VCC rising edge cannot be guaranteed by the
application, TOBY-R2 series modules can be switched on from not-powered mode as following:

 RESET_N input pin is held low by the external application during the VCC rising edge, so that the

modules will switch on when the external application releases the RESET_N input pin from the low
logic level after that the VCC supply voltage stabilizes at its proper nominal value within the
operating range

 PWR_ON input pin is held low by the external application during the VCC rising edge, so that the

modules will switch on when the external application releases the PWR_ON input pin from the low
logic level after that the VCC supply voltage stabilizes at its proper nominal value within the
operating range

When the TOBY-R2 series modules are in the power-off mode (i.e. switched off with valid VCC module
supply applied), they can be switched on as following:

 Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time

period: the modules start the internal switch-on sequence when the external application releases
the PWR_ON pin from the low logic level after that it has been set low for an appropriate time
period

 Rising edge on the RESET_N pin, i.e. releasing the pin from the low level, as that the pin is normally

set high by an internal pull-up: the modules start the internal switch-on sequence when the
external application releases the RESET_N pin from the low logic level

 RTC alarm, i.e. pre-programmed alarm by AT+CALA command (see u-blox AT commands

manual [2]).

As described in Figure 13, the TOBY-R2 series PWR_ON input is equipped with an internal active
pull-up resistor to the V_BCKP supply: the PWR_ON input voltage thresholds are different from the
other generic digital interfaces. Detailed electrical characteristics are described in TOBY-R2 series
data sheet [1].

Figure 13: TOBY-R2 series PWR_ON input description

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VCC

V_BCKP

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State

Internal Reset → Operational

Operational

Tristate / Floating

Internal Reset

OFF

ON

Start of interface

configuration

Module interfaces

are configured

Start-up

event

Figure 14 shows the module switch-on sequence from the not-powered mode, describing the following

phases:

 The external supply is applied to the VCC module supply inputs, representing the start-up event.
 The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage

value.

 The PWR_ON and the RESET_N pins suddenly rise to high logic level due to internal pull-ups.
 All the generic digital pins of the module are tri-stated until the switch-on of their supply source

(V_INT).

 The internal reset signal is held low: the baseband core and all the digital pins are held in the reset

state. The reset state of all the digital pins is reported in the pin description table of TOBY-R2
series data sheet [1].

 When the internal reset signal is released, any digital pin is set in a proper sequence from the reset

state to the default operational configured state. The duration of this pins’ configuration phase
differs within generic digital interfaces and the USB interface due to host / device enumeration
timings (see section 1.9.2).

 The module is fully ready to operate after all interfaces are configured.

☞ The Internal Reset signal is not available on a module pin, but the host application can monitor the
☞ Before the switch-on of the generic digital interface supply source (V_INT) of the module, no

☞ Before the TOBY-R2 series module is fully ready to operate, the host application processor should
☞ The duration of the TOBY-R2 series modules’ switch-on routine can vary depending on the

Figure 14: TOBY-R2 series switch-on sequence description

The greeting text can be activated by means of +CSGT AT command (see u-blox AT commands
manual [2]) to notify the external application that the module is ready to operate (i.e. ready to reply to
AT commands) and the first AT command can be sent to the module, given that autobauding has to
be disabled on the UART to let the module sending the greeting text: the UART has to be configured
at fixed baud rate (the baud rate of the application processor) instead of the default autobauding,
otherwise the module does not know the baud rate to be used for sending the greeting text (or any
other URC) at the end of the internal boot sequence.

V_INT pin to sense the start of the TOBY-R2 series module switch-on sequence.

voltage driven by an external application should be applied to any generic digital interface of the
module.

not send any AT command over the AT communication interfaces (USB, UART) of the module.

application / network settings and the concurrent module activities.

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1.6.2 Module power-off

TOBY-R2 series can be properly switched off by:
 AT+CPWROFF command (see u-blox AT commands manual [2]). The current parameter settings

are saved in the module’s non-volatile memory and a proper network detach is performed.

 Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time

period (see TOBY-R2 series data sheet [1]): the modules start the internal switch-off sequence
when the external application releases the PWR_ON line from the low logic level, after that it has
been set low for a proper time period.

An abrupt under-voltage shutdown occurs on TOBY-R2 series modules when the VCC module supply
is removed. If this occurs, it is not possible to perform the storing of the current parameter settings
in the module’s non-volatile memory or to perform the proper network detach.

☞ It is highly recommended to avoid an abrupt removal of the VCC supply during TOBY-R2 series

modules normal operations: the switch off procedure must be started by the AT+CPWROFF
command, waiting the command response for a proper time period (see u-blox AT commands
manual [2]), and then a proper VCC supply has to be held at least until the end of the modules’
internal switch off sequence, which occurs when the generic digital interfaces supply output
(V_INT) is switched off by the module.

An abrupt hardware shutdown occurs on TOBY-R2 series modules when a low level is applied on
RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile
memory and a proper network detach is not performed.

☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low

level on the RESET_N input pin during module normal operation: the RESET_N line should be set
low only if reset or shutdown via AT commands fails or if the module does not reply to a specific
AT command after a time period longer than the one defined in the u-blox AT commands
manual [2].

An over-temperature or an under-temperature shutdown occurs on TOBY-R2 series modules when
the temperature measured within the cellular module reaches the dangerous area, if the optional
Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For
more details see section 1.14.15 and u-blox AT commands manual [2], +USTS AT command.

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VCC

V_BCKP

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State Operational

OFF

Tristate / Floating

ON

Operational →

Tristate

AT+CPWROFF

sent to the module

OK

replied by the module

VCC

can be removed

Figure 15 describes the TOBY-R2 series modules switch-off sequence started by means of the

AT+CPWROFF command, allowing storage of current parameter settings in the module’s non-volatile
memory and a proper network detach, with the following phases:

 When the +CPWROFF AT command is sent, the module starts the switch-off routine.
 The module replies OK on the AT interface: the switch-off routine is in progress.
 At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage

regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).

 Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g.

applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N
input), and enters not-powered mode if the supply is removed from the VCC pins.

☞ The Internal Reset signal is not available on a module pin, but the application can monitor the

☞ The VCC supply can be removed only after the end of the module internal switch-off routine,

☞ The duration of each phase in the TOBY-R2 series modules’ switch-off routines can largely vary

Figure 15: TOBY-R2 series switch-off sequence by means of AT+CPWROFF command

V_INT pin to sense the end of the switch-off sequence.

i.e. only after that the V_INT voltage level has gone low.

depending on the application / network settings and the concurrent module activities.

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VCC

V_BCKP

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State

OFF

Tristate / Floating

ON

Operational -> Tristate

Operational

The module starts

the switch-off

VCC

can be removed

Figure 16 describes the TOBY-R2 series modules switch-off sequence started by means of the

PWR_ON input pin, allowing storage of current parameter settings in the module’s non-volatile
memory and a proper network detach, with the following phases:

 A low pulse with appropriate time duration (see TOBY-R2 series data sheet [1]) is applied at the

PWR_ON input pin, which is normally set high by an internal pull-up: the module starts the switch­off routine when the PWR_ON signal is released from the low logical level.

 At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage

regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).

 Then, the module remains in power-off mode as long as a switch-on event does not occur (e.g.

applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N
input), and enters not-powered mode if the supply is removed from the VCC pins.

☞ The Internal Reset signal is not available on a module pin, but the application can monitor the

☞ The VCC supply can be removed only after the end of the module internal switch-off routine, i.e.

☞ The duration of each phase in the TOBY-R2 series modules’ switch-off routines can largely vary

Figure 16: TOBY-R2 series switch-off sequence by means of PWR_ON pin

V_INT pin to sense the end of the switch-off sequence.

only after that the V_INT voltage level has gone low.

depending on the application / network settings and the concurrent module activities.

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