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SARA-G3 and SARA-U2 series

GSM/GPRS and GSM/EGPRS/HSPA Cellular Modules

System Integration Manual

Abstract

This document describes the features and the system integration of the SARA-G3 series GSM/GPRS cellular modules and the SARAGSM/EGPRS/HSPA cellular modules.

These modules are complete and cost efficient solutions offering voice and/or data communication over diverse cellular radio access technologies in the same compact SARA form factor: the SARAseries support up to 4-band GSM/GPRS while the SARAsupport 2-band high-speed HSPA and up to 2-band GSM/EGPRS.

-blox.com

-13000995 - R11

SARA-G3 and SARA-U2 series - System Integration Manual

Document Information

Title SARA-G3 and SARA-U2 series

Subtitle

GSM/GPRS and GSM/EGPRS/HSPA Cellular Modules

Document type System Integration Manual

Document number UBX-13000995

Revision, date R12 30-Jan-2015

Document status Early Production Information

Document status explanation

Objective Specification Document contains target values. Revised and supplementary data will be published later.

Advance Information Document contains data based on early testing. Revised and supplementary data will be published later.

Early Production Information Document contains data from product verification. Revised and supplementary data may be published later.

Production Information Document contains the final product specification.

This document applies to the following products:

Name Type number Modem version Application version SDN / IN / PCN

SARA-G300 SARA-G300-00S-00 08.58 GSM.G2-TN-13007 SARA-G310 SARA-G310-00S-00 08.58 GSM.G2-TN-13007 SARA-G340 SARA-G340-00S-00 08.49 UBX-14000382 SARA-G340-01S-00 08.70 A00.02 UBX-14039634 SARA-G350 SARA-G350-00S-00 08.49 GSM.G2-TN-13002 SARA-G350-01S-00 08.70 A00.02 UBX-14039634 SARA-G350-01B-00 08.70 A00.02 TBD SARA-G350 ATEX SARA-G350-00X-00 08.49 GSM.G2-TN-13002 SARA-U260 SARA-U260-00S-00 23.20 A01.00 UBX-14015739 SARA-U270 SARA-U270-00S-00 23.20 A01.00 UBX-14015739 SARA-U270 ATEX SARA-U270-00X-00 23.20 A01.00 TBD SARA-U280 SARA-U280-00S-00 23.28 A01.00 TBD

u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited.

The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com.

Trademark Notice

Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners.

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Preface

u-blox Technical Documentation

As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.

• AT Commands Manual: This document provides the description of the AT commands supported by the

u-blox cellular modules.

• System Integration Manual: This document provides the description of u-blox cellular modules’ system

from the hardware and the software point of view, it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules.

• Application Notes: These documents provide guidelines and information on specific hardware and/or

software topics on u-blox cellular modules. See Related documents for a list of application notes related to your cellular module.

How to use this Manual

The SARA-G3 and SARA-U2 series System Integration Manual provides the necessary information to successfully design in and configure these u-blox cellular modules.

This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance.

A warning symbol indicates actions that could negatively impact or damage the module.

Questions

If you have any questions about u-blox cellular Integration:

• Read this manual carefully.

• Contact our information service on the homepage

http://www.u-blox.com

Technical Support

Worldwide Web

Our website ( can be accessed 24h a day.

By E-mail

If you have technical problems or cannot find the required information in the provided documents, contact the closest Technical Support office. To ensure that we process your request as soon as possible, use our service pool email addresses rather than personal staff email addresses. Contact details are at the end of the document.

Helpful Information when Contacting Technical Support

When contacting Technical Support, have the following information ready:

• Module type (e.g. SARA-G350) and firmware version

• Module configuration

• Clear description of your question or the problem

• A short description of the application

• Your complete contact details

http://www.u-blox.com) is a rich pool of information. Product information and technical documents

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Preface ................................................................................................................................ 3

Contents .............................................................................................................................. 4

1 System description ....................................................................................................... 8

1.1 Overview .............................................................................................................................................. 8

1.2 Architecture ........................................................................................................................................ 10

1.2.1 Internal blocks ............................................................................................................................. 12

1.3 Pin-out ............................................................................................................................................... 13

1.4 Operating modes ................................................................................................................................ 18

1.5 Supply interfaces ................................................................................................................................ 20

1.5.1 Module supply input (VCC) ......................................................................................................... 20

1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 28

1.5.3 Generic digital interfaces supply output (V_INT) ........................................................................... 29

1.6 System function interfaces .................................................................................................................. 30

1.6.1 Module power-on ....................................................................................................................... 30

1.6.2 Module power-off ....................................................................................................................... 33

1.6.3 Module reset ............................................................................................................................... 35

1.6.4 External 32 kHz signal input (EXT32K) ......................................................................................... 36

1.6.5 Internal 32 kHz signal output (32K_OUT) .................................................................................... 36

1.7 Antenna interface ............................................................................................................................... 37

1.7.1 Antenna RF interface (ANT) ......................................................................................................... 37

1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 39

1.8 SIM interface ...................................................................................................................................... 39

1.8.1 (U)SIM card interface ................................................................................................................... 39

1.8.2 SIM card detection interface (SIM_DET) ....................................................................................... 39

1.9 Serial interfaces .................................................................................................................................. 40

1.9.1 Asynchronous serial interface (UART)........................................................................................... 40

1.9.2 Auxiliary asynchronous serial interface (UART AUX) ..................................................................... 53

1.9.3 USB interface............................................................................................................................... 53

1.9.4 DDC (I2C) interface ...................................................................................................................... 55

1.10 Audio interface ............................................................................................................................... 57

1.10.1 Analog audio interface ................................................................................................................ 57

1.10.2 Digital audio interface ................................................................................................................. 59

1.10.3 Voice-band processing system ..................................................................................................... 61

1.11 General Purpose Input/Output (GPIO) ............................................................................................. 64

1.12 Reserved pins (RSVD) ...................................................................................................................... 68

1.13 System features............................................................................................................................... 69

1.13.1 Network indication ...................................................................................................................... 69

1.13.2 Antenna detection ...................................................................................................................... 69

1.13.3 Jamming detection ...................................................................................................................... 69

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1.13.4

TCP/IP and UDP/IP ....................................................................................................................... 70

1.13.5 FTP .............................................................................................................................................. 70

1.13.6 HTTP ........................................................................................................................................... 70

1.13.7 SMTP ........................................................................................................................................... 70

1.13.8 SSL .............................................................................................................................................. 71

1.13.9 Dual stack IPv4/IPv6 ..................................................................................................................... 72

1.13.10 Smart temperature management ............................................................................................. 73

1.13.11 AssistNow clients and GNSS integration ................................................................................... 76

1.13.12 Hybrid positioning and CellLocate® .......................................................................................... 76

1.13.13 Firmware upgrade Over AT (FOAT) .......................................................................................... 79

1.13.14 Firmware upgrade Over The Air (FOTA) .................................................................................... 79

1.13.15 In-Band modem (eCall / ERA-GLONASS) .................................................................................. 80

1.13.16 SIM Access Profile (SAP) ........................................................................................................... 80

1.13.17 Power saving ........................................................................................................................... 82

2 Design-in ..................................................................................................................... 83

2.1 Overview ............................................................................................................................................ 83

2.2 Supply interfaces ................................................................................................................................ 84

2.2.1 Module supply (VCC) .................................................................................................................. 84

2.2.2 RTC supply (V_BCKP) ................................................................................................................... 96

2.2.3 Interface supply (V_INT) ............................................................................................................... 98

2.3 System functions interfaces ................................................................................................................ 99

2.3.1 Module power-on (PWR_ON) ...................................................................................................... 99

2.3.2 Module reset (RESET_N) ............................................................................................................ 100

2.3.3 32 kHz signal (EXT32K and 32K_OUT) ....................................................................................... 101

2.4 Antenna interface ............................................................................................................................. 103

2.4.1 Antenna RF interface (ANT) ....................................................................................................... 103

2.4.2 Antenna detection interface (ANT_DET) .................................................................................... 110

2.5 SIM interface .................................................................................................................................... 113

2.6 Serial interfaces ................................................................................................................................ 119

2.6.1 Asynchronous serial interface (UART)......................................................................................... 119

2.6.2 Auxiliary asynchronous serial interface (UART AUX) ................................................................... 125

2.6.3 Universal Serial Bus (USB) .......................................................................................................... 127

2.6.4 DDC (I2C) interface .................................................................................................................... 129

2.7 Audio interface ................................................................................................................................. 135

2.7.1 Analog audio interface .............................................................................................................. 135

2.7.2 Digital audio interface ............................................................................................................... 141

2.8 General Purpose Input/Output (GPIO) ............................................................................................... 144

2.9 Reserved pins (RSVD) ........................................................................................................................ 145

2.10 Module placement ........................................................................................................................ 145

2.11 Module footprint and paste mask ................................................................................................. 146

2.12 Thermal guidelines ........................................................................................................................ 147

2.13 ESD guidelines .............................................................................................................................. 149

2.13.1 ESD immunity test overview ...................................................................................................... 149

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2.13.2

ESD immunity test of u-blox SARA-G3 and SARA-U2 reference designs..................................... 149

2.13.3 ESD application circuits .............................................................................................................. 150

2.14 SARA-G350 ATEX and SARA-U270 ATEX integration in explosive atmospheres applications ......... 152

2.14.1 General guidelines ..................................................................................................................... 152

2.14.2 Guidelines for VCC supply circuit design ................................................................................... 153

2.14.3 Guidelines for antenna RF interface design ................................................................................ 154

2.15 Schematic for SARA-G3 and SARA-U2 series module integration .................................................. 156

2.15.1 Schematic for SARA-G300 / SARA-G310 modules integration ................................................... 156

2.15.2 Schematic for SARA-G340 / SARA-G350 modules integration ................................................... 157

2.15.3 Schematic for SARA-U2 series modules integration ................................................................... 158

2.16 Design-in checklist ........................................................................................................................ 159

2.16.1 Schematic checklist ................................................................................................................... 159

2.16.2 Layout checklist ......................................................................................................................... 160

2.16.3 Antenna checklist ...................................................................................................................... 160

3 Handling and soldering ........................................................................................... 161

3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 161

3.2 Handling ........................................................................................................................................... 161

3.3 Soldering .......................................................................................................................................... 162

3.3.1 Soldering paste.......................................................................................................................... 162

3.3.2 Reflow soldering ....................................................................................................................... 162

3.3.3 Optical inspection ...................................................................................................................... 163

3.3.4 Cleaning .................................................................................................................................... 163

3.3.5 Repeated reflow soldering ......................................................................................................... 164

3.3.6 Wave soldering.......................................................................................................................... 164

3.3.7 Hand soldering .......................................................................................................................... 164

3.3.8 Rework ...................................................................................................................................... 164

3.3.9 Conformal coating .................................................................................................................... 164

3.3.10 Casting ...................................................................................................................................... 164

3.3.11 Grounding metal covers ............................................................................................................ 164

3.3.12 Use of ultrasonic processes ........................................................................................................ 164

4 Approvals .................................................................................................................. 165

4.1 Product certification approval overview ............................................................................................. 165

4.2 Federal Communications Commission and Industry Canada notice ................................................... 166

4.2.1 Safety warnings review the structure ......................................................................................... 166

4.2.2 Declaration of conformity .......................................................................................................... 166

4.2.3 Modifications ............................................................................................................................ 167

4.3 R&TTED and European conformance CE mark .................................................................................. 168

4.4 Anatel certification ........................................................................................................................... 169

4.5 CCC mark ........................................................................................................................................ 170

4.6 SARA-G350 ATEX and LISA-U270 ATEX conformance for use in explosive atmospheres ................... 170

5 Product testing ......................................................................................................... 172

5.1 u-blox in-series production test ......................................................................................................... 172

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5.2

Test parameters for OEM manufacturer ............................................................................................ 172

5.2.1 “Go/No go” tests for integrated devices .................................................................................... 173

5.2.2 Functional tests providing RF operation ..................................................................................... 173

Appendix ........................................................................................................................ 176

A Migration between LISA and SARA-G3 modules ................................................... 176

A.1 Overview .......................................................................................................................................... 176

A.2 Checklist for migration ..................................................................................................................... 177

A.3 Software migration ........................................................................................................................... 178

A.4 Hardware migration.......................................................................................................................... 178

A.4.1 Supply interfaces ....................................................................................................................... 178

A.4.2 System functions interfaces ....................................................................................................... 179

A.4.3 Antenna interface ..................................................................................................................... 180

A.4.4 SIM interface ............................................................................................................................. 181

A.4.5 Serial interfaces ......................................................................................................................... 181

A.4.6 Audio interfaces ........................................................................................................................ 182

A.4.7 GPIO pins .................................................................................................................................. 182

A.4.8 Reserved pins ............................................................................................................................ 182

A.4.9 Pin-out comparison between LISA and SARA-G3 ....................................................................... 183

B Migration between SARA-G3 and SARA-U2 ........................................................... 188

B.1 Overview .......................................................................................................................................... 188

B.2 Pin-out comparison between SARA-G3 and SARA-U2 ...................................................................... 189

B.3 Schematic for SARA-G3 and SARA-U2 integration ............................................................................ 191

C Glossary .................................................................................................................... 192

Related documents......................................................................................................... 194

Revision history .............................................................................................................. 195

Contact ............................................................................................................................ 196

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3G Up

3G Down

2G Up

2G Down

3G bands [MHz] 2G bands [MHz] UART USB DDC

GPIO Analog

Digital audio Network indication Antenna

Jamming detection Embedded TCP

Embedded

GNSS via Modem AssistNow

CellLocate

FW update

FOTA

eCall / ERA

Low power idle

Dual stack IPv4/IPv6 ATEX certification Standard

Professional

Automotive

42.8

85.6

A = available upon request

E = 32 kHz signal at EXT32K input pin is required for low power idle-mode

1 System description

1.1 Overview

SARA-G3 series GSM/GPRS cellular modules and SARA-U2 series GSM/EGPRS/HSPA cellular modules are versatile solutions offering voice and/or data communication over diverse radio access technologies in the same miniature SARA LGA form factor (26 x 16 mm) that allows seamless drop-in migration between the two SARA-G3 and SARA-U2 series and easy migration to u-blox LISA-U series GSM/EGPRS/HSPA+ modules, LISA-C2 series CDMA modules, TOBY-L1 series LTE modules and to TOBY-L2 series GSM/EGPRS/DC-HSPA+/LTE modules.

SARA-G350 and SARA-G340 are respectively quad-band and dual-band full feature GSM/GPRS cellular modules with a comprehensive feature set including an extensive set of internet protocols and access to u-blox GNSS positioning chips and modules, with embedded A-GPS (AssistNow Online and AssistNow Offline) functionality.

SARA-G310 and SARA-G300 are respectively quad-band and dual-band GSM/GPRS cellular modules targeted for high volume cost sensitive applications, providing GSM/GPRS functionalities with a reduced set of additional features to minimize the customer’s total cost of ownership.

SARA-U2 series include variants supporting band combination for North America and band combination for Europe, Asia and other countries. For each combination, a complete UMTS/GSM variant and a cost-saving UMTS-only variant are available. All SARA-U2 series modules provide a rich feature set including an extensive set of internet protocols, dual-stack IPv4 / IPv6 and access to u-blox GNSS positioning chips and modules, with embedded A-GPS (AssistNow Online and AssistNow Offline) functionality.

Table 1 describes a summary of interfaces and features provided by SARA-G3 and SARA-U2 series modules.

Module Data rate Bands Interfaces Audio

SARA-G300

SARA-G310

SARA-G340

SARA-G350

SARA-G350 ATEX

SARA-U260 5.76 7.2

SARA-U270

SARA-U270 ATEX 5.76 7.2

SARA-U280

V = available from product version “01” onwards

Table 1: SARA-G3 and SARA-U2 series1 features summary

-Link [Mb/s]

5.76 7.2

5.76 7.2 850/1900 1 1 1 9 1 • • • • • • • • • • • •

-Link [kb/s]

85.6 900/1800 2 • E

85.6 4-band 2 • E

85.6 900/1800 2 1 4 1 1 • • • • • V • • • • • •

85.6 4-band 2 1 4 1 1 • • • • • V • • • • A • •

85.6 4-band 2 1 4 1 1 • • • • • • • • • • • •

236.8 850/1900 850/1900 1 1 1 9 1 • • • • • • • • • • • •

236.8 900/2100 900/1800 1 1 1 9 1 • • • • • • • • • • • • •

236.8 900/2100 900/1800 1 1 1 9 1 • • • • • • • • • • • • • •

Functions Grade

/ UDP

SSL / TLS

audio

supervisor

HTTP, FTP

via serial

Software

-mode

-GLONASS

SARA-G350 ATEX modules provide the same feature set of the SARA-G350 modules plus the certification for use in potentially explosive atmospheres; the same applies for SARA-U270 ATEX modules and SARA-U270 modules. Unless otherwise specified, SARA-G350 refers to all SARA-G350 ATEX and SARA-G350 modules, whereas SARA-U270 refers to all SARA-U270 ATEX modules and SARA-U270 modules.

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Protocol stack

3GPP Release 7

3GPP Release 99

Table 2 reports a summary of 2G cellular characteristics of SARA-G3 and SARA-U2 series modules.

Item SARA-U260 SARA-U270 SARA-G300 / SARA-G340 SARA-G310 / SARA-G350

MS class Class B2 Class B2 Class B2 Class B2

Bands3 GSM 850 MHz

PCS 1900 MHz

Power class Class 4 (33 dBm)

for 850 band Class 1 (30 dBm) for 1900 band

PS data rate4 GPRS multi-slot class 125

CS 1-4, 85.6 kb/s DL CS 1-4, 85.6 kb/s UL EDGE multi-slot class 12 MCS 1-9, 236.8 kb/s DL MCS 1-4, 70.4 kb/s UL

CS data rate4 Up to 9.6 kb/s DL/UL

Transparent mode Non transparent mode

Table 2: SARA-G3 series and SARA-U2 series 2G characteristics summary

E-GSM 900 MHz DCS 1800 MHz

Class 4 (33 dBm) for 900 band Class 1 (30 dBm) for 1800 band

GPRS multi-slot class 12 CS 1-4, 85.6 kb/s DL CS 1-4, 85.6 kb/s UL

EDGE multi-slot class 12 MCS 1-9, 236.8 kb/s DL MCS 1-4, 70.4 kb/s UL

Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode

E-GSM 900 MHz DCS 1800 MHz

Class 4 (33 dBm) for 900 band Class 1 (30 dBm) for 1800 band

GPRS multi-slot class 10 CS 1-4, 85.6 kb/s DL CS 1-4, 42.8 kb/s UL

Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode

GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz

Class 4 (33 dBm) for 850/900 bands Class 1 (30 dBm) for 1800/1900 bands

GPRS multi-slot class 10 CS 1-4, 85.6 kb/s DL

CS 1-4, 42.8 kb/s UL

Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode

Table 3 reports a summary of 3G cellular characteristics of SARA-U2 series modules.

Item SARA-U260 SARA-U270 SARA-U280

Protocol stack 3GPP Release 7 3GPP Release 7 3GPP Release 7

UE class Class A

Bands Band V (850 MHz)

Power class Class 3 (24 dBm)

PS data rate4 HSUPA category 6

Class A7 Class A7

Band VIII (900 MHz)

Band II (1900 MHz)

Band I (2100 MHz)

Class 3 (24 dBm)

for all bands

HSUPA category 6

5.76 Mb/s UL HSDPA category 8

7.2 Mb/s DL

5.76 Mb/s UL HSDPA category 8

7.2 Mb/s DL

Band V (850 MHz) Band II (1900 MHz)

Class 3 (24 dBm) for all bands

HSUPA category 6

5.76 Mb/s UL HSDPA category 8

7.2 Mb/s DL

CS data rate4 Up to 64 kb/s DL/UL Up to 64 kb/s DL/UL Up to 64 kb/s DL/UL

Table 3: SARA-U2 series 3G characteristics summary

Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time.

The 2G 850 / 1900 MHz and 3G 850 / 1900 MHz bands are mainly operative in America. The 2G 900 / 1800 MHz and 3G 900 / 2100 MHz bands are mainly operative in Europe, Asia and other countries.

The maximum bit rate of the module depends on the actual network environmental conditions and settings.

GPRS/EDGE multi-slot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total.

GPRS multi-slot class 10 implies a maximum of 4 slots in DL (reception) and 2 slots in UL (transmission) with 5 slots in total.

Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active without any interruption in service.

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Memory

V_BCKP (RTC)

V_INT (I/O)

32 kHz

26 MHz

Transceiver

Power

Management

ANT

SAW Filter

Switch

VCC (Supply)

32 kHz

Auxiliary UART

SIM

UART

Power-On

Reset

Cellular BaseBand Processor

Memory

V_BCKP (RTC)

V_INT (I/O)

26 MHz

32.768 kHz

Transceiver

Power

Management

Cellular BaseBand Processor

ANT

SAW Filter

Switch

VCC (Supply)

Auxiliary UART

DDC (for GNSS)

SIM Card Detection

SIM

UART

Power-On

Reset

Digital Audio

Analog Audio

GPIO

Antenna Detection

1.2 Architecture

Figure 1 summarizes the architecture of SARA-G300 and SARA-G310 modules, while Figure 2 summarizes the architecture of SARA-G340 and SARA-G350 modules, describing the internal blocks of the modules, consisting of the RF, Baseband and Power Management main sections, and the available interfaces.

Figure 1: SARA-G300 and SARA-G310 modules block diagram

Figure 2: SARA-G340 and SARA-G350 modules block diagram

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Memory

V_BCKP (RTC)

V_INT (I/O)

Transceiver

Power

Management

Cellular BaseBand Processor

ANT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UART

Power

-On

Reset

Digital audio (I2S)

GPIO

Antenna detection

3G PA

26 MHz

Duplexer

Filter

Switch

2G PA

LNA

32.768 kHz

Memory

V_BCKP (RTC)

V_INT (I/O)

Transceiver

Power

Management

Cellular

BaseBand

Processor

ANT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UART

Power-On

Reset

Digital audio (I2S)

GPIO

Antenna detection

3G PA

26 MHz

Duplexer

Filter

Switch

LNA

32.768 kHz

Figure 3 summarizes the architecture of SARA-U260 and SARA-U270 modules, while Figure 4 summarizes the architecture of SARA-U280 modules, describing the internal blocks of the modules, consisting of the RF, Baseband and Power Management main sections, and the available interfaces.

Figure 3: SARA-U260 and SARA-U270 modules block diagram

Figure 4: SARA-U280 modules block diagram

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1.2.1 Internal blocks

SARA-G3 and SARA-U2 series modules internally consist of the RF, Baseband and Power Management sections here described with more details than the simplified block diagrams of Figure 1, Figure 2, Figure 3 and Figure 4.

RF section

The RF section is composed of the following main elements:

• 2G / 3G RF transceiver performing modulation, up-conversion of the baseband I/Q signals, down-conversion

and demodulation of the RF received signals. The RF transceiver includes:

Constant gain direct conversion receiver with integrated LNAs Highly linear RF quadrature GMSK demodulator Digital Sigma-Delta transmitter GMSK modulator Fractional-N Sigma-Delta RF synthesizer

3.8 GHz VCO Digital controlled crystal oscillator

• 2G / 3G Power Amplifier, which amplifies the signals modulated by the RF transceiver

• RF switch, which connects the antenna input/output pin (ANT) of the module to the suitable RX/TX path

• RX diplexer SAW (band pass) filters

• 26 MHz crystal, connected to the digital controlled crystal oscillator to perform the clock reference in

active-mode or connected-mode

Baseband and Power Management section

The Baseband and Power Management section is composed of the following main elements:

• Baseband processor, a mixed signal ASIC which integrates:

Microprocessor for controller functions DSP core for 2G / 3G Layer 1 and audio processing Dedicated peripheral blocks for parallel control of the digital interfaces Audio analog front-end

• Memory system in a multi-chip package integrating two devices:

NOR flash non-volatile memory RAM volatile memory

• Voltage regulators to derive all the system supply voltages from the module supply VCC

• Circuit for the RTC clock reference in low power idle-mode:

SARA-G340, SARA-G350 and SARA-U2 series modules are equipped with an internal 32.768 kHz crystal connected to the oscillator of the RTC (Real Time Clock) block that gives the RTC clock reference needed to provide the RTC functions as well as to reach the very low power idle-mode (with power saving configuration enabled by the AT+UPSV command).

SARA-G300 and SARA-G310 modules are not equipped with an internal 32.768 kHz crystal: a proper 32 kHz signal must be provided at the EXT32K input pin of the modules to give the RTC clock reference and to provide the RTC functions as well as to reach the very low power idle-mode (with power saving configuration enabled by AT+UPSV). The 32K_OUT output pin of SARA-G300 and SARA-G310 provides a 32 kHz reference signal suitable only to feed the EXT32K input pin, furnishes the reference clock for the RTC, and allows low power idle-mode and RTC functions support with modules switched on.

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5, 14,

22, 30,

1.3 Pin-out

Table 4 lists the pin-out of the SARA-G3 and SARA-U2 series modules, with pins grouped by function.

Function Pin Name Module Pin No I/O Description Remarks

Power VCC All 51, 52, 53 I Module supply

GND All 1, 3,

V_BCKP All 2 I/O Real Time Clock

V_INT All 4 O Generic Digital

System PWR_ON All 15 I Power-on input High input impedance: input voltage level has to be

RESET_N All 18 I External reset

EXT32K SARA-G300

SARA-G310

32K_OUT SARA-G300

SARA-G310

Antenna ANT All 56 I/O RF input/output

ANT_DET SARA-G340

SARA-G350 SARA-U2

2032, 43, 50 54, 55, 57-61, 63-96

31 I 32 kHz input Input for RTC reference clock, needed to enter the

24 O 32 kHz output 32 kHz output suitable only to feed the EXT32K

62 I Input for antenna

input

N/A Ground GND pins are internally connected each other.

supply input/output

Interfaces supply output

input

for antenna

detection

VCC pins are internally connected each other. VCC supply circuit affects the RF performance and

compliance of the device integrating the module with applicable required certification schemes. See section 1.5.1 for functional description and requirements for the VCC module supply. See section 2.2.1 for external circuit design-in.

External ground connection affects the RF and thermal performance of the device. See section 1.5.1 for functional description. See section 2.2.1 for external circuit design-in.

V_BCKP = 2.3 V (typical) on SARA-G3 series. V_BCKP = 1.8 V (typical) on SARA-U2 series. V_BCKP is generated by internal low power linear

regulator when valid VCC supply is present. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.

V_INT = 1.8 V (typical), generated by internal DC/DC regulator when the module is switched on.

See section 1.5.3 for functional description. See section 2.2.3 for external circuit design-in.

properly fixed, e.g. adding external pull-up. See section 1.6.1 for functional description. See section 2.3.1 for external circuit design-in.

A series Schottky diode is integrated in the module as protection, and then an internal 10 kΩ pull-up resistor to V_INT is provided. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in.

low power idle-mode and provide RTC functions. See section 1.6.4 for functional description. See section 2.3.3 for external circuit design-in.

input giving the RTC reference clock, allowing low power idle-mode and RTC functions support. See section 1.6.5 for functional description. See section 2.3.3 for external circuit design-in.

50 Ω nominal characteristic impedance. Antenna circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes. See section 1.7 for functional description and requirements for the antenna RF interface. See section 2.4 for external circuit design-in.

ADC input for antenna detection function. See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in.

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Function Pin Name Module Pin No I/O Description Remarks

SIM VSIM All 41 O SIM supply output VSIM = 1.80 V typ. or 2.85 V typ. automatically

SIM_IO All 39 I/O SIM data Data input/output for 1.8 V / 3 V SIM

SIM_CLK All 38 O SIM clock 3.25 MHz clock output for 1.8 V / 3 V SIM

SIM_RST All 40 O SIM reset Reset output for 1.8 V / 3 V SIM

SIM_DET All 42 I /

UART RXD All 13 O UART data output 1.8 V output, Circuit 104 (RXD) in ITU-T V.24,

TXD All 12 I UART data input 1.8 V input, Circuit 103 (TXD) in ITU-T V.24,

CTS All 11 O UART clear to

RTS All 10 I UART ready to

DSR All 6 O UART data set

RI All 7 O UART ring

DTR All 9 I UART data

DCD All 8 O UART data carrier

I/O

SIM detection / GPIO

send output

send input

ready output

indicator output

terminal ready input

detect output

generated according to the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in.

Internal 4.7 kΩ pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.

See section 1.8 for functional description. See section 2.5 for external circuit design-in.

1.8 V input for SIM presence detection function. Pin configurable also as GPIO on SARA-U2 series. See section 1.8.2 for functional description. See section 2.5 for external circuit design-in.

for AT, data, FOAT on SARA-G3 series modules, for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic on SARA-U2 series modules. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

for AT, data, FOAT on SARA-G3 series modules, for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic on SARA-U2 series modules.

Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V output, Circuit 106 (CTS) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V output, Circuit 107 (DSR) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V output, Circuit 125 (RI) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

1.8 V input, Circuit 109 (DCD) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

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Function Pin Name Module Pin No I/O Description Remarks

Auxiliary UART

RXD_AUX SARA-G3 28 O Auxiliary UART

data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for FW upgrade via EasyFlash tool and diagnostic.

Access by external test-point is recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

TXD_AUX SARA-G3 29 I Auxiliary UART

data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for FW upgrade via EasyFlash tool and diagnostic. Access by external test-point is recommended. Internal active pull-up to V_INT.

See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB VUSB_DET SARA-U2 17 I USB detect input High-Speed USB 2.0 interface input for VBUS (5 V

typical) USB supply sense. USB available for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

USB_D- SARA-U2 28 I/O USB Data Line D- High-Speed USB 2.0 interface data line for AT, data,

FOAT, FW upgrade via EasyFlash tool and diagnostic. 90 Ω nominal differential impedance. Pull-up, pull-down and series resistors as required by

USB 2.0 specifications [14] are part of the USB pin driver and need not be provided externally. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

USB_D+ SARA-U2 29 I/O USB Data Line D+ High-Speed USB 2.0 interface data line for AT, data,

FOAT, FW upgrade via EasyFlash tool and diagnostic. 90 Ω nominal differential impedance. Pull-up, pull-down and series resistors as required by

USB 2.0 specifications [14] are part of the USB pin driver and need not be provided externally. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

DDC SCL SARA-G340

SARA-G350 SARA-U2

27 O I

C bus clock line 1.8 V open drain, for the communication with the

u-blox positioning modules / chips. Communication with other external I

C-slave devices as an audio codec is additionally supported by SARA-U2 series. External pull-up required. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SDA SARA-G340

SARA-G350 SARA-U2

26 I/O I

C bus data line 1.8 V open drain, for the communication with

u-blox positioning modules / chips. Communication with other external I

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Function Pin Name Module Pin No I/O Description Remarks

Analog Audio

MIC_BIAS SARA-G340

SARA-G350

46 O Microphone

supply output

Supply output (2.2 V typ) for external microphone. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

MIC_GND SARA-G340

SARA-G350

47 I Microphone

analog reference

Local ground for the external microphone (reference for the analog audio uplink path). See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

MIC_N SARA-G340

SARA-G350

48 I Differential

analog audio input (negative)

Differential analog audio signal input (negative) shared for all the analog uplink path modes: handset, headset, hands-free mode.

No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

MIC_P SARA-G340

SARA-G350

49 I Differential

analog audio input (positive)

Differential analog audio signal input (positive) shared for all the analog uplink path modes: handset, headset, hands-free mode.

No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

SPK_P SARA-G340

SARA-G350

44 O Differential

analog audio output (positive)

Differential analog audio signal output (positive) shared for all the analog downlink path modes: earpiece, headset and loudspeaker mode.

See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

SPK_N SARA-G340

SARA-G350

45 O Differential

analog audio output (negative)

Differential analog audio signal output (negative) shared for all the analog downlink path modes: earpiece, headset and loudspeaker mode.

See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.

Digital Audio

I2S_CLK SARA-G340

SARA-G350 SARA-U2

36 O /

I/O

S clock /

GPIO

1.8 V serial clock for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in.

I2S_RXD SARA-G340

SARA-G350 SARA-U2

37 I /

I/O

S receive data /

GPIO

1.8 V data input for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. Internal active pull-down to GND. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in.

I2S_TXD SARA-G340

SARA-G350 SARA-U2

35 O /

I/O

S transmit data /

GPIO

1.8 V data output for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in.

I2S_WA SARA-G340

SARA-G350 SARA-U2

34 O /

I/O

I2S word alignment GPIO

1.8 V word alignment for PCM / normal I2S modes Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in.

CODEC_CLK SARA-U2 19 O Clock output 1.8 V master clock output for external audio codec

See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in

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See section 2.8 for external circuit design-in.

SARA-G310

See section 2.9

Function Pin Name Module Pin No I/O Description Remarks

GPIO GPIO1 SARA-G340

SARA-G350 SARA-U2

GPIO2 SARA-G340

SARA-G350 SARA-U2

GPIO3 SARA-G340

SARA-G350 SARA-U2

GPIO4 SARA-G340

SARA-G350 SARA-U2

Reserved RSVD All 33 N/A RESERVED pin This pin must be connected to ground.

RSVD SARA-G3 17, 19 N/A RESERVED pin Leave unconnected.

RSVD SARA-G340

SARA-G350 SARA-U2

RSVD SARA-G300

SARA-G310

RSVD SARA-G300

SARA-G310 SARA-U2

RSVD SARA-G300

16 I/O GPIO 1.8 V GPIO by default configured as pin disabled.

See section 1.11 for functional description. See section 2.8 for external circuit design-in.

23 I/O GPIO 1.8 V GPIO by default configured to provide the

24 I/O GPIO 1.8 V GPIO by default configured to provide the

25 I/O GPIO 1.8 V GPIO by default configured to provide the

31 N/A RESERVED pin Internally not connected. Leave unconnected.

16, 23, 25-27, 34-37

44-49 N/A RESERVED pin Leave unconnected.

62 N/A RESERVED pin Leave unconnected.

N/A RESERVED pin Pin disabled. Leave unconnected.

custom GNSS supply enable function. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

custom GNSS data ready function. See section 1.11 for functional description.

custom GNSS RTC sharing function. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

See section 2.9

Table 4: SARA-G3 and SARA-U2 series modules pin definition, grouped by function

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1.4 Operating modes

SARA-G3 modules have several operating modes. The operating modes defined in Table 5 and described in detail in Table 6 provide general guidelines for operation.

General Status Operating Mode Definition

Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal Operation Idle-Mode Module processor core runs with 32 kHz reference, that is generated by:

• The internal 32 kHz oscillator (SARA-G340, SARA-G350 and SARA-U2 series)

• The 32 kHz signal provided at the EXT32K pin (SARA-G300 and SARA-G310)

Active-Mode Module processor core runs with 26 MHz reference generated by the internal oscillator. Connected-Mode Voice or data call enabled and processor core runs with 26 MHz reference.

Table 5: Module operating modes definition

Operating Mode

Not-Powered Module is switched off.

Power-Off Module is switched off: normal shutdown by an

Idle The module is not ready to communicate with

Description Transition between operating modes

When VCC supply is removed, the module enters not-powered mode. Application interfaces are not accessible. Internal RTC operates on SARA-G340/G350,

SARA-U2 if a valid voltage is applied to V_BCKP. Additionally, a proper external 32 kHz signal must be fed to EXT32K on SARA-G300/G310

When in not-powered mode, the modules cannot be switched on by

PWR_ON, RESET_N or RTC alarm.

When in not-powered mode, the modules can be switched on applying

VCC supply (see 2.3.1) so that the module switches from not-powered

to active-mode. modules to let internal RTC timer running.

When the module is switched off by an appropriate power-off event appropriate power-off event (see 1.6.2).

Application interfaces are not accessible. Internal RTC operates on SARA-G340/G350,

SARA-U2 as V_BCKP is internally generated. A proper external 32 kHz signal must be fed to the EXT32K pin on SARA-G300/G310 to let RTC

(see 1.6.2), the module enters power-off mode from active-mode.

When in power-off mode, the modules can be switched on by

PWR_ON, RESET_N or RTC alarm (see 2.3.1): the module switches

from power-off to active-mode.

When VCC supply is removed, the module switches from power-off

mode to not-powered mode. timer running that otherwise is not in operation.

The module automatically switches from active-mode to idle-mode an external device by means of the application interfaces as configured to reduce consumption.

The module automatically enters idle-mode whenever possible if power saving is enabled by the AT+UPSV command (see u-blox AT Commands Manual [3]), reducing power consumption (see section 1.5.1.4).

The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active-mode according to power saving and HW flow control settings (see 1.9.1.3, 1.9.1.4).

Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [3]).

A proper 32 kHz signal must be fed to the EXT32K pin of SARA-G300/G310 modules to let idle-mode that otherwise cannot be reached (this is not needed for the other SARA-G3 and SARA-U2 series modules).

whenever possible if power saving is enabled (see sections 1.5.1.4,

1.9.1.4 and to the u-blox AT Commands Manual [3], AT+UPSV).

The module wakes up from idle to active mode in the following events:

• Automatic periodic monitoring of the paging channel for the

paging block reception according to network conditions (see

1.5.1.4, 1.9.1.4)

• Automatic periodic enable of the UART interface to receive and

send data, if AT+UPSV=1 power saving is set (see 1.9.1.4)

• RTC alarm occurs (see u-blox AT Commands Manual [3], +CALA)

• Data received on UART interface, according to HW flow control

(AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)

• RTS input line set to the ON state by the DTE, if HW flow control

is disabled by AT&K3 and AT+UPSV=2 is set (see 1.9.1.4)

• DTR input line set to the ON state by the DTE, if AT+UPSV=3

power saving is set (see 1.9.1.4)

• USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.3)

• The connected USB host forces a remote wakeup of the module

as USB device (see 1.9.3)

• GNSS data ready: when the GPIO3 pin is informed by the

connected u-blox GNSS receiver that it is ready to send data over the DDC (I

C) communication interface (see 1.11, 1.9.4)

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Switch ON:

• Apply VCC

If power saving

is enabled and there is no activity for a defined time interval

Any wake up event described in the module operating modes summary table above

Incoming/outgoing call or other dedicated device network communication

No RF Tx/Rx in progress, Call terminated, Communication dropped

Remove VCC

Switch ON:

• PWR_ON

• RTC alarm

• RESET_N

(SARA-U2)

Not

powered

Power off

ActiveConnected Idle

Switch OFF:

• AT+CPWROFF

• PWR_ON

(SARA-U2)

Operating Mode

Active The module is ready to communicate with an

Connected A voice call or a data call is in progress.

Table 6: Module operating modes description

Description Transition between operating modes

external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and to the u-blox AT Commands Manual [3]).

The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and the u-blox AT Commands Manual [3]).

When the module is switched on by an appropriate power-on event (see 2.3.1), the module enters active-mode from not-powered or power-off mode.

If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see idle to active transition description).

When a voice call or a data call is initiated, the module switches from active-mode to connected-mode.

When a voice call or a data call is initiated, the module enters connected-mode from active-mode.

When a voice call or a data call is terminated, the module returns to the active-mode.

Figure 5 describes the transition between the different operating modes.

Figure 5: Operating modes transition

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ripple

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input. The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit:

all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators, including V_BCKP Real Time Clock supply, V_INT digital interfaces supply and VSIM SIM card supply.

During operation, the current drawn by the SARA-G3 and SARA-U2 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in connected-mode (as described in section 1.5.1.2), to the low current consumption during low power idle-mode with power saving enabled (as described in section 1.5.1.4).

1.5.1.1 VCC supply requirements

Table 7 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 7.

VCC supply circuit affects the RF compliance of the device integrating SARA-G3 and SARA-U2

series modules with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the VCC requirements summarized in the Table 7 are fulfilled.

For the additional specific requirements for SARA-G350 ATEX and SARA-U270 ATEX modules integration

in potentially explosive atmospheres applications, see section 2.14.

Item Requirement Remark

VCC nominal voltage Within VCC normal operating range:

3.35 V min. / 4.50 V max for SARA-G3 series

3.30 V min. / 4.40 V max for SARA-U2 series

VCC voltage during normal operation

VCC average current Support with adequate margin the highest averaged

VCC peak current Support with margin the highest peak VCC current

VCC voltage drop

during 2G Tx slots

VCC voltage ripple during 2G/3G Tx

VCC under/over-shoot at start/end of Tx slots

Within VCC extended operating range:

3.00 V min. / 4.50 V max for SARA-G3 series

3.10 V min. / 4.50 V max for SARA-U2 series

VCC current consumption value in connected-mode conditions specified in SARA-G3 series Data Sheet [1] and in SARA-U2 series Data Sheet [2].

consumption value specified in SARA-G3 series Data Sheet [1] and in SARA-U2 series Data Sheet [2].

Lower than 400 mV VCC voltage drop directly affects the RF compliance with

Lower than 50 mVpp if f Lower than 10 mVpp if 200 kHz < f Lower than 2 mVpp if f

Absent or at least minimized VCC under/over-shoot directly affects the RF compliance

≤ 200 kHz

ripple

> 400 kHz

≤ 400 kHz

ripple

The module cannot be switched on if VCC voltage value is below the normal operating range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for at least more than 3 s after the module switch-on.

The module may switch off when VCC voltage drops below the extended operating range minimum limit. Operation above extended operating range limit is not recommended and may affect device reliability.

The highest averaged VCC current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and VCC voltage.

See 1.5.1.2, 1.5.1.3 for connected-mode current profiles.

The specified highest peak of VCC current consumption occurs during GSM single transmit slot in 850/900 MHz connected-mode, in case of mismatched antenna.

See

1.5.1.2 for 2G connected-mode current profiles.

applicable certification schemes. Figure 7 describes VCC voltage drop during Tx slots.

VCC voltage ripple directly affects the RF compliance with applicable certification schemes. Figure 7 describes VCC voltage ripple during Tx slots.

with applicable certification schemes. Figure 7 describes VCC voltage under/over-shoot.

Table 7: Summary of VCC supply requirements

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Time [ms]

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200 mA

60-120 mA

1900 mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5

1.0

0.5

0.0

2.0

60-120 mA

10-40 mA

Time

undershoot

overshoot

ripple

drop

Voltage

3.8 V (typ)

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5.1.2 VCC current consumption in 2G connected-mode

When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts.

The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption.

If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands, at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the current consumption can reach an high peak / pulse (see SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2])

for

576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications.

During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts and it is low in the bursts unused to transmit / receive.

Figure 6 shows an example of the module current consumption profile versus time in GSM talk mode.

Figure 6: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)

Figure 7 illustrates VCC voltage profile versus time during a GSM call, according to the related VCC current consumption profile described in Figure 6.

Figure 7: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot)

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Time [ms]

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

TX slot

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

60-120mA

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5

1.0

0.5

0.0

60-120mA

10-40mA

200mA

Peak current depends

on TX power and

actual antenn a load

1600 mA

Time [ms]

slot

unused

slot

TX slot

MON

slot

unused

slot

unused

slot

TX slot

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

60-120mA

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5

1.0

0.5

0.0

60-120mA

10-40mA

200mA

Peak current depends

on TX power and

actual antenna load

1600 mA

When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as can be in case of a GSM call.

If the module transmits in GPRS multi-slot class 10 or 12, in 850 or 900 MHz bands, at maximum RF power level, the consumption can reach a quite high peak but lower than the one achievable in 2G single-slot mode. This happens for 1.154 ms (width of the 2 Tx slots/bursts) in case of multi-slot class 10 or for 2.308 ms (width of the 4 Tx slots/bursts) in case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/4 or 1/2 duty cycle, according to GSM TDMA.

If the module is in GPRS connected-mode in 1800 or 1900 MHz bands, consumption figures are lower than in the 850 or 900 MHz band, due to 3GPP Tx power specifications.

Figure 8 reports the current consumption profiles in GPRS connected-mode, in the 850 or 900 MHz bands, with 2 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 10.

Figure 8: VCC current consumption profile versus time during a GPRS multi-slot class 10 connection (2 TX slots, 1 RX slot)

Figure 9 reports the current consumption profiles in GPRS connected-mode, in the 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.

Figure 9: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)

For detailed current consumption values during 2G single-slot or multi-slot connection see SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2].

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Time

[ms]

3G frame

10 ms

(1 frame = 15 slots)

Current [mA]

Current consumption

depends on TX power and

actual antenna load

170 mA

1 slot

666 µs

850 mA

300

200

100

500

400

600

700

800

1.5.1.3 VCC current consumption in 3G connected mode

During a 3G connection, the SARA-U2 modules can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA).

The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a maximum rate of 1.5 kHz.

There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case.

In the worst scenario, corresponding to a continuous transmission and reception at maximum RF output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins is high (see the SARA-U2 series Data Sheet [2]).

Even at lowest RF output power level (approximately 0.01 µW or -50 dBm), the

average current is still not so low as in the equivalent 2G case, also due to module continuous baseband processing and transceiver activity.

Figure 10 shows an example of current consumption profile of SARA-U2 series modules in 3G WCDMA/HSPA continuous transmission and reception mode. For detailed current consumption values during a 3G connection see the SARA-U2 series Data Sheet [2].

Figure 10: VCC current consumption profile versus time during a 3G connection (TX and RX continuously enabled)

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20-30 ms

IDLE MODE

ACTIVE MODE IDLE MODE

300-600 µA

Active Mode

Enabled

Idle Mode

Enabled

300-600 µA

60-120 mA

2G case: 0.44

-2.09 s

3G case: 0.61-5.09 s

IDLE MODE

20-30 ms

ACTIVE MODE

Time [s]

Current [mA]

100

Time [ms]

Current [mA]

100

4-5 mA

60-120 mA

Enabled

20-40 mA

DSP

Enabled

1.5.1.4 VCC current consumption in cyclic idle/active-mode (power saving enabled)

The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (see u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, reducing current consumption.

During idle-mode, the module processor runs with 32 kHz reference clock:

• the internal oscillator automatically generates the 32 kHz clock on SARA-G340, SARA-G350, SARA-U2 series

• a valid 32 kHz signal must be properly provided to the EXT32K input pin of the SARA-G300 and

SARA-G310 modules to let low power idle-mode, that otherwise cannot be reached by these modules.

When the power saving configuration is enabled and the module is registered or attached to a network, the module automatically enters the low power idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the 2G or 3G system requirements, even if connected-mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active-mode, to enable the reception of paging block. In between, the module switches to low power idle-mode. This is known as discontinuous reception (DRX).

The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode.

The time period between two paging block receptions is defined by the network. This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell.

• In case of 2G radio access technology, the paging period varies from 470.8 ms (DRX = 2, length of 2 x 51

2G frames = 2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms)

• In case of 3G radio access technology, the paging period can vary from 640 ms (DRX = 6, i.e. length of 26

3G frames = 64 x 10 ms) up to 5120 ms (DRX = 9, length of 29 3G frames = 512 x 10 ms).

Figure 11 roughly describes the current consumption profile of SARA-G300 and SARA-G310 modules (when their EXT32K input pin is fed by an external 32 kHz signal with characteristics compliant to the one specified in SARA-G3 series Data Sheet [1]), or the SARA-G340 and SARA-G350 modules, or the SARA-U2 modules, when power saving is enabled. The module is registered with the network, automatically enters the very low power idle-mode, and periodically wakes up to active-mode to monitor the paging channel for paging block reception.

Figure 11: VCC current consumption profile versus time of the SARA-G300 and SARA-G310 modules (with the EXT32K input fed by a proper external 32 kHz signal), or the SARA-G340 and SARA-G350 modules, or the SARA-U2 modules, when registered with the network, with power saving enabled: the very low power idle-mode is reached and periodical wake up to active-mode are performed to monitor the paging channel

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20-30 ms

IDLE MODE ACTIVE MODE IDLE MODE

3-4 mA

Active Mode

Enabled

Idle Mode

Enabled

3-4 mA

60-120 mA

0.44-2.09 s

IDLE MODE

20-30 ms

ACTIVE MODE

Time [s]

Current [mA]

100

Time [ms]

Current [mA]

100

4-5 mA

60-120 mA

Enabled

20-40 mA

DSP

Enabled

Figure 12 roughly describes the current consumption profile of SARA-G300 and SARA-G310 modules when the EXT32K input pin is fed by the 32K_OUT output pin provided by these modules, when power saving is enabled. The module is registered with the network, automatically enters the low power idle-mode and periodically wakes up to active-mode to monitor the paging channel for paging block reception.

Figure 12: VCC current consumption profile versus time of the SARA-G300 and SARA-G310 modules (with the EXT32K input pin fed by the 32K_OUT output pin provided by these modules), when registered with the network, with power saving enabled: the low power idle-mode is reached and periodical wake up to active-mode are performed to monitor the paging channel

For detailed current consumption values with the module registered with 2G or 3G network with power saving enabled (cyclic idle/active-mode) see SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2].

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ACTIVE MODE

60-120 mA

0.47-2.12 s

Paging period

Time [s]

Current [mA]

100

Time [ms]

Current [mA]

100

3-5 mA

60-120 mA

Enabled

20-40 mA

DSP

Enabled

-5 mA

3-5 mA

1.5.1.5 VCC current consumption in fixed active-mode (power saving disabled)

Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (see u-blox AT Commands Manual [3], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle-mode whenever possible: the module remains in active-mode.

The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. Figure 13 roughly describes the current consumption profile of the SARA-G300 and SARA-G310 modules (when

the EXT32K input pin is fed by external 32 kHz signal with characteristics compliant to the one specified in SARA-G3 series Data Sheet [1], or by the 32K_OUT output pin provided by these modules), or the SARA-G340 and SARA-G350 modules (except ‘00’ versions), when power saving is disabled: the module is registered with the network, active-mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception.

Figure 13: VCC current consumption profile versus time of the SARA-G300 and SARA-G310 modules (with the EXT32K input pin fed by proper external 32 kHz signal or by 32K_OUT output pin), or SARA-G340 and SARA-G350 modules (except ‘00’ versions), when registered with the network, with power saving disabled: the active-mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel

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ACTIVE MODE

10-18 mA

60-120 mA

2G case: 0.47-2.12 s 3G case: 0.64-5.12 s

Paging period

Time [s]

Current [mA]

100

Time [ms]

Current [mA]

100

10-18 mA

60-120 mA

Enabled

20-40 mA

DSP

Enabled

10-18 mA

Figure 14 roughly describes the current consumption profile of the SARA-G300 and SARA-G310 modules (when their EXT32K input is not fed by a signal, i.e. left unconnected), or the SARA-G340 and SARA-G350 modules (‘00’ versions only), or the SARA-U2 modules, when power saving is disabled: the module is registered with the network, active-mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception.

Figure 14: VCC current consumption profile versus time of the SARA-G300 and SARA-G310 modules (when their EXT32K input is not fed by a signal), or the SARA-G340 and SARA-G350 modules (‘00’ versions only), or the SARA-U2 modules, when registered with the network, with power saving disabled: the active-mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel

For detailed current consumption values with the module registered with 2G or 3G network with power saving disabled (fixed active-mode) see the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2].

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Baseband Processor

VCC

V_BCKP

Linear

LDO

RTC

Power

Management

SARA-G340 / SARA-G350

SARA-U2 series

32 kHz

Baseband

Processor

VCC

V_BCKP

Linear

LDO

RTC

Power

Management

SARA-G300 / SARA-G310

32 kHz

EXT32K

1.5.2 RTC supply input/output (V_BCKP)

The V_BCKP pin of SARA-G3 and SARA-U2 series modules connects the supply for the Real Time Clock (RTC) and Power-On internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 15. The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range, with the module switched off or switched on.

Figure 15: RTC supply input/output (V_BCKP) and 32 kHz RTC timing reference clock simplified block diagram

The RTC provides the module time reference (date and time) that is used to set the wake-up interval during the idle-mode periods between network paging, and is able to make available the programmable alarm functions.

The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid range (specified in the “Input characteristics of Supply/Power pins” table in the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2]) and, for SARA-G300 / SARA-G310 modules only, when their EXT32K input pin is fed by an external 32.768 kHz signal with proper characteristics (specified in the “EXT32K pin characteristics” table in SARA-G3 series Data Sheet [1]). See the u-blox AT Commands Manual [3] for more details.

The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module.

The RTC oscillator does not necessarily stop operation (i.e. the RTC counting does not necessarily stop) when V_BCKP voltage value drops below the specified operating range minimum limit (1.00 V): the RTC value read after a system restart could be not reliable, as explained in Table 8.

V_BCKP voltage value RTC value reliability Notes

1.00 V < V_BCKP < 2.40 V RTC oscillator does not stop operation RTC value read after a restart of the system is reliable

0.05 V < V_BCKP < 1.00 V RTC oscillator does not necessarily stop operation RTC value read after a restart of the system is not reliable

0.00 V < V_BCKP < 0.05 V RTC oscillator stops operation RTC value read after a restart of the system is reliable

V_BCKP within operating range

V_BCKP below operating range

Table 8: RTC value reliability as function of V_BCKP voltage value

Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).

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Baseband

Processor

VCC

V_INT

Switching

Step-Down

Digital I/O

Interfaces

Power

Management

SARA-G3 / SARA

-U2 series

The RTC has very low power consumption, but is highly temperature dependent. For example at 25 °C, with the V_BCKP voltage equal to the typical output value, the current consumption is approximately 2 µA (see the “Input characteristics of Supply/Power pins” table in the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2] for the detailed specification), whereas at 70 °C and an equal voltage the current consumption increases to 5-10 µA.

If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). This has no impact on cellular connectivity, as all the module functionalities do not rely on date and time setting.

1.5.3 Generic digital interfaces supply output (V_INT)

The same 1.8 V voltage domain used internally to supply the generic digital interfaces of SARA-G3 and SARA-U2 series modules is also available on the V_INT supply output pin, as described in Figure 16.

Figure 16: SARA-G3 and SARA-U2 series interfaces supply output (V_INT) simplified block diagram

The internal regulator that generates the V_INT supply is a switching step-down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and it is disabled when the module is switched off.

The switching regulator operates in Pulse Width Modulation (PWM) for greater efficiency at high output loads when the module is in active-mode or in connected-mode. When the module is in low power idle-mode between paging periods and with power saving configuration enabled by the appropriate AT command, it automatically switches to Pulse Frequency Modulation (PFM) for greater efficiency at low output loads. See the u-blox AT Commands Manual [3], +UPSV command.

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Baseband

Processor

PWR_ON

SARA-G3 / SARA-U2 series

Power-on

Power

Management

Power-on

1.6 System function interfaces

1.6.1 Module power-on

1.6.1.1 Switch-on events

Table 9 summarizes the possible switch-on events for the SARA-G3 and SARA-U2 series modules.

SARA-G3 SARA-U2

From Not-Powered Mode

From Power-Off Mode

Table 9: Summary of SARA-G3 and SARA-U2 modules’ switch-on events

Applying valid VCC supply voltage (i.e. VCC rise edge), ramping from 2.5 V to 3.2 V within 4 ms

Low level on PWR_ON pin for 5 ms min. Low pulse on PWR_ON pin for 50 µs min. / 80 µs max.

RTC alarm programmed by AT+CALA command (Not supported by SARA-G300 / SARA-G310)

RESET_N pin released from low level

Applying valid VCC supply voltage (i.e. VCC rise edge), ramping from 2.5 V to 3.2 V within 1 ms

RTC alarm programmed by AT+CALA command

When the SARA-G3 and SARA-U2 series modules are in the not-powered mode (i.e. switched off with the VCC module supply not applied), they can be switched on by:

• Rising edge on the VCC supply input to a valid voltage for modules supply: the modules switch on applying

VCC supply starting from a voltage value lower than 2.25 V, providing a fast VCC voltage slope, as it must ramp from 2.5 V to 3.2 V within 4 ms on SARA-G3 modules and within 1 ms on SARA-U2 modules, and reaching a proper nominal VCC voltage value within the normal operating range.

• Alternately, the RESET_N pin can be held low during the VCC rising edge, so that the module switches on

by releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal range.

The status of the PWR_ON input pin of SARA-G3 and SARA-U2 series modules while applying the VCC module supply is not relevant: during this phase the PWR_ON pin can be set high or low by the external circuit.

When the SARA-G3 and SARA-U2 series modules are in the power-off mode (i.e. switched off by means of the AT+CPWROFF command, with valid VCC module supply applied), they can be switched on by:

• Low level / pulse on PWR_ON pin, which is normally set high by an external pull-up, for a valid time period.

As described in Figure 17, there is no internal pull-up resistor on the PWR_ON pin of the modules: the pin has high input impedance and is weakly pulled high by the internal circuit. Therefore the external circuit must be able to hold the high logic level stable, e.g. providing an external pull-up resistor (for design-in see section 2.3.1).

The PWR_ON input voltage thresholds are different from the other generic digital interfaces of the modules: refer to SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2] for detailed electrical characteristics.

Figure 17: PWR_ON input description

The SARA-G340, SARA-G350 and SARA-U2 series can be also switched on from power-off mode by:

• RTC alarm pre-programmed by AT+CALA command at specific time (see u-blox AT Commands Manual [3]).

The SARA-U2 series modules can be also switched on from power-off mode by:

• Low pulse on the RESET_N pin, which is normally set high by an internal pull-up (refer to section 1.6.3 and

to the SARA-U2 series Data Sheet [2] for the description of the RESET_N input electrical characteristics).

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VCC

V_BCKP

PWR_ON

SARA-U2 RESET_N

V_INT

SARA-G3 RESET_N

Internal Reset

System State

Digital Pins State

Internal Reset

→ Operational

Operational

Tristate / Floating

OFF

Internal Reset

Sta rt of interfa ce

configuration

Module interfaces

are configured

Sta rt-up

event

1.6.1.2 Switch-on sequence from not-powered mode

Figure 18 shows the modules power-on sequence from the not-powered mode, describing the following phases:

• The external supply is applied to the VCC module supply inputs, representing the start-up event.

• The status of the PWR_ON input pin while applying the VCC module supply is not relevant: during this

phase the PWR_ON pin can be set high or low by the external circuit, but in Figure 18 it is assumed that the PWR_ON line rise suddenly to high logic level due to external pull-up connected to V_BCKP or VCC.

• The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value.

• The RESET_N line of SARA-U2 series rise suddenly to high logic level due to internal pull-up to V_BCKP.

• All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (V_INT):

any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a proper boot of the module.

• The V_INT generic digital interfaces supply output is enabled by the integrated power management unit.

• The RESET_N line of SARA-G3 series rise suddenly to high logic level due to internal pull-up to V_INT.

• The internal reset signal is held low by the integrated power management unit: the baseband processor core

and all the digital pins of the modules are held in reset state.

• When the internal reset signal is released by the integrated power management unit, the processor core

starts to configure the digital pins of the modules to each default operational state.

• The duration of this pins’ configuration phase differs within generic digital interfaces (3 s typical) and the

USB interface due to specific host / device enumeration timings (5 s typical, see section 1.9.3). The host application processor should not send any AT command over the AT interfaces (USB, UART) of the modules until the end of this interfaces’ configuration phase to allow a proper boot of the module.

• After the interfaces’ configuration phase, the application can start sending AT commands, and the following

starting procedure is suggested to check the effective completion of the module internal boot sequence: send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the

VCC supply of the module, and then run the application

Figure 18: SARA-G3 and SARA-U2 series power-on sequence from not-powered mode

The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage

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to sense the start of the power-on sequence.

driven by an external application should be applied to any generic digital interface of the modules.

SARA-G3 and SARA-U2 series - System Integration Manual

VCC

V_BCKP

PWR_ON

SARA-U2 RESET_N

V_INT

SARA-G3 RESET_N

Internal Reset

System State

Digital Pins State

Internal Reset → Operational Operational

Tristate / Floating

OFF

Internal Reset

Sta rt of interfa ce

configuration

Module interfaces

are configured

Sta rt-up

event

1.6.1.3 Switch-on sequence from power-off mode

Figure 19 shows the modules power-on sequence from the power-off mode, describing the following phases:

• The external supply is still applied to the VCC inputs as it is assumed that the module has been previously

switched off by means of the AT+CPWROFF command: the V_BCKP output is internally enabled as proper VCC is present, the RESET_N of SARA-U2 series is set to high logic level due to internal pull-up to V_BCKP, the PWR_ON is set to high logic level due to external pull-up connected to V_BCKP or VCC.

• The PWR_ON input pin is set low for a valid time period, representing the start-up event.