Ublox SARA-R4 Series, SARA-N4 Series, SARA-R404M, SARA-R410M, SARA-N410 System Integration Manual

Abstract

This document describes the features and the integration of the size-optimized SARA-R4/N4 series cellular

modules. These modules are a complete, cost efficient, performance optimized, multi-mode and multi

band LTE Cat M1 / NB1 and EGPRS solution in the compact SARA form factor.

www.u-blox.com

UBX-16029218 - R11

SARA-R4/N4

SARA-R4/N4 series

System Integration Manual

System Integration Manual

SARA-R4/N4 series - System Integration Manual

Title

SARA-R4/N4 series

Subtitle

System Integration Manual

Document type

System Integration Manual

Document number

UBX-16029218

Revision and date

R11

20-Feb-2019

Disclosure Restriction

Product status

Corresponding content status

Functional Sample

Draft

For functional testing. Revised and supplementary data will be published later.

In Development /
Prototype

Objective Specification

Target values. Revised and supplementary data will be published later.

Engineering Sample

Advance Information

Data based on early testing. Revised and supplementary data will be published later.

Initial Production

Early Production Information

Data from product verification. Revised and supplementary data may be published later.

Mass Production /
End of Life

Production Information

Document contains the final product specification.

Product name

Type number

Modem version

Application version

PCN reference

Product status

SARA-R404M

SARA-R404M-00B-00

K0.0.00.00.07.06

UBX-17047084

End of Life

SARA-R404M-00B-01

K0.0.00.00.07.08

UBX-18053670

Initial Production

SARA-R410M

SARA-R410M-01B-00

L0.0.00.00.02.03

UBX-17051617

Initial Production

SARA-R410M-02B-00

L0.0.00.00.05.06

A02.00

UBX-18010263

Initial Production

SARA-R410M-52B-00

L0.0.00.00.06.05

A02.06

UBX-18045915

Initial Production

SARA-R412M

SARA-R412M-02B-00

M0.09.00

A02.11

UBX-19004091

Initial Production

SARA-N410

SARA-N410-02B-00

L0.0.00.00.07.07

A02.09

UBX-18057459

Initial Production

u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document.

Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the

express written permission of u-blox.

The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or

implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular

purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents,

visit www.u-blox.com.

Copyright © u-blox AG.

Document Information

This document applies to the following products:

UBX-16029218 - R11 Page 2 of 157

SARA-R4/N4 series - System Integration Manual

Contents

Document Information ............................................................................................................................ 2

Contents...................................................................................................................................................... 3

1 System description ............................................................................................................................ 7

1.1 Overview ........................................................................................................................................................................................... 7

1.2 Architecture ................................................................................................................................................................................... 11

1.3 Pin-out ............................................................................................................................................................................................. 12

1.4 Operating modes ....................................................................................................................................................................... 17

1.5 Supply interfaces ........................................................................................................................................................................ 21

1.5.1 Module supply input (VCC) ......................................................................................................................................... 21

1.5.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 28

1.6 System function interfaces ..................................................................................................................................................... 30

1.6.1 Module power-on ............................................................................................................................................................ 30

1.6.2 Module power-off ............................................................................................................................................................ 31

1.6.3 Module reset ...................................................................................................................................................................... 33

1.7 Antenna interface ....................................................................................................................................................................... 35

1.7.1 Antenna RF interface (ANT) ......................................................................................................................................... 35

1.7.2 Antenna detection interface (ANT_DET) ................................................................................................................ 36

1.8 SIM interface................................................................................................................................................................................. 36

1.8.1 SIM interface ...................................................................................................................................................................... 36

1.8.2 SIM detection interface ................................................................................................................................................. 37

1.9 Data communication interfaces ........................................................................................................................................... 38

1.9.1 UART interface ................................................................................................................................................................... 38

1.9.2 USB interface ...................................................................................................................................................................... 40

1.9.3 SPI interface ........................................................................................................................................................................ 42

1.9.4 SDIO interface .................................................................................................................................................................... 42

1.9.5 DDC (I2C) interface........................................................................................................................................................... 42

1.10 Audio ................................................................................................................................................................................................ 42

1.11 General Purpose Input/Output ............................................................................................................................................ 44

1.12 Reserved pins (RSVD) ............................................................................................................................................................... 44

1.13 System features ........................................................................................................................................................................... 45

UBX-16029218 - R11 Page 3 of 157

SARA-R4/N4 series - System Integration Manual

1.13.1 Network indication .......................................................................................................................................................... 45

1.13.2 Antenna supervisor.......................................................................................................................................................... 45

1.13.3 Dual stack IPv4/IPv6........................................................................................................................................................ 45

1.13.4 TCP/IP and UDP/IP .......................................................................................................................................................... 45

1.13.5 FTP ........................................................................................................................................................................................... 45

1.13.6 HTTP ....................................................................................................................................................................................... 46

1.13.7 Firmware update Over AT (FOAT) ............................................................................................................................ 46

1.13.8 Firmware update Over The Air (uFOTA) ................................................................................................................ 46

1.13.9 Power saving ...................................................................................................................................................................... 47

2 Design-in ........................................................................................................................................... 51

2.1 Overview ......................................................................................................................................................................................... 51

2.2 Supply interfaces ........................................................................................................................................................................ 53

2.2.1 Module supply (VCC) ..................................................................................................................................................... 53

2.2.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 75

2.3 System functions interfaces ................................................................................................................................................... 76

2.3.1 Module power-on (PWR_ON)..................................................................................................................................... 76

2.3.2 Module reset (RESET_N) ................................................................................................................................................ 78

2.4 Antenna interface ....................................................................................................................................................................... 79

2.4.1 Antenna RF interface (ANT) ......................................................................................................................................... 79

2.4.2 Antenna detection interface (ANT_DET) ................................................................................................................ 88

2.5 SIM interface................................................................................................................................................................................. 92

2.5.1 Guidelines for SIM circuit design ............................................................................................................................. 92

2.5.2 Guidelines for SIM layout design ............................................................................................................................. 97

2.6 Data communication interfaces ........................................................................................................................................... 98

2.6.1 UART interface ................................................................................................................................................................... 98

2.6.2 USB interface ................................................................................................................................................................... 105

2.6.3 SPI interface ..................................................................................................................................................................... 107

2.6.4 SDIO interface ................................................................................................................................................................. 107

2.6.5 DDC (I2C) interface........................................................................................................................................................ 107

2.7 Audio ............................................................................................................................................................................................. 111

2.7.1 Guidelines for Audio circuit design ...................................................................................................................... 111

2.8 General Purpose Input/Output ......................................................................................................................................... 111

2.8.1 Guidelines for GPIO circuit design ........................................................................................................................ 111

UBX-16029218 - R11 Page 4 of 157

SARA-R4/N4 series - System Integration Manual

2.8.2 Guidelines for general purpose input/output layout design ................................................................... 112

2.9 Reserved pins (RSVD) ............................................................................................................................................................ 113

2.10 Module placement .................................................................................................................................................................. 113

2.11 Module footprint and paste mask .................................................................................................................................. 114

2.12 Thermal guidelines ................................................................................................................................................................. 115

2.13 Schematic for SARA-R4/N4 series module integration ......................................................................................... 116

2.13.1 Schematic for SARA-R4/N4 series modules ..................................................................................................... 116

2.14 Design-in checklist .................................................................................................................................................................. 118

2.14.1 Schematic checklist ...................................................................................................................................................... 118

2.14.2 Layout checklist .............................................................................................................................................................. 118

2.14.3 Antenna checklist .......................................................................................................................................................... 119

3 Handling and soldering ................................................................................................................ 120

3.1 Packaging, shipping, storage and moisture preconditioning ............................................................................. 120

3.2 Handling ...................................................................................................................................................................................... 120

3.3 Soldering ..................................................................................................................................................................................... 122

3.3.1 Soldering paste .............................................................................................................................................................. 122

3.3.2 Reflow soldering ............................................................................................................................................................ 122

3.3.3 Optical inspection ......................................................................................................................................................... 124

3.3.4 Cleaning ............................................................................................................................................................................. 124

3.3.5 Repeated reflow soldering ........................................................................................................................................ 124

3.3.6 Wave soldering .............................................................................................................................................................. 124

3.3.7 Hand soldering ............................................................................................................................................................... 125

3.3.8 Rework ................................................................................................................................................................................ 125

3.3.9 Conformal coating ........................................................................................................................................................ 125

3.3.10 Casting................................................................................................................................................................................ 125

3.3.11 Grounding metal covers ............................................................................................................................................ 125

3.3.12 Use of ultrasonic processes ...................................................................................................................................... 126

4 Approvals......................................................................................................................................... 127

4.1 Product certification approval overview ....................................................................................................................... 127

4.2 US Federal Communications Commission notice .................................................................................................... 130

4.2.1 Safety warnings review the structure .................................................................................................................. 130

4.2.2 Declaration of Conformity ........................................................................................................................................ 130

UBX-16029218 - R11 Page 5 of 157

SARA-R4/N4 series - System Integration Manual

4.2.3 Modifications ................................................................................................................................................................... 131

4.3 Innovation, Science, Economic Development Canada notice ............................................................................ 132

4.3.1 Declaration of Conformity ........................................................................................................................................ 132

4.3.2 Modifications ................................................................................................................................................................... 133

4.4 European Conformance CE mark ..................................................................................................................................... 136

4.5 Taiwanese National Communication Commission .................................................................................................. 137

5 Product testing ............................................................................................................................... 138

5.1 u-blox in-series production test ....................................................................................................................................... 138

5.2 Test parameters for OEM manufacturers ..................................................................................................................... 139

5.2.1 “Go/No go” tests for integrated devices ........................................................................................................... 139

5.2.2 RF functional tests ........................................................................................................................................................ 140

Appendix ................................................................................................................................................ 142

A Migration between SARA modules ............................................................................................ 142

A.1 Overview ...................................................................................................................................................................................... 142

A.2 Pin-out comparison ................................................................................................................................................................ 144

B Glossary ........................................................................................................................................... 151

Related documents ............................................................................................................................... 154

Revision history ..................................................................................................................................... 155

Contact .................................................................................................................................................... 156

UBX-16029218 - R11 Page 6 of 157

SARA-R4/N4 series - System Integration Manual

Model

Region

Bands

Positioning

Interfaces

Audio

Features

Grade

-band

®

2

C)

(FOTA)

SARA-R404M

USA

13

M1

13

●

●

●

●

● ● ● ● ● ●

SARA-R410M-01B

North America

13

M1

2,4

5,12

●

●

●

●

● ● ● ● ● ●

SARA-R410M-02B

Multi Region

13

M1

NB1

*

● ● ○ ● ● ○ ○ ● ● ○ ● ● ● ● ● ●

● ●

SARA-R410M-52B

North America

13

M1

2,4,5

12,13

● ● ○ ● ● ○ ○ ● ●

● ● ● ● ● ● ● ●

1 System description

1.1 Overview

The SARA-R4/N4 series comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode modules in the miniature

SARA LGA form-factor (26.0 x 16.0 mm, 96-pin), that allow easy integration in compact designs and a

seamless drop-in migration from u-blox cellular module families.

SARA-R4/N4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module

families and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families.

This facilitates migration from u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules,

maximizes customer investments, simplifies logistics, and enables very short time-to-market. See Table 1

for a summary of the main features and interfaces.

The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices

that require long battery lifetimes, such as connected health, smart metering, smart cities and wearables.

The modules support handover capability and delivers the technology necessary for use in applications such

as vehicle, asset and people tracking where mobility is a pre-requisite. Other applications where the modules

are well-suited include and are not limited to: smart home, security systems, industrial monitoring and

control.

The modules support data communication over an extended operating temperature range of –40 to +85

°C, with extremely low power consumption, and with coverage enhancement for deeper range into buildings

and basements (and underground with NB1).

UBX-16029218 - R11 System description Page 7 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R412M-02B

Multi Region

13

M1

NB1

*

● ● ● ○ ● ● ○ ○ ●

●

● ● ● ● ● ● ● ●

SARA-N410-02B

Multi Region

13

NB1 *

● ● ○ ● ● ○ ○ ● ●

● ● ● ● ● ● ● ●

* = LTE Cat M1/NB1 Bands may include 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only)

● = supported by all FW versions

○ = supported by future FW versions

Item

SARA-R404M

SARA-R410M

SARA-R412M

SARA-N410

Protocol stack

3GPP Release 13

3GPP Release 13

3GPP Release 13

3GPP Release 13

RAT

LTE Cat M1 Half-Duplex

LTE Cat M1 Half-Duplex

LTE Cat NB1 Half-Duplex 1

LTE Cat M1 Half-Duplex

LTE Cat NB1 Half-Duplex

2G GPRS / EGPRS

LTE Cat NB1 Half-Duplex

1

Table 1: SARA-R4/N4 series main features summary

SARA-R4/N4 series modules include the following variants / product versions:
 SARA-R404M LTE Cat M1 module,

mainly designed for operation in LTE band 13

 SARA-R410M-01B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12

 SARA-R410M-02B LTE Cat M1 / NB1 module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28

 SARA-R410M-52B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12, 13

 SARA-R412M-02B LTE Cat M1 / NB1 and 2G module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad-band

 SARA-N410-02B LTE Cat NB1 module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 28

Table 2 summarizes cellular radio access technologies characteristics and features of the modules.

Not supported by the “01” product version.

UBX-16029218 - R11 System description Page 8 of 157

SARA-R4/N4 series - System Integration Manual

Item

SARA-R404M

SARA-R410M

SARA-R412M

SARA-N410

LTE FDD bands

Band 13 (750 MHz)

Band 12 (700 MHz)

Band 17 (700 MHz)

1, 2, 3

Band 28 (700 MHz) 1

Band 13 (750 MHz) 1

Band 20 (800 MHz) 1

Band 26 (850 MHz)

1, 2

Band 18 (850 MHz)

1, 2

Band 5 (850 MHz)

Band 19 (850 MHz)

1, 2

Band 8 (900 MHz) 1

Band 4 (1700 MHz)

Band 3 (1800 MHz) 1

Band 2 (1900 MHz)

Band 25 (1900 MHz)

1, 2, 3

Band 1 (2100 MHz) 1

Band 12 (700 MHz)

Band 13 (750 MHz)

Band 20 (800 MHz)

Band 5 (850 MHz)

Band 8 (900 MHz)

Band 4 (1700 MHz)

Band 3 (1800 MHz)

Band 2 (1900 MHz)

Band 12 (700 MHz)

Band 28 (700 MHz)

Band 13 (750 MHz)

Band 20 (800 MHz)

Band 5 (850 MHz)

Band 8 (900 MHz)

Band 4 (1700 MHz)

Band 3 (1800 MHz)

Band 2 (1900 MHz)

LTE TDD bands

Band 39 (1900 MHz)

3, 4

2G bands

GSM 850 MHz

E-GSM 900 MHz

DCS 1800 MHz

PCS 1900 MHz

Power class

LTE Cat M1:

Class 3 (23 dBm)

LTE Cat M1 / NB15:

Class 3 (23 dBm)

LTE category M1 / NB1:

Class 3 (23 dBm)

2G GMSK:

Class 4 (33 dBm) for

GSM/E-GSM bands

Class 1 (30 dBm) for

DCS/PCS bands

2G 8-PSK:

Class E2 (27 dBm) for

GSM/E-GSM bands

Class E2 (26 dBm) for

DCS/PCS bands

LTE category NB1:

Class 3 (23 dBm)

2

3

4

5

Not supported by the “52” product version.

Not supported in signaling mode by the “02” product version

Not supported in LTE category NB1. Not supported by the “01” and “52” product versions.

Not supported by the “01” product version.

UBX-16029218 - R11 System description Page 9 of 157

SARA-R4/N4 series - System Integration Manual

Item

SARA-R404M

SARA-R410M

SARA-R412M

SARA-N410

Data rate

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category NB15:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category NB1:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

GPRS multi-slot class 336:

Up to 85.6 kb/s UL

Up to 107 kb/s DL

EGPRS multi-slot class 336:

Up to 236.8 kb/s UL

Up to 296.0 kb/s DL

LTE category NB1:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

6

Table 2: SARA-R4/N4 series modules LTE Cat M1, LTE Cat NB1, EGPRS and GPRS characteristics summary

GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total.

UBX-16029218 - R11 System description Page 10 of 157

SARA-R4/N4 series - System Integration Manual

Memory

V_INT

RF

transceiver

Cellular
BaseBand
Processor

ANT

VCC (Supply)

USB
DDC (I2C)

SIM card det ection

SIM

UART

Power-On

Reset

GPIOs

Antenna detect ion

Switch

PA

19.2 MHz

Power

Management

Filter

SDIO
SPI / Digit al Audio

1.2 Architecture

Figure 1 summarizes the internal architecture of SARA-R4/N4 series modules.

☞ SARA-R404M-00B and SARA-R410M-01B modules, i.e. the “00” and “01” product versions of the

☞ SARA-R410M-02B, SARA-R410M-52B, SARA-R412M-02B and SARA-N410-02B modules, i.e. the “02” and

Figure 1: SARA-R4/N4 series modules simplified block diagram

SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected

and should not be driven by external devices:
o DDC (I

2

C) interface

o SDIO interface
o SPI interface
o Digital audio interface

“52” product versions of the SARA-R4/N4 series modules, do not support the following interfaces, which

should be left unconnected and should not be driven by external devices:

o SDIO interface
o SPI interface
o Digital audio interface

UBX-16029218 - R11 System description Page 11 of 157

SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

51, 52, 53

I

Module supply

input

VCC supply circuit affects the RF performance and compliance

of the device integrating the module with applicable required

certification schemes.

See section 1.5.1 for functional description / requirements.

See section 2.2.1 for external circuit design-in.

GND

1, 3, 5, 14,

20-22, 30,

32, 43, 50,

54, 55, 57-

61, 63-96

N/A

Ground

GND pins are internally connected each other.

External ground connection affects the RF and thermal

performance of the device.

See section 1.5.1for functional description.

See section 2.2.1 for external circuit design-in.

V_INT

4 O Generic digital

interfaces supply

output

V_INT = 1.8 V (typical) generated by internal regulator when

the module is switched on, outside the low power PSM deep

sleep mode.

Test-Point for diagnostic access is recommended.

See section 1.5.2 for functional description.

See section 2.2.2 for external circuit design-in.

System

PWR_ON

15 I Power-on input

Internal 200 k pull-up resistor.

Test-Point for diagnostic access is recommended.

See section 1.6.1 for functional description.

See section 2.3.1 for external circuit design-in.

RESET_N

18 I External reset input

Internal 37 k pull-up resistor.

Test-Point for diagnostic access is recommended.

See section 1.6.3 for functional description.

See section 2.3.2 for external circuit design-in.

Antenna

ANT

56

I/O

Primary antenna

Main Tx / Rx antenna interface.

50  nominal characteristic impedance.

Antenna circuit affects the RF performance and application

device compliance with required certification schemes.

See section 1.7 for functional description / requirements.

See section 2.4 for external circuit design-in.

ANT_DET

62 I Antenna detection

ADC for antenna presence detection function

See section 1.7.2 for functional description.

See section 2.4.2 for external circuit design-in.

SIM

VSIM

41 O SIM supply output

VSIM = 1.8 V / 3 V output as per the connected SIM type.

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

1.3 Pin-out

Table 3 lists the pin-out of the SARA-R4/N4 series modules, with pins grouped by function.

UBX-16029218 - R11 System description Page 12 of 157

SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

I/O

Description

Remarks

SIM_IO

39

I/O

SIM data

Data input/output for 1.8 V / 3 V SIM

Internal 4.7 k pull-up to VSIM.

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_CLK

38 O SIM clock

4.8 MHz clock output for 1.8 V / 3 V SIM

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_RST

40 O SIM reset

Reset output for 1.8 V / 3 V SIM

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

UART

RXD

13 O UART data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24,

for AT commands, data communication, FOAT.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

TXD

12 I UART data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24,

for AT commands, data communication, FOAT.

Internal pull-down to GND on “00” and R410M-02B versions

Internal pull-up to V_INT on other product versions

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

CTS

11 O UART clear to send

output

1.8 V output, Circuit 106 (CTS) in ITU-T V.24.

Not supported by ‘00’, ‘01’ and R410M-02B versions.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

RTS

10 I UART ready to send

input

1.8 V input, Circuit 105 (RTS) in ITU-T V.24.

Internal active pull-up to V_INT.

Not supported by ‘00’, ‘01’ and R410M-02B versions.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DSR 6 O

UART data set

ready output

1.8 V, Circuit 107 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

RI 7 O

UART ring indicator

output

1.8 V, Circuit 125 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DTR 9 I

UART data terminal

ready input

1.8 V, Circuit 108/2 in ITU-T V.24.

Internal active pull-up to V_INT.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DCD 8 O

UART data carrier

detect output

1.8 V, Circuit 109 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

UBX-16029218 - R11 System description Page 13 of 157

SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

I/O

Description

Remarks

USB

VUSB_DET

17 I USB detect input

VBUS (5 V typical) USB supply generated by the host must be

connected to this input pin to enable the USB interface.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

USB_D-

28

I/O

USB Data Line D-

USB interface for AT commands, data communication, FOAT,

FW update by u-blox tool, diagnostics.

90  nominal differential impedance (Z0)
30  nominal common mode impedance (ZCM)

Pull-up or pull-down resistors and external series resistors as

required by the USB 2.0 specifications [4] are part of the USB

pin driver and need not be provided externally.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

USB_D+

29

I/O

USB Data Line D+

USB interface for AT commands, data communication, FOAT,

FW update by u-blox tool, diagnostics.

90  nominal differential impedance (Z0)
30  nominal common mode impedance (ZCM)

Pull-up or pull-down resistors and external series resistors as

required by the USB 2.0 specifications [4] are part of the USB

pin driver and need not be provided externally.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

SPI

I2S_WA /

SPI_MOSI

34 O SPI MOSI

SPI Master Output Slave Input, alternatively configurable as I2S

word alignment

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

I2S_RXD /

SPI_MISO

37 I SPI MISO

SPI Master Input Slave Output, alternatively configurable as I2S

receive data

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

I2S_CLK /

SPI_CLK

36 O SPI clock

SPI clock, alternatively configurable as I2S clock

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

I2S_TXD /

SPI_CS

35 O SPI Chip Select

SPI Chip Select, alternatively settable as I2S transmit data

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

UBX-16029218 - R11 System description Page 14 of 157

SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

I/O

Description

Remarks

SDIO

SDIO_D0

47

I/O

SDIO serial data [0]

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_D1

49

I/O

SDIO serial data [1]

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_D2

44

I/O

SDIO serial data [2]

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_D3

48

I/O

SDIO serial data [3]

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_CLK

45 O SDIO serial clock

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_CMD

46

I/O

SDIO command

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

DDC

SCL

27 O I2C bus clock line

1.8 V open drain, for communication with I2C-slave devices.

Internal pull-up to V_INT: external pull-up is not required.

Not supported by “00” and “01” product versions.

See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDA

26

I/O

I2C bus data line

1.8 V open drain, for communication with I2C-slave devices.

Internal pull-up to V_INT: external pull-up is not required.

Not supported by “00” and “01” product versions.

See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

Audio

I2S_TXD /

SPI_CS

35 O I2S transmit data

I2S transmit data, alternatively configurable as SPI Chip Select

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

I2S_RXD /

SPI_MISO

37

I

I2S receive data

I2S receive data, alternatively configurable as SPI Master Input

Slave Output

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

I2S_CLK /

SPI_CLK

36

I/O

I2S clock

I2S clock, alternatively configurable as SPI clock

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

UBX-16029218 - R11 System description Page 15 of 157

SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

I/O

Description

Remarks

I2S_WA /

SPI_MOSI

34

I/O

I2S word alignment

I2S word alignment, alternatively configurable as

SPI Master Output Slave Input

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

GPIO

GPIO1

16

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

GPIO2

23

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

GPIO3

24

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

GPIO4

25

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

GPIO5

42

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

GPIO6

19

I/O

GPIO

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

Reserved

RSVD

33

N/A

Reserved pin

This pin can be connected to GND.

See sections 1.12 and 2.9

RSVD

2, 31

N/A

Reserved pin

Leave unconnected.

See sections 1.12 and 2.9

Table 3: SARA-R4/N4 series modules pin definition, grouped by function

UBX-16029218 - R11 System description Page 16 of 157

SARA-R4/N4 series - System Integration Manual

General Status

Operating Mode

Definition

Power-down

Not-Powered Mode

VCC supply not present or below operating range: module is switched off.

Power-Off Mode

VCC supply within operating range and module is switched off.

Normal Operation

Deep-Sleep Mode

RTC runs with 32 kHz reference internally generated.

Idle Mode

Module processor runs with 32 kHz reference generated by the internal oscillator.

Active Mode

Module processor runs with 19.2 MHz reference generated by the internal oscillator.

Connected Mode

RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.

Mode

Description

Transition between operating modes

Not-Powered

Module is switched off.

Application interfaces are not accessible.

When VCC supply is removed, the modules enter not-powered

mode.

When in not-powered mode, the module can enter power-off mode

applying VCC supply (see 1.6.1).

Power-Off

Module is switched off: normal shutdown by

an appropriate power-off event (see 1.6.2).

Application interfaces are not accessible.

The modules enter power-off mode from active mode when the

host processor implements a clean switch-off procedure, by sending

the AT+CPWROFF command or by using the PWR_ON pin (see

1.6.2).

When in power-off mode, the modules can be switched on by the

host processor using the PWR_ON input pin (see 1.6.1).

When in power-off mode, the modules enter not-powered mode by

removing VCC supply.

1.4 Operating modes

SARA-R4/N4 series modules have several operating modes. The operating modes are defined in Table 4

and described in detail in Table 5, providing general guidelines for operation.

Table 4: SARA-R4/N4 series modules operating modes definition

UBX-16029218 - R11 System description Page 17 of 157

SARA-R4/N4 series - System Integration Manual

Mode

Description

Transition between operating modes

Deep-Sleep

Only the internal 32 kHz reference is active.

The RF section and the application interfaces

are temporarily disabled and switched off: the

module is temporarily not ready to

communicate with an external device by

means of the application interfaces as

configured to reduce the current consumption.

The module enters the low power deep sleep

mode (entering the Power Saving Mode

defined in 3GPP Rel.13) whenever possible, if

power saving configuration is enabled by

AT+CPSMS command (see the SARA-R4/N4

series AT Commands Manual [2]), reducing

current consumption (see 1.13.9).

Power saving configuration is not enabled by

default; it can be enabled by AT+CPSMS (see

the SARA-R4/N4 series AT Commands Manual

[2]).

The modules automatically switch from the active mode to low

power deep sleep mode whenever possible, upon expiration of the

6 seconds AT inactivity timer, and upon expiration of “Active Timer”,

entering in the Power Saving Mode defined in 3GPP Rel.13, if power

saving configuration is enabled (see 1.13.9 and the SARA-R4/N4

series AT Commands Manual [2], AT+CPSMS command).

When in low power deep sleep mode, the module switches on to

the active mode upon expiration of “Periodic Update Timer”

according to the Power Saving Mode defined in 3GPP Rel.13 (see

1.13.9 and the SARA-R4/N4 series AT Commands Manual [2],

AT+CPSMS command), or it can be switched on to the active mode

by the host processor using the PWR_ON input pin (see section

1.6.1).

Idle

Module is switched on with application

interfaces temporarily disabled: the module is

temporarily not ready to communicate with an

external device by means of the application

interfaces as configured to reduce the current

consumption.

The module enters the low power idle mode

whenever possible, if low power configuration

is enabled by AT+UPSV command (see the

SARA-R4/N4 series AT Commands Manual [2]),

reducing current consumption.

Low power configuration is not enabled by

default; it can be enabled by AT+UPSV (see

the SARA-R4/N4 series AT Commands Manual

[2]).

The modules automatically switch from the active mode to low

power idle mode whenever possible, upon expiration of the 6

seconds AT inactivity timer, if low power configuration is enabled

(see the SARA-R4/N4 series AT Commands Manual [2], AT+UPSV

command).

When in low power idle mode, the module switches to the active

mode upon data reception over UART serial interface. The first

character received in low power idle mode wakes up the system: it

is not recognized as valid communication character, and the

recognition of the subsequent characters is guaranteed only after

the complete system wake-up.

UBX-16029218 - R11 System description Page 18 of 157

SARA-R4/N4 series - System Integration Manual

Mode

Description

Transition between operating modes

Active

Module is switched on with application

interfaces enabled or not suspended: the

module is ready to communicate with an

external device by means of the application

interfaces unless power saving configuration is

enabled by AT+CPSMS (see the SARA-R4/N4

series AT Commands Manual [2]).

The modules enter active mode from power-off mode when the

host processor implements a clean switch-on procedure by using

the PWR_ON pin (see 1.6.1).

The modules enter active mode from low power deep sleep mode

upon expiration of “Periodic Update Timer” (see 1.13.9), or when the

host processor implements a clean switch-on procedure by using

the PWR_ON pin (see 1.6.1).

The modules enter power-off mode from active mode when the

host processor implements a clean switch-off procedure (see 1.6.2).

The modules automatically switch from active to low power deep

sleep mode whenever possible, if power saving is enabled (see

1.13.9).

The module switches from active to connected mode when a RF

Tx/Rx data connection is initiated or when RF Tx/Rx activity is

required due to a connection previously initiated.

The module switches from connected to active mode when a RF

Tx/Rx data connection is terminated or suspended.

Connected

RF Tx/Rx data connection is in progress.

The module is prepared to accept data signals

from an external device.

When a data connection is initiated, the module enters connected

mode from active mode.

Connected mode is suspended if Tx/Rx data is not in progress. In

such cases the module automatically switches from connected to

active mode and then, if power saving configuration is enabled by

the AT+CPSMS command, the module automatically switches to low

power deep sleep mode whenever possible. Vice-versa, the module

wakes up from low power deep sleep mode to active mode and

then connected mode if RF Tx/Rx activity is necessary.

When a data connection is terminated, the module returns to the

active mode.

Table 5: SARA-R4/N4 series modules operating modes description

UBX-16029218 - R11 System description Page 19 of 157

SARA-R4/N4 series - System Integration Manual

If PSM mode is enabled,
if AT Inact ivity Timer and
Active Timer are expired

• Upon expirat ion of the

Periodic Update Timer

• Using PWR_ON pin

Incoming/outgoing data
or ot her dedicated device
net work communication

No RF Tx/Rx in progress,
Communicat ion dropped

Remove VCC

Swit ch ON:

• PWR_ON

Not

powered

Power off

ActiveConnected

Deep

Sleep

Swit ch OFF:

• AT+CPWROFF

• PWR_ON

Apply VCC

If low power mode is enabled,
if AT Inactivity Timer is expired

Idle

Data received over UART

Figure 2 describes the transition between the different operating modes.

Figure 2: SARA-R4/N4 series modules operating modes transitions

UBX-16029218 - R11 System description Page 20 of 157

SARA-R4/N4 series - System Integration Manual

53

VCC

52

VCC

51

VCC

SARA-R404M / SARA-R410M / SARA-N410

Power

Management

Unit

Memory

Baseband
Processor

Transceiver

Power

Amplifier

53

VCC

52

VCC

51

VCC

SARA-R412M

Power

Management

Unit

Memory

Baseband
Processor

Transceiver

Power

Amplifier

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input.

Voltage must be stable, because during operation, the current drawn by the SARA-R4/N4 series modules
through the VCC pins can vary by several orders of magnitude, depending on the operating mode and

state (as described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.6).

It is important that the supply source is able to withstand both the maximum pulse current occurring during

a transmit burst at maximum power level and the average current consumption occurring during Tx / Rx

call at maximum RF power level (see the SARA-R4 Data Sheet [1]).

SARA-R412M modules provide separate supply inputs over the three VCC pins:
 VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most

of the total current drawn of the module when RF transmission is enabled during a call

 VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding

minor part of the total current drawn of the module when RF transmission is enabled during a call

The 3 VCC pins of SARA-R404M, SARA-R410M, SARA-N410 modules are internally connected each other

to both the internal RF Power Amplifier and the internal baseband Power Management Unit.

Figure 3 provides a simplified block diagram of SARA-R4/N4 series modules’ internal VCC supply routing.

Figure 3: Block diagram of SARA-R4/N4 series modules’ internal VCC supply routing

UBX-16029218 - R11 System description Page 21 of 157

SARA-R4/N4 series - System Integration Manual

Item

Requirement

Remark

VCC nominal voltage

Within VCC normal operating range:

SARA-R404M / SARA-R410M / SARA-N410:

3.2 V / 4.2 V

SARA-R412M:

3.2 V / 4.5 V

RF performance is guaranteed when VCC voltage is

inside the normal operating range limits.

RF performance may be affected when VCC voltage is

outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is

inside the extended operating range limits.

VCC voltage during

normal operation

Within VCC extended operating range:

SARA-R404M / SARA-R410M / SARA-N410:

3.0 V / 4.2 V

SARA-R412M:

3.0 V / 4.5 V

VCC voltage must be above the extended operating

range minimum limit to switch-on the module.

The module may switch-off when the VCC voltage drops

below the extended operating range minimum limit.

Operation above VCC extended operating range is not

recommended and may affect device reliability.

VCC average current

Support with adequate margin the highest
averaged VCC current consumption value in

connected mode conditions specified in the SARA-

R4/N4 series Data Sheet [1]

The maximum average current consumption can be

greater than the specified value according to the actual

antenna mismatching, temperature and supply voltage.

Section 1.5.1.2 describes current consumption profiles in

connected mode.

VCC peak current

Support with adequate margin the highest peak
VCC current consumption value in Tx connected

mode conditions specified in the SARA-R4/N4

series Data Sheet [1]

The maximum peak Tx current consumption can be

greater than the specified value according to the actual

antenna mismatching, temperature and supply voltage.

Section 1.5.1.2 describes current consumption profiles in

connected mode.

VCC voltage drop

during Tx slots

Lower than 400 mV

VCC voltage drop directly affects the RF compliance with

applicable certification schemes.

Figure 6 describes VCC voltage drop during 2G Tx slots.

VCC voltage ripple

during Tx

Noise in the supply pins must be minimized

High supply voltage ripple values during RF

transmissions in connected mode directly affect the RF

compliance with the applicable certification schemes.

VCC under/over-shoot

at start/end of Tx slots

Absent or at least minimized

VCC under/over-shoot directly affects the RF compliance

with applicable certification schemes.

Figure 6 describes VCC voltage under/over-shoot.

1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to

correctly design a VCC supply circuit compliant with the requirements listed in Table 6.

⚠ The supply circuit affects the RF compliance of the device integrating SARA-R4/N4 series modules with

applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if

the requirements summarized in the Table 6 are fulfilled.

UBX-16029218 - R11 System description Page 22 of 157

Table 6: Summary of VCC modules supply requirements

SARA-R4/N4 series - System Integration Manual

UBX-16029218 - R11 System description Page 23 of 157

SARA-R4/N4 series - System Integration Manual

Time

[ms]

Current [mA]

0

300

200

100

500

400

Current consumption value

depends on TX power and

act ual antenna load

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Fram e

(10 ms)

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Fram e

(10 ms)

1.5.1.2 VCC current consumption in LTE connected mode

During an LTE connection, the SARA-R4/N4 series modules transmit and receive in half duplex mode.

The current consumption depends on output RF power, which is always regulated by the network (the

current base station) sending power control commands to the module. These power control commands are

logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change

can reach a maximum rate of 2 kHz.

Figure 4 shows an example of SARA-R4/N4 series modules’ current consumption profile versus time in

connected mode: transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-

duplex connected mode.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

Figure 4: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection

1.5.1.3 VCC current consumption in 2G connected mode

When a 2G call is established, the VCC consumption is determined by the current consumption profile

typical of the 2G transmitting and receiving bursts.

The current consumption peak during a transmission slot is strictly dependent on the transmitted power,

which is regulated by the network. The transmitted power in the transmit slot is also the more relevant

factor for determining the average current consumption.

If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands at the maximum RF

power control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can
reach a high peak / pulse (see the SARA-R4/N4 series Data Sheet [1]) for 576.9 µs (width of the transmit

UBX-16029218 - R11 System description Page 24 of 157

SARA-R4/N4 series - System Integration Manual

Time

[ms]

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200 mA

60-120 mA

190 0 mA

Peak current depends

on TX power and

act ual antenna load

GSM frame

4.615 ms

(1 frame = 8 slot s)

1.5

1.0

0.5

0.0

2.0

60-120 mA

10 -40 mA

Time

undershoot

overshoot

ripple

drop

Volt age

3.8 V
(typ)

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

MON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX
slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slot s)

GSM frame

4.615 ms

(1 fram e = 8 slot s)

slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 duty cycle

according to GSM TDMA (Time Division Multiple Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current

consumption figures are much lower than during transmission in the low bands, due to the 3GPP transmitter

output power specifications.

During a 2G call, current consumption is not significantly high while receiving or in monitor bursts, and it

is low in the bursts unused to transmit / receive.

Figure 5 shows an example of the module current consumption profile versus time in 2G single-slot.

Figure 5: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)

Figure 6 illustrates the VCC voltage profile versus time during a 2G single-slot call, according to the related

VCC current consumption profile described in Figure 5.

Figure 6: Description of the VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)

When a GPRS connection is established, more than one slot can be used to transmit and/or more than one

slot can be used to receive. The transmitted power depends on network conditions, which set the peak

UBX-16029218 - R11 System description Page 25 of 157

SARA-R4/N4 series - System Integration Manual

Time

[ms]

RX

slot

unused

slot

TX

slot

TX

slot

TX

slot

TX

slot

MON

slot

unused

slot

RX

slot

unused

slot

TX

slot

TX

slot

TX

slot

TX

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 fram e = 8 slot s)

Current [A]

60-120mA

GSM frame

4.615 ms

(1 fram e = 8 slot s)

1.5

1.0

0.5

0.0

60-120mA

10-40 mA

200m A

Peak current depends

on TX power and

act ual antenna load

1600 mA

current consumption. But according to GPRS specifications, the maximum transmitted RF power is reduced

if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the

case of a GSM call.

If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level,

the consumption can reach a quite a high peak but lower than the one achievable in 2G single-slot mode.

This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity

of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA.

If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower

than in the 850 or 900 MHz band because of the 3GPP Tx power specifications.

Figure 7 illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz bands,

with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.

Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)

In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one

during GPRS connections: the current consumption profile in GPRS multi-slot class 12 connected mode

illustrated in the Figure 7 is representative for the EDGE multi-slot class 12 connected mode as well.

1.5.1.4 VCC current consumption in low power deep sleep mode (PSM enabled)

The power saving mode configuration is by default disabled, but it can be enabled using the AT+CPSMS

command (see the SARA-R4/N4 series AT Commands Manual [2] and section 1.13.9).

When power saving mode is enabled, the module automatically enters the PSM low power deep sleep
mode whenever possible, reducing current consumption down to a steady value in the µA range: only the

RTC runs with internal 32 kHz reference clock frequency.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

☞ Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the RC

UBX-16029218 - R11 System description Page 26 of 157

oscillator, as a consequence, a very low spike in current consumption will be observed.

SARA-R4/N4 series - System Integration Manual

1.5.1.5 VCC current consumption in low power idle mode (low power enabled)

The low power idle mode configuration is by default disabled, but it can be enabled using the AT+UPSV

command (see the SARA-R4/N4 series AT Commands Manual [2]).

When low power idle mode is enabled, the module automatically enters the low power mode whenever

possible, but it must periodically monitor the paging channel of the current base station (paging block

reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled by

the application. When the module monitors the paging channel, it wakes up to the active mode to enable

the reception of the paging block. In between, the module switches to low power mode. This is known as

discontinuous reception (DRX) or extended discontinuous reception (eDRX).

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

UBX-16029218 - R11 System description Page 27 of 157

SARA-R4/N4 series - System Integration Manual

ACTIVE MODE

Paging period

Time [s]

Current [mA]

Time [ms]

Current [mA]

RX

Enabled

0

100

0

100

1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)

The active mode is the state where the module is switched on and ready to communicate with an external

device by means of the application interfaces (as the USB or the UART serial interface). The module

processor core is active, and the 19.2 MHz reference clock frequency is used.

If power saving mode and/or low power mode configurations are disabled, as it is by default (see the SARA-

R4/N4 series AT Commands Manual [2], +CPSMS, +UPSV AT commands for details), the module remains in

active mode. Otherwise, if PSM mode and/or low power mode configurations are enabled, the module

enters PSM mode and/or low power mode whenever possible.

Figure 8 illustrates a typical example of the module current consumption profile when the module is in

active mode. In such case, the module is registered with the network and, while active mode is maintained,

the receiver is periodically activated to monitor the paging channel for paging block reception.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

Figure 8: VCC current consumption profile with power saving disabled and module registered with the network: active mode is
always held and the receiver is periodically activated to monitor the paging channel for paging block reception

1.5.2 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the SARA-R4/N4 series modules is generated by the module internal power

management circuitry when the module is switched on and it is not in the deep sleep power saving mode.

UBX-16029218 - R11 System description Page 28 of 157

SARA-R4/N4 series - System Integration Manual

The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4/N4 series
Data Sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a

reference voltage rail for external components.

UBX-16029218 - R11 System description Page 29 of 157

SARA-R4/N4 series - System Integration Manual

VCC

PWR_ON

RESET_N

V_INT

Internal Rese t

GPIO

System State

BB Pads State Operati onal

OFF

ON

Interna l Re set → Operationa l

Tristate / Floa ting

Interna l Re set

Start of interface

configuration

Module interfaces

are configured

Start-up

event

~4.5 s

0 s

1.6 System function interfaces

1.6.1 Module power-on

When the SARA-R4/N4 series modules are in the not-powered mode (i.e. the VCC module supply is not

applied), they can be switched on as follows:
 Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set

at the PWR_ON input pin for a valid time.

When the SARA-R4/N4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving
Mode (PSM), with a valid VCC supply applied, they can be switched on as follows:

 Low pulse on the PWR_ON pin for a valid time period

The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics

with voltages and timings are described in the SARA-R4/N4 series Data Sheet [1].

Figure 9 shows the module switch-on sequence from the not-powered mode, with following phases:

 The external power supply is applied to the VCC module pins
 The PWR_ON pin is held low for a valid time
 All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).
 The internal reset signal is held low: the baseband core and all digital pins are held in reset state. When

the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to

the default operational configured state. The duration of this phase differs within generic digital

interfaces and USB interface due to host / device enumeration timings.

 The module is fully ready to operate after all interfaces are configured.

Figure 9: SARA-R4/N4 series switch-on sequence description

☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:

o the V_INT pin, to sense the start of the SARA-R4/N4 series module switch-on sequence
o the GPIO pin configured to provide the module operating status indication (see SARA-R4/N4 series

Commands Manual [2], AT+UGPIOC), to sense when the module is ready to operate

UBX-16029218 - R11 System description Page 30 of 157

SARA-R4/N4 series - System Integration Manual

☞ Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage driven

by an external application should be applied to any generic digital interface of the module.

☞ Before the SARA-R4/N4 series module is fully ready to operate, the host application processor should

not send any AT command over AT communication interfaces (USB, UART) of the module.

☞ The duration of the SARA-R4/N4 series modules’ switch-on routine can vary depending on the

application / network settings and the concurrent module activities.

⚠ An abrupt removal of the VCC supply or forcing a low level on the RESET_N input once the boot of

SARA-R4/N4 series modules has been triggered may lead to an unrecoverable faulty state!

1.6.2 Module power-off

SARA-R4/N4 series modules can be cleanly switched off by:

 AT+CPWROFF command (see SARA-R4/N4 series AT Commands Manual [2]).
 Low pulse on the PWR_ON pin for a valid time period (see the SARA-R4/N4 series Data Sheet [1]).

These events listed above trigger the storage of the current parameter settings in the non-volatile memory

of the module, and a clean network detach procedure.

An abrupt under-voltage shutdown occurs on SARA-R4/N4 series modules when the VCC module supply

is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the

module’s non-volatile memory or to perform the clean network detach.

☞ It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series

modules normal operations.

⚠ An abrupt removal of the VCC supply during SARA-R4/N4 series modules normal operations may lead

to an unrecoverable faulty state!

An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on
RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory

and a clean network detach is not performed.

☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level

on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if

reset or shutdown via AT commands fails or if the module does not reply to a specific AT command

after a time period longer than the one defined in SARA-R4/N4 series AT Commands Manual [2].

UBX-16029218 - R11 System description Page 31 of 157

SARA-R4/N4 series - System Integration Manual

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State Operationa l

OFF

Trista te / Floating

ON

Operational → Tristate

AT+CPWROFF

sent to the module

OK

replied by the module

VCC can be

removed

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State

OFF

Trista te / Floating

ON

Operational -> Tristate

Operational

The module starts

the switch-off routine

VCC can be

removed

⚠ Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may

lead to an unrecoverable faulty state!

Figure 10 and Figure 11 describe the SARA-R4/N4 series modules switch-off sequence started by means of

the AT+CPWROFF command and by means of the PWR_ON input pin respectively, allowing storage of

current parameter settings in the module’s non-volatile memory and a clean network detach, with the

following phases:
 When the +CPWROFF AT command is sent, or when a low pulse with appropriate time duration (see

the SARA-R4/N4 series Data Sheet [1]) is applied at the PWR_ON input pin, the module starts the

switch-off routine.

 Then, if the +CPWROFF AT command has been sent, the module replies OK on the AT interface: the

switch-off routine is in progress.

 At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage

regulators are turned off, including the generic digital interfaces supply (V_INT).

 Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying

a low level to PWR_ON), and enters not-powered mode if the VCC supply is removed.

Figure 10: SARA-R4/N4 series modules switch-off sequence by means of AT+CPWROFF command

Figure 11: SARA-R4/N4 series modules switch-off sequence by means of PWR_ON pin

UBX-16029218 - R11 System description Page 32 of 157

SARA-R4/N4 series - System Integration Manual

☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor the

V_INT pin to sense the end of the switch-off sequence.

⚠ VCC supply can be removed only after V_INT goes low: an abrupt removal of the VCC supply during

SARA-R4/N4 series modules normal operations may lead to an unrecoverable faulty state!

☞ The duration of each phase in the SARA-R4/N4 series modules’ switch-off routines can largely vary

depending on the application / network settings and the concurrent module activities.

1.6.3 Module reset

SARA-R4/N4 series modules can be cleanly reset (rebooted) by:
 AT+CFUN command (see the SARA-R4/N4 series AT Commands Manual [2]).

In the case above an “internal” or “software” reset of the module is executed: the current parameter settings

are saved in the module’s non-volatile memory and a clean network detach is performed.

An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on
RESET_N input pin for a valid time period. In this case, the current parameter settings are not saved in the

module’s non-volatile memory and a clean network detach is not performed. Then, the module remains in

power-off mode as long as a switch on event does not occur applying an appropriate low level to the
PWR_ON input.

☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level

on the RESET_N input during modules normal operation: the RESET_N line should be set low only if

reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT

command after a time period longer than the one defined in the SARA-R4/N4 series AT Commands

Manual [2].

⚠ Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may

lead to an unrecoverable faulty state!

The RESET_N input pin is directly connected to the Power Management Unit IC, with an integrated pull-up

to a 1.8 V supply domain, in order to perform an abrupt hardware shutdown when asserted. Detailed

electrical characteristics with voltages and timings are described in the SARA-R4/N4 series Data Sheet [1].

UBX-16029218 - R11 System description Page 33 of 157

18

RESET_N

SARA-R4/N4

Power Management Unit

Reset

Shutdown

1.8V

Figure 12: RESET_N input description

SARA-R4/N4 series - System Integration Manual

UBX-16029218 - R11 System description Page 34 of 157

SARA-R4/N4 series - System Integration Manual

Item

Requirements

Remarks

Impedance

50  nominal characteristic

impedance

The impedance of the antenna RF connection must match the 50 
impedance of the ANT port.

Frequency
Range

See the SARA-R4/N4 series Data

Sheet [1]

The required frequency range of the antenna connected to ANT port

depends on the operating bands of the used cellular module and the

used mobile network.

Return Loss

S11 < -10 dB (VSWR < 2:1)

recommended

S11 < -6 dB (VSWR < 3:1) acceptable

The Return loss or the S11, as the VSWR, refers to the amount of

reflected power, measuring how well the antenna RF connection matches
the 50  characteristic impedance of the ANT port.

The impedance of the antenna termination must match as much as
possible the 50  nominal impedance of the ANT port over the

operating frequency range, reducing as much as possible the amount of

reflected power.

Efficiency

> -1.5 dB ( > 70% ) recommended

> -3.0 dB ( > 50% ) acceptable

The radiation efficiency is the ratio of the radiated power to the power

delivered to antenna input: the efficiency is a measure of how well an

antenna receives or transmits.

The radiation efficiency of the antenna connected to the ANT port needs

to be enough high over the operating frequency range to comply with

the Over-The-Air (OTA) radiated performance requirements, as Total

Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified

by applicable related certification schemes.

1.7 Antenna interface

1.7.1 Antenna RF interface (ANT)

SARA-R4/N4 series modules provide an RF interface for connecting the external antenna. The ANT pin

represents the primary RF input/output for transmission and reception of LTE RF signals.

The ANT pin has a nominal characteristic impedance of 50  and must be connected to the primary Tx /

Rx antenna through a 50  transmission line to allow clear RF transmission and reception.

1.7.1.1 Antenna RF interfaces requirements

Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to

correctly design antennas circuits compliant with these requirements.

⚠ The antenna circuits affect the RF compliance of the device integrating SARA-R4/N4 series modules

with applicable required certification schemes (for more details see section 4). Compliance is guaranteed

if the antenna RF interface requirements summarized in Table 7 are fulfilled.

UBX-16029218 - R11 System description Page 35 of 157

SARA-R4/N4 series - System Integration Manual

Item

Requirements

Remarks

Maximum Gain

According to radiation exposure

limits

The power gain of an antenna is the radiation efficiency multiplied by

the directivity: the gain describes how much power is transmitted in the

direction of peak radiation to that of an isotropic source.

The maximum gain of the antenna connected to ANT port must not

exceed the herein stated value to comply with regulatory agencies

radiation exposure limits. For additional info see sections 4.2.2.

Input Power

> 24 dBm ( > 0.25 W ) for R404M /

R410M / N410

> 33 dBm ( > 2.0 W ) for R412M

The antenna connected to the ANT port must support with adequate

margin the maximum power transmitted by the modules.

Table 7: Summary of Tx/Rx antenna RF interface requirements

1.7.2 Antenna detection interface (ANT_DET)

The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter

(ADC) provided to sense the antenna presence.

The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented

if the application requires it. The antenna detection is forced by the +UANTR AT command. See the SARA-

R4/N4 series AT Commands Manual [2] for more details on this feature.

The ANT_DET pin generates a DC current (for detailed characteristics see the SARA-R4/N4 series Data

Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna

connector provided on the application board to GND. So, the requirements to achieve antenna detection

functionality are the following:

 an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
 an antenna detection circuit must be implemented on the application board

See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna

assembly design-in guidelines.

1.8 SIM interface

1.8.1 SIM interface

SARA-R4/N4 series modules provide high-speed SIM/ME interface including automatic detection and

configuration of the voltage required by the connected SIM card or chip.

Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage switch
from 1.8 V to 3 V are implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output

provides internal short circuit protection to limit start-up current and protect the SIM to short circuits.

UBX-16029218 - R11 System description Page 36 of 157

SARA-R4/N4 series - System Integration Manual

The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection,

according to the values determined by the SIM card or chip.

1.8.2 SIM detection interface

The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence.

The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence

only if cleanly connected to the mechanical switch of a SIM card holder as described in section 2.5:

 Low logic level at GPIO5 input pin is recognized as SIM card not present
 High logic level at GPIO5 input pin is recognized as SIM card present

For more details, see the SARA-R4/N4 series AT Commands Manual [2], +UGPIOC, +CIND and +CMER AT

commands.

UBX-16029218 - R11 System description Page 37 of 157

SARA-R4/N4 series - System Integration Manual

7

7

1.9 Data communication interfaces

SARA-R4/N4 series modules provide the following serial communication interface:
 USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host

application processor (AT commands, data, FW update by means of the FOAT feature), for FW update

by means of the u-blox dedicated tool and for diagnostics. See section 1.9.2.

 SPI interface: Serial Peripheral Interface available for communication with an external compatible device.

See section 1.9.3.

 SDIO interface: Secure Digital Input Output interface available for communication with a compatible

device. See section 1.9.4.

 DDC interface: I

positioning chips or modules and with external I2C devices. See section 1.9.5.

2

C bus compatible interface available for the communication with u-blox GNSS

1.9.1 UART interface

1.9.1.1 UART features

The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the SARA-

R4/N4 series modules, supporting:

 AT command mode
 Data mode and Online command mode
 Multiplexer protocol functionality
 FW upgrades by means of the FOAT feature (see 1.13.7)

7

☞ The UART is available only if the USB is not enabled as AT command / data communication interface:

UART and USB cannot be concurrently used for this purpose.

UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS

compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for

electrical characteristics see the SARA-R4/N4 series Data Sheet [1]), providing:

 data lines (RXD as output, TXD as input)
 hardware flow control lines (CTS as output, RTS as input)
 modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output)

For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [1]

UBX-16029218 - R11 System description Page 38 of 157

SARA-R4/N4 series - System Integration Manual

D0 D1 D2 D3 D4 D5 D6 D7

Start of 1-Byte
transfer

Start Bit
(Always 0)

Possible Start of

next transfer

Stop Bit
(Always 1)

t

bit

= 1/(Baudrate)

Normal Transfer, 8N1

SARA-R4/N4 series modules are designed to operate as cellular modems, i.e. as the data circuit-

terminating equipment (DCE) according to the ITU-T V.24 Recommendation [5]. A host application

processor connected to the module UART interface represents the data terminal equipment (DTE).

☞ UART signal names of the cellular modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD

line represents data transmitted by the DTE (host processor output) and received by the DCE (module

input).

☞ Hardware flow control is not supported by the “00”, “01” and SARA-R410M-02B product versions, but

the RTS input line of the module must be set low (= ON state) to communicate over UART interface

on the “00” and “01” product versions.

☞ DTR input of the module must be set low (= ON state) to have URCs presented over UART interface.

SARA-R4/N4 series modules’ UART interface is by default configured in AT command mode, if the USB

interface is not enabled as AT command / data communication interface (UART and USB cannot be

concurrently used for this purpose): the module waits for AT command instructions and interprets all the

characters received as commands to execute. All the functionalities supported by SARA-R4/N4 series

modules can be in general set and configured by AT commands:

 AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]
 u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2])

The default baud rate is 115200 b/s, while the default frame format is 8N1 (8 data bits, No parity, 1 stop

bit: see Figure 13). Baud rates can be configured by AT command (see the SARA-R4/N4 series AT

Commands Manual [2]).

☞ Automatic baud rate detection and automatic frame format recognition are not supported.

Figure 13: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit)

1.9.1.2 UART signals behavior

At the end of the module boot sequence (see Figure 9), the module is by default in active mode, and the

UART interface is initialized and enabled as AT commands interface only if the USB interface is not enabled

as AT command / data communication interface: UART and USB cannot be concurrently used for this

purpose.

UBX-16029218 - R11 System description Page 39 of 157

SARA-R4/N4 series - System Integration Manual

 Channel 0:

for Multiplexer control

 Channel 1:

for all AT commands, and non-Dial Up Network (non-DUN) data connections. UDP, TCP

data socket / data call connections via relevant AT commands.

 Channel 2:

for Dial Up Network (DUN) data connection. It requires the host to have and use its own

TCP/IP stack. The DUN can be initiated on modem side or terminal/host side.

 Channel 3:

for u-blox GNSS data tunneling (not supported by “00” and “01” product versions).

8

8

The configuration and the behavior of the UART signals after the boot sequence are described below:
 The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization.

The module holds RXD in the OFF state until the module transmits some data.

 The module data input line (TXD) is assumed to be controlled by the external host once UART is

initialized and if UART is used in the application. The TXD data input line has an internal active pull-

down enabled on the “00” and SARA-R410M-02B product versions, and an internal active pull-up

enabled on the other product version.

1.9.1.3 UART multiplexer protocol

SARA-R4/N4 series modules include multiplexer functionality as per 3GPP TS 27.010 [8], on the UART

physical link. This is a data link protocol which uses HDLC-like framing and operates between the module

(DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used

physical link (UART).

The following virtual channels are defined:

1.9.2 USB interface

1.9.2.1 USB features

SARA-R4/N4 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum

data rate, representing the main interface for transferring high speed data with a host application

processor, supporting:

 AT command mode
 Data mode and Online command mode

8

 FW upgrades by means of the FOAT feature (see 1.13.7)
 FW upgrades by means of the u-blox EasyFlash dedicated tool
 Trace log capture (diagnostic purposes)

For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [2]

UBX-16029218 - R11 System description Page 40 of 157

SARA-R4/N4 series - System Integration Manual

The module itself acts as a USB device and can be connected to a USB host such as a Personal Computer

or an embedded application microprocessor equipped with compatible drivers.

The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus
Revision 2.0 specification [4], while the VUSB_DET input pin senses the VBUS USB supply presence

(nominally 5 V at the source) to detect the host connection and enable the interface. Neither the USB
interface, nor the whole module is supplied by the VUSB_DET input, which senses the USB supply voltage

and absorbs few microamperes.

☞ The USB interface is available as AT command / data communication interface only if an external valid

USB VBUS supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the

switch-on of the module, and then held during normal operations. In this case, the UART will be not

available.

☞ If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external

USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter

the Power Saving Mode defined in 3GPP Rel.13.

The USB interface is controlled and operated with:

 AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]
 u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2])

The USB interface of SARA-R4/N4 series modules can provide the following USB functions:

 AT commands and data communication
 Diagnostic log

The USB profile of SARA-R4/N4 series modules identifies itself by the following VID (Vendor ID) and PID

(Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [4].

 VID = 0x05C6
 PID = 0x90B2

UBX-16029218 - R11 System description Page 41 of 157

SARA-R4/N4 series - System Integration Manual

1.9.3 SPI interface

☞ The SPI interface is not supported by “00”, “01”, “02” and “52” product versions: the SPI interface pins

should not be driven by any external device.

SARA-R4/N4 series modules include a Serial Peripheral Interface for communication with compatible

external device.

The SPI interface can be made available as alternative function, in mutually exclusive way, over the digital
audio interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK,

I2S_TXD / SPI_CS).

1.9.4 SDIO interface

☞ The SDIO interface is not supported by “00”, “01”, “02” and “52” product versions: the SDIO interface

pins should not be driven by any external device.

SARA-R4/N4 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1,
SDIO_D2, SDIO_D3, SDIO_CLK, and SDIO_CMD) designed to communicate with external compatible SDIO

devices.

1.9.5 DDC (I

☞ The I

SARA-R4/N4 series modules include an I2C-bus compatible DDC interface (SDA, SCL lines) available to

communicate with a u-blox GNSS receiver and with external I2C devices as an audio codec: the SARA-R4/N4

series module acts as an I2C master which can communicate with I2C slaves in accordance with the I2C bus

specifications [9].

The SDA and SCL pins have internal pull-up to V_INT, so there is no need of additional pull-up resistors

on the external application board.

2

C interface is not supported by “00” and “01” product versions: the I2C interface pins should not

be driven by any external device.

2

C) interface

1.10 Audio

☞ Audio is not supported by “00”, “01”, “02” and “52” ” product versions: the I

be driven by any external device.

UBX-16029218 - R11 System description Page 42 of 157

2

S interface pins should not

SARA-R4/N4 series - System Integration Manual

SARA-R4/N4 series modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio

services.

SARA-R4/N4 series modules include an I2S digital audio interface to transfer digital audio data to/from an

external compatible audio device.

The digital audio interface can be made available as alternative function, in mutually exclusive way, over
the SPI interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS).

UBX-16029218 - R11 System description Page 43 of 157

SARA-R4/N4 series - System Integration Manual

Function

Description

Default GPIO

Configurable GPIOs

Network status indication

Network status: registered / data transmission, no service

--

GPIO1

GNSS supply enable 9

Enable/disable the supply of a u-blox GNSS receiver

connected to the cellular module by the DDC (I2C)

interface

--

GPIO2

GNSS data ready 9

Sense when a u-blox GNSS receiver connected to the

module is ready for sending data by the DDC (I2C)

interface

--

GPIO3

SIM card detection

SIM card physical presence detection

--

GPIO5

Module status indication

Module switched off or in PSM low power deep sleep

mode, versus active or connected mode

--

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

Last gasp 10

Input to trigger last gasp notification

--

GPIO3, GPIO4, GPIO6

General purpose input

Input to sense high or low digital level

--

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

General purpose output

Output to set the high or the low digital level

--

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO6

Pin disabled

Tri-state with an internal active pull-down enabled

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

9

10

1.11 General Purpose Input/Output

SARA-R4/N4 series modules include six pins (GPIO1-GPIO6) which can be configured as General Purpose

Input/Output or to provide custom functions via u-blox AT commands (for more details see the SARA-

R4/N4 series AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized

in Table 8.

Table 8: SARA-R4/N4 series modules GPIO custom functions configuration

1.12 Reserved pins (RSVD)

SARA-R4/N4 series modules have pins reserved for future use, marked as RSVD.

All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number
33 that can be externally connected to ground.

Not supported by “00” and “01” product versions

Not supported by “00”, “01” and SARA-R410M-02B product versions

UBX-16029218 - R11 System description Page 44 of 157

SARA-R4/N4 series - System Integration Manual

1.13 System features

1.13.1 Network indication

GPIOs can be configured by the AT command to indicate network status (for further details see section 1.11

and the SARA-R4/N4 series AT Commands Manual [2]):

 No service (no network coverage or not registered)
 Registered / Data call enabled (RF data transmission / reception)

1.13.2 Antenna supervisor

The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional

feature that can be implemented if the application requires it. The antenna supervisor is forced by the

+UANTR AT command (see the SARA-R4/N4 series AT Commands Manual [2] for more details).

The requirements to achieve antenna detection functionality are the following:

 an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
 an antenna detection circuit must be implemented on the application board

See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for

detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines.

1.13.3 Dual stack IPv4/IPv6

SARA-R4/N4 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel.

For more details about dual stack IPv4/IPv6 see the SARA-R4/N4 series AT Commands Manual [2].

1.13.4 TCP/IP and UDP/IP

SARA-R4/N4 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be

configured established and handled via the data connection management packet switched data commands.

SARA-R4/N4 series modules provide Direct Link mode to establish a transparent end-to-end communication

with an already connected TCP or UDP socket via serial interfaces (USB, UART). In Direct Link mode, data

sent to the serial interface from an external application processor is forwarded to the network and vice-

versa.

For more details on embedded TCP/IP and UDP/IP functionalities, see SARA-R4/N4 series AT Commands

Manual [2].

1.13.5 FTP

SARA-R4/N4 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in the

local file system of the module.

UBX-16029218 - R11 System description Page 45 of 157

SARA-R4/N4 series - System Integration Manual

FTP files can also be transferred using FTP Direct Link:
 FTP download: data coming from the FTP server is forwarded to the host processor via USB / UART

serial interfaces (for FTP without Direct Link mode the data is always stored in the module’s flash file

system)

 FTP upload: data coming from the host processor via USB / UART serial interface is forwarded to the

FTP server (for FTP without Direct Link mode the data is read from the module’s flash file system)

When Direct Link is used for an FTP file transfer, only the file contents passes through USB / UART serial

interface, whereas all the FTP command handling is managed internally by the FTP application.

For more details about embedded FTP functionalities, see the SARA-R4/N4 series AT Commands Manual

[2].

1.13.6 HTTP

SARA-R4/N4 series modules provide the embedded Hypertext Transfer Protocol (HTTP) services via AT

commands for sending requests to a remote HTTP server, receiving the server response and transparently

storing it in the module’s flash file system. For more details, see the SARA-R4/N4 series AT Commands

Manual [2].

1.13.7 Firmware update Over AT (FOAT)

This feature allows upgrading of the module firmware over the AT interface, using AT commands.

The +UFWUPD AT command enables a code download to the device from the host via the Xmodem

protocol.

The +UFWINSTALL AT command then triggers a reboot, and upon reboot initiates a firmware installation

on the device via a special boot loader on the module. The bootloader first authenticates the downloaded

image, then installs it, and then reboots the module.

Firmware authenticity verification is performed via a security signature. The firmware is then installed,

overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at

the next wake-up, and restarts the firmware installation. After completing the upgrade, the module is reset

again and wakes-up in normal boot.

For more details about Firmware update Over AT procedure, see the SARA-R4/N4 series AT Commands

Manual [2], +UFWUPD AT command.

1.13.8 Firmware update Over The Air (uFOTA)

This feature allows upgrading the module firmware over the air interface, based on u-blox client/server

solution (uFOTA), using LWM2M.

For more details about firmware update over-the-air procedure, see the SARA-R4/N4 series AT Commands

Manual [2].

UBX-16029218 - R11 System description Page 46 of 157

SARA-R4/N4 series - System Integration Manual

11

1.13.9 Power saving

1.13.9.1 Guidelines to optimize power consumption

The LTE Cat M1 / NB1 technology is mainly intended for applications that only require a small amount of

data exchange per day (i.e. a few bytes in uplink and downlink per day). Depending on the application

type, the battery may be required to last for a few years. For these reasons, the whole application board

should be optimized in terms of current consumption and should carefully take into account the following

aspects:
 Enable the low power mode configuration using the AT+UPSV command (for the complete description

of the AT+UPSV command, see the SARA-R4/N4 series AT Commands Manual [2]).

 Enable the power saving mode configuration using the AT+CPSMS command (for the complete

description of the AT+CPSMS command, see the SARA-R4/N4 series AT Commands Manual [2]).

 Use the UART interface instead of the USB interface as a serial communication interface, because the

current consumption of the module is ~20 mA higher when the USB interface is enabled.

 Use an application processor with a UART interface working at the same voltage level (1.8 V) as the

module. In this way it is possible to avoid voltage translators, which helps to minimize current leakage.

 If the USB interface is implemented in the design, remove the external USB VBUS voltage from the

VUSB_DET input when serial communication is not necessary, letting the module enter the Power Saving

Mode defined in 3GPP Rel.13: the module does not enter the deep sleep power saving mode if the USB

interface is enabled.

 Minimize current leakage on the power supply line.
 Optimize the antenna matching, since a mismatched antenna leads to higher current consumption.
 Monitor V_INT level to sense when the module enters power-off mode or deep sleep power saving

mode.

 Disconnect the VCC supply source from the module when it is switched off (see 2.2.1.9).
 Disconnect the VCC supply source from the module during deep sleep power saving mode (see 2.2.1.9):

using a host application processor equipped with a RTC, the module can execute a standard PSM

procedure and store the NAS protocol context in non-volatile memory, and then rely on the host

application processor for running its RTC and triggering wake-up upon need11.

1.13.9.2 Functionality

When power saving is enabled using the AT+CPSMS command, the module automatically enters the low

power deep sleep mode whenever possible, reducing current consumption (see the section 1.5.1.4 and the

SARA-R4/N4 series Data Sheet [1]).

The use of an external RTC during deep sleep power saving mode is not supported by the “00”, “01” and “x2” product versions

UBX-16029218 - R11 System description Page 47 of 157

SARA-R4/N4 series - System Integration Manual

For the definition and the description of the SARA-R4/N4 series operating modes, including the events

forcing transitions between the different operating modes, see section 1.4.

The SARA-R4/N4 series modules achieve the low power deep sleep mode by powering down all the

Hardware components with the exception of the 32 kHz reference internally generated.

☞ From the host application point of view, the serial port will not be available during low power deep

sleep mode, as the SARA-R4/N4 series module will act as if it is in Power-Off mode.

1.13.9.3 Timers and network interaction

The SARA-R4/N4 series modules goes in low power deep sleep mode entering in the Power Saving Mode

(PSM) defined in 3GPP Release 13.

Two timers have been specified on the PSM Signaling: the “Periodic Update Timer” and “Active Timer”.

The “Active Timer” is the time defined by the network where the SARA-R4/N4 series module will keep

listening for any active operation, during this time the module is in Active mode.

The “Periodic Update Timer” is the Extended Tracking Area Update (TAU) used by the SARA-R4/N4 series

module to periodically notify the network of its availability.

The SARA-R4/N4 series module requests the PSM by including the “Active Timer” with the desired value in

the Attach, TAU or Routing Area Update (RAU) messages. The “Active Timer” is the time the module listens

to the Paging Channel after having transitioned from connected to active mode. When the “Active Timer”

expires, the module enters PSM low power deep sleep mode.

SARA-R4/N4 series module can also request an extended “Periodic Update Timer” value to remain in PSM

low power deep sleep mode for longer than the original “Periodic Update Timer” broadcasted by the

network.

The grant of PSM is a negotiation between SARA-R4/N4 series module and the attached network: the

network accepts PSM by providing the actual value of the “Active Timer” (and “Periodic Update Timer”) to

be used in the Attach/TAU/RAU accept procedure. The maximum duration, including the “Periodic Update

Timer”, is about 413 days. The SARA-R4/N4 series module enters PSM low power deep sleep mode only

after the “Active Timer” expires.

UBX-16029218 - R11 System description Page 48 of 157

SARA-R4/N4 series - System Integration Manual

PSM low power deep sleep mode

(periodic update timer)

Connected mode: Data Tx / Rx

Active mode

(active timer)

Time

Current

Figure 14: Description of the PSM timing

1.13.9.4 Timers and AT interaction

The SARA-R4/N4 series modules go into low power deep sleep mode and enter the Power Saving Mode

(PSM) only after the 6 s “AT Inactivity Timer” expires:

 If the UART interface is used, when the host application stops sending AT commands for 6 s – the “AT

Inactivity Timer” expiration – then the module enters deep sleep power saving mode according to

“Active Timer” expiration.

 If the USB interface is enabled, the module does not enter the deep sleep power saving mode.

1.13.9.5 AT commands

The module uses the +CPSMS AT command with its defined parameters to request PSM timers to the

network.

☞ See the SARA-R4/N4 series AT Commands Manual [2] for details of the +CPSMS operation and features.

1.13.9.6 Host application

The PSM low power deep sleep mode implementation allows the SARA-R4/N4 series module to help extend

the battery life of the application.

The Host Application should be aware that the SARA-R4/N4 series module is PSM-capable.

☞ The host application needs to sense the V_INT supply output of the module to get the notification

when the module has entered into PSM low power deep sleep mode.

☞ If the host application receives an event that needs to be reported by the SARA-R4/N4 series module

interrupting the PSM low power deep sleep mode, it can be done so by setting the module into Active

mode using the appropriate power-on event (see 1.6.1).

☞ From the host application point of view, the module will look as it is in Power-Off mode.

UBX-16029218 - R11 System description Page 49 of 157

SARA-R4/N4 series - System Integration Manual

1.13.9.7 Normal operation

The Host Application can force the SARA-R4/N4 series module to transition from PSM low power deep

sleep mode to Active mode by using the Power-Up procedure specified in section 1.6.1.

☞ Be aware that when the host application transitions from low power deep sleep mode to active mode,

it will cause the SARA-R4/N4 series module to consume the same amount of power as in active mode,

thereby shortening the battery life of the host application.

UBX-16029218 - R11 System description Page 50 of 157

SARA-R4/N4 series - System Integration Manual

2 Design-in

2.1 Overview

For an optimal integration of the SARA-R4/N4 series modules in the final application board, follow the

design guidelines stated in this section.

Every application circuit must be suitably designed to guarantee the correct functionality of the relative

interface, but a number of points require particular attention during the design of the application device.

The following list provides a rank of importance in the application design, starting from the highest

relevance:

1. Module antenna connection: ANT and ANT_DET pins.

Antenna circuit directly affects the RF compliance of the device integrating a SARA-R4/N4 series module

with applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the

schematic and layout design.

2. Module supply: VCC and GND pins.

The supply circuit affects the RF compliance of the device integrating a SARA-R4/N4 series module with

the applicable required certification schemes as well as the antenna circuit design. Very carefully follow

the suggestions provided in the relative section 2.2.1 for the schematic and layout design.

3. USB interface: USB_D+, USB_D- and VUSB_DET pins.

Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the

suggestions provided in the relative section 2.6.2 for the schematic and layout design.

4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins.

Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling.

Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design.

5. System functions: RESET_N and PWR_ON pins.

Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully

follow the suggestions provided in relative section 2.3 for schematic and layout design.

6. Other digital interfaces: UART, SPI, SDIO, I

Accurate design is required to guarantee correct functionality and reduce the risk of digital data

frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3, 2.6.4, 2.6.5,

2.7, 2.8 and 2.9 for the schematic and layout design.

UBX-16029218 - R11 Design-in Page 51 of 157

2

C, I2S, GPIOs and reserved pins.

SARA-R4/N4 series - System Integration Manual

7. Other supplies: V_INT generic digital interfaces supply.

Accurate design is required to guarantee correct functionality. Follow the suggestions provided in the

corresponding section 2.2.2 for the schematic and layout design.

☞ It is recommended to follow the specific design guidelines provided by each manufacturer of any

external part selected for the application board integrating the u-blox cellular modules.

UBX-16029218 - R11 Design-in Page 52 of 157

SARA-R4/N4 series - System Integration Manual

Main Supply

Available?

Battery

Li-Ion 3.7 V

Linear LDO

Regulator

Main Supply

Voltage > 5V?

Swit ching Step-Down

Regulator

No, port able device

No, less t han 5 V

Yes, greater than 5 V

Yes, always available

2.2 Supply interfaces

2.2.1 Module supply (VCC)

2.2.1.1 General guidelines for VCC supply circuit selection and design

All the available VCC pins have to be connected to the external supply minimizing the power loss due to

series resistance.

GND pins are internally connected. Application design shall connect all the available pads to solid ground

on the application board, since a good (low impedance) connection to external ground can minimize power

loss and improve RF and thermal performance.

SARA-R4/N4 series modules must be sourced through the VCC pins with a suitable DC power supply that
should meet the following prerequisites to comply with the modules’ VCC requirements summarized in

Table 6.

The appropriate DC power supply can be selected according to the application requirements (see Figure

15) between the different possible supply sources types, which most common ones are the following:

 Switching regulator
 Low Drop-Out (LDO) linear regulator
 Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery
 Primary (disposable) battery

Figure 15: VCC supply concept selection

The switching step-down regulator is the typical choice when primary supply source has a nominal voltage

much higher (e.g. greater than 5 V) than the operating supply voltage of SARA-R4/N4 series. The use of

switching step-down provides the best power efficiency for the overall application and minimizes current

drawn from the main supply source. See section 2.2.1.2 for design-in.

The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage

(e.g. less or equal than 5 V). In this case, the typical 90% efficiency of the switching regulator diminishes

the benefit of voltage step-down and no true advantage is gained in input current savings. On the opposite

UBX-16029218 - R11 Design-in Page 53 of 157

SARA-R4/N4 series - System Integration Manual

side, linear regulators are not recommended for high voltage step-down as they dissipate a considerable

amount of energy in thermal power. See section 2.2.1.3 for design-in.

If SARA-R4/N4 series modules are deployed in a mobile unit where no permanent primary supply source is
available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack
directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with
Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should

therefore be avoided. See sections 2.2.1.4, 2.2.1.5, 2.2.1.6 and 2.2.1.7 for specific design-in.

Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger

circuit, which is not included in the modules. The charger circuit needs to be designed to prevent over­voltage on VCC pins, and it should be selected according to the application requirements. A DC/DC

switching charger is the typical choice when the charging source has a high nominal voltage (e.g. ~12 V),

whereas a linear charger is the typical choice when the charging source has a relatively low nominal voltage

(~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up

battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a suitable charger

/ regulator with integrated power path management function can be selected to supply the module while

simultaneously and independently charging the battery. See sections 2.2.1.6 and 2.2.1.7 for specific design-

in.

An appropriate primary (not rechargeable) battery can be selected taking into account the maximum current

specified in the SARA-R4/N4 series Data Sheet [1] during connected mode, considering that primary cells

might have weak power capability. See section 2.2.1.5 for specific design-in.

The usage of more than one DC supply at the same time should be carefully evaluated: depending on the

supply source characteristics, different DC supply systems can result as mutually exclusive.

The selected regulator or battery must be able to support with adequate margin the highest averaged

current consumption value specified in the SARA-R4/N4 series Data Sheet [1].

The following sections highlight some design aspects for each of the supplies listed above providing
application circuit design-in compliant with the module VCC requirements summarized in Table 6.

2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator

The use of a switching regulator is suggested when the difference from the available supply rail source to
the VCC value is high, since switching regulators provide good efficiency transforming a 12 V or greater
voltage supply to the typical 3.8 V value of the VCC supply.

The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites
to comply with the module VCC requirements summarized in Table 6:

UBX-16029218 - R11 Design-in Page 54 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/ N4

12V

C5

R3

C4

R2

C2C1

R1

VIN

RUN
VC
RT
PG

SYNC

BD

BOOST

SW

FB

GND

6

7

10

9

5

C6

1
2
3

8

11

4

C7

C8

D1

R4

R5

L1

C3

U1

52

VCC

53

VCC

51

VCC

GND

C9 C10 C11

Reference

Description

Part Number - Manufacturer

C1

10 µF Capacitor Ceramic X7R 5750 15% 50 V

Generic manufacturer

C2

10 nF Capacitor Ceramic X7R 0402 10% 16 V

Generic manufacturer

C3

680 pF Capacitor Ceramic X7R 0402 10% 16 V

Generic manufacturer

C4

22 pF Capacitor Ceramic C0G 0402 5% 25 V

Generic manufacturer

 Power capability: the switching regulator with its output circuit must be capable of providing a voltage

value to the VCC pins within the specified operating range and must be capable of delivering to VCC

pins the maximum current consumption occurring during transmissions at the maximum power, as

specified in the SARA-R4/N4 series Data Sheet [1].

 Low output ripple: the switching regulator together with its output circuit must be capable of providing

a clean (low noise) VCC voltage profile.

 High switching frequency: for best performance and for smaller applications it is recommended to

select a switching frequency ≥ 600 kHz (since L-C output filter is typically smaller for high switching

frequency). The use of a switching regulator with a variable switching frequency or with a switching
frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC

profile and therefore negatively impact modulation spectrum performance.

 PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode.

While in connected mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM modes
transitions must be avoided to reduce noise on VCC voltage profile. Switching regulators can be used

that are able to switch between low ripple PWM mode and high ripple PFM mode, provided that the

mode transition occurs when the module changes status from the active mode to connected mode. It

is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an

appropriate current threshold.

Figure 16 and the components listed in Table 9 show an example of a high reliability power supply circuit

for the SARA-R412M modules that support 2G radio access technology. This circuit is also suitable for the

other SARA-R4/N4 series modules, where the module VCC input is supplied by a step-down switching

regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, with low

output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz.

Figure 16: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

UBX-16029218 - R11 Design-in Page 55 of 157

SARA-R4/N4 series - System Integration Manual

C5

10 nF Capacitor Ceramic X7R 0402 10% 16 V

Generic manufacturer

C6

470 nF Capacitor Ceramic X7R 0603 10% 25 V

Generic manufacturer

C7

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C8

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

C9

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C10

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C11

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

D1

Schottky Diode 40 V 3 A

MBRA340T3G - ON Semiconductor

L1

10 µH Inductor 744066100 30% 3.6 A

744066100 - Wurth Electronics

R1

470 k Resistor 0402 5% 0.1 W

Generic manufacturer

R2

15 k Resistor 0402 5% 0.1 W

Generic manufacturer

R3

22 k Resistor 0402 5% 0.1 W

Generic manufacturer

R4

390 k Resistor 0402 1% 0.063 W

Generic manufacturer

R5

100 k Resistor 0402 5% 0.1 W

Generic manufacturer

U1

Step-Down Regulator MSOP10 3.5 A 2.4 MHz

LT3972IMSE#PBF - Linear Technology

SARA-R404M

SARA-R410M

SARA-N410

12V

C2C1

VCC

EN

PG

VSW

GND

8

9

1

4

2

D1

L1

U1

BST

FB

5

R1

R2

52

VCC

53

VCC

51

VCC

GND

3V8

C6 C7 C8

PGND

C4

C3

C5

11

10

C9

Reference

Description

Part Number - Manufacturer

C1

10 µF Capacitor Ceramic X7R 50 V

Generic manufacturer

Table 9: Components for high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

Figure 17 and the components listed in Table 10 show an example of a high reliability power supply circuit

for SARA-R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access
technology. In this example, the module VCC is supplied by a step-down switching regulator capable of

delivering the maximum peak / pulse current specified for the LTE use-case, with low output ripple and

with fixed switching frequency in PWM mode operation greater than 1 MHz.

Figure 17: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using a step-down regulator

UBX-16029218 - R11 Design-in Page 56 of 157

SARA-R4/N4 series - System Integration Manual

C2

10 nF Capacitor Ceramic X7R 16 V

Generic manufacturer

C3

22 nF Capacitor Ceramic X7R 16 V

Generic manufacturer

C4

22 µF Capacitor Ceramic X5R 25 V

Generic manufacturer

C5

22 µF Capacitor Ceramic X5R 25 V

Generic manufacturer

C6

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

C7

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C8

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C9

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

D1

Schottky Diode 30 V 2 A

MBR230LSFT1G - ON Semiconductor

L1

4.7 µH Inductor 20% 2 A

SLF7045T-4R7M2R0-PF - TDK

R1

470 k Resistor 0.1 W

Generic manufacturer

R2

150 k Resistor 0.1 W

Generic manufacturer

U1

Step-Down Regulator 1 A 1 MHz

TS30041 - Semtech

Table 10: High reliability VCC supply circuit components for SARA-R404M /-R410M /-N410, using a step-down regulator

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 57 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/N4

12V

R5

C2C1

VCC

INH

FSW
SYNC

OUT

GND

2

6

3

1

7

8

C3

D1

R1

R2

L1

U1

GND

FB

COMP

5
4

R3

C4

R4

C5

52

VCC

53

VCC

51

VCC

C6

C7 C8 C9 C10

Reference

Description

Part Number - Manufacturer

C1

22 µF Capacitor Ceramic X5R 1210 10% 25 V

Generic manufacturer

C2

220 nF Capacitor Ceramic X7R 0603 10% 25 V

Generic manufacturer

C3

5.6 nF Capacitor Ceramic X7R 0402 10% 50 V

Generic manufacturer

C4

6.8 nF Capacitor Ceramic X7R 0402 10% 50 V

Generic manufacturer

C5

56 pF Capacitor Ceramic C0G 0402 5% 50 V

Generic manufacturer

C6

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C7

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

C8

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C9

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C10

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

D1

Schottky Diode 25V 2 A

STPS2L25 – STMicroelectronics

L1

5.2 µH Inductor 30% 5.28A 22 m

MSS1038-522NL – Coilcraft

R1

4.7 k Resistor 0402 1% 0.063 W

Generic manufacturer

R2

910  Resistor 0402 1% 0.063 W

Generic manufacturer

R3

82  Resistor 0402 5% 0.063 W

Generic manufacturer

R4

8.2 k Resistor 0402 5% 0.063 W

Generic manufacturer

R5

39 k Resistor 0402 5% 0.063 W

Generic manufacturer

U1

Step-Down Regulator 8-VFQFPN 3 A 1 MHz

L5987TR – ST Microelectronics

Figure 18 and the components listed in Table 11 show an example of a low cost power supply circuit

suitable for all the SARA-R4/N4 series modules, where the module VCC is supplied by a step-down switching

regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, transforming

a 12 V supply input.

Figure 18: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

Table 11: Suggested components for low cost VCC circuit for SARA-R4/N4 series modules, using a step-down regulator

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 58 of 157

SARA-R4/N4 series - System Integration Manual

UBX-16029218 - R11 Design-in Page 59 of 157

SARA-R4/N4 series - System Integration Manual

5V

C1

IN

OUT

ADJ

GND

1

2

4

5

3

R1

R2

U1

SHDN

SARA-R4/N4

52

VCC

53

VCC

51

VCC

GND

C2

C3 C4 C5 C6

Reference

Description

Part Number - Manufacturer

C1

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

Generic manufacturer

C2

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C3

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator

The use of a linear regulator is suggested when the difference from the available supply rail source and the
VCC value is low. The linear regulators provide high efficiency when transforming a 5 VDC supply to a
voltage value within the module VCC normal operating range.

The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC pins should meet the
following prerequisites to comply with the module VCC requirements summarized in Table 6:

 Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a

voltage value to the VCC pins within the specified operating range and must be capable of delivering
to VCC pins the maximum current consumption occurring during a transmission at the maximum Tx

power, as specified in the SARA-R4/N4 series Data Sheet [1].

 Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit

its junction temperature to the rated range (i.e. check the voltage drop from the maximum input voltage

to the minimum output voltage to evaluate the power dissipation of the regulator).

Figure 19 and the components listed in Table 12 show an example of a high reliability power supply circuit

for the SARA-R412M modules supporting the 2G radio access technology. This example is also suitable for
the other SARA-R4/N4 series modules, where the VCC module supply is provided by an LDO linear regulator

capable of delivering the highest peak / pulse current specified for the 2G use-case, with an appropriate

power handling capability. The regulator described in this example supports a wide input voltage range,

and it includes internal circuitry for reverse battery protection, current limiting, thermal limiting and reverse

current protection.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below
the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in

Figure 20 and Table 13). This reduces the power on the linear regulator and improves the whole thermal

design of the supply circuit.

Figure 19: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator

UBX-16029218 - R11 Design-in Page 60 of 157

SARA-R4/N4 series - System Integration Manual

C4

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C5

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C6

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

R1

9.1 k Resistor 0402 5% 0.1 W

Generic manufacturer

R2

3.9 k Resistor 0402 5% 0.1 W

Generic manufacturer

U1

LDO Linear Regulator ADJ 3.0 A

LT1764AEQ#PBF - Linear Technology

5V

C1

R1

IN OUT

ADJ

GND

5

8

1

3

4

C2

R2

R3

U1

EN

SARA-R404M

SARA-R410M

SARA-N410

52

VCC

53

VCC

51

VCC

GND

C4

C3 C5 C6

Reference

Description

Part Number - Manufacturer

C1

1 µF Capacitor Ceramic X5R 6.3 V

Generic manufacturer

C2

22 µF Capacitor Ceramic X5R 25 V

Generic manufacturer

C3

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

C4

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C5

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C6

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

R1

47 k Resistor 0.1 W

Generic manufacturer

R2

41 k Resistor 0.1 W

Generic manufacturer

R3

10 k Resistor 0.1 W

Generic manufacturer

Table 12: Suggested components for high reliability VCC circuit for SARA-R4/N4 series modules, using an LDO regulator

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

Figure 20 and the components listed in Table 13 show an example of a high reliability power supply circuit

for SARA-R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access
technology, where the module VCC is supplied by an LDO linear regulator capable of delivering maximum

peak / pulse current specified for LTE use-case, with suitable power handling capability.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below
the maximum limit of the module VCC normal operating range (e.g. ~4.1 V for the VCC, as in the circuits

described in Figure 20 and Table 13). This reduces the power on the linear regulator and improves the

thermal design of the circuit.

Figure 20: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator

UBX-16029218 - R11 Design-in Page 61 of 157

SARA-R4/N4 series - System Integration Manual

U1

LDO Linear Regulator 1.0 A

AP7361 – Diodes Incorporated

5V

C1

IN

OUT

ADJ

GND

1

2

4

5

3

R1

R2

U1

EN

SARA-R4/N4

52

VCC

53

VCC

51

VCC

GND

C2

C3 C4 C5 C6

Reference

Description

Part Number - Manufacturer

C1

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

Generic manufacturer

C2

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C3

100 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

C4

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C103KA01 - Murata

C5

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

C6

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

R1

27 k Resistor 0402 5% 0.1 W

Generic manufacturer

R2

4.7 k Resistor 0402 5% 0.1 W

Generic manufacturer

U1

LDO Linear Regulator ADJ 3.0 A

LP38501ATJ-ADJ/NOPB - Texas Instrument

Table 13: Components for high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

Figure 21 and the components listed in Table 14 show an example of a low cost power supply circuit, where

the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest

peak / pulse current, with an appropriate power handling capability. The regulator described in this example

supports a limited input voltage range and it includes internal circuitry for current and thermal protection.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below

the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in

Figure 21 and Table 14). This reduces the power on the linear regulator and improves the whole thermal

design of the supply circuit.

Figure 21: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator

Table 14: Suggested components for low cost VCC supply circuit for SARA-R4/N4 modules, using an LDO linear regulator

UBX-16029218 - R11 Design-in Page 62 of 157

SARA-R4/N4 series - System Integration Manual

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 63 of 157

SARA-R4/N4 series - System Integration Manual

2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery

Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following prerequisites
to comply with the module VCC requirements summarized in Table 6:

 Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output

circuit connected to the VCC pins must be capable of delivering the maximum current occurring during

a transmission at maximum Tx power, as specified in the SARA-R4/N4 series Data Sheet [1]. The

maximum discharge current is not always reported in the data sheets of batteries, but the maximum

DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour.

 DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding

a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts.

2.2.1.5 Guidelines for VCC supply circuit design using a primary battery

The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the
following prerequisites to comply with the module VCC requirements summarized in Table 6:

 Maximum pulse and DC discharge current: the non-rechargeable battery with its related output circuit

connected to the VCC pins must be capable of delivering the maximum current consumption occurring

during a transmission at maximum Tx power, as specified in SARA-R4/N4 series Data Sheet [1]. The

maximum discharge current is not always reported in the data sheets of batteries, but the maximum

DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour.

 DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding

a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts.

2.2.1.6 Guidelines for external battery charging circuit

SARA-R4/N4 series modules do not have an on-board charging circuit. Figure 22 provides an example of a

battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell.

In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features the correct pulse

and DC discharge current capabilities and the appropriate DC series resistance, is directly connected to the
VCC supply input of the module. Battery charging is completely managed by the Battery Charger IC, which

from a USB power source (5.0 V typ.), linearly charges the battery in three phases:
 Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with

a low current.

 Fast-charge constant current: the battery is charged with the maximum current, configured by the

value of an external resistor.

UBX-16029218 - R11 Design-in Page 64 of 157

SARA-R4/N4 series - System Integration Manual

C5C3 C6

GND

SARA-R4/N4

52

VCC

53

VCC

51

VCC

USB

Supply

θ

U1

PG

STAT2

STA1

VDD

C1

5V0

THERM

Vss

Vbat

Li-Ion/Li-Pol

Batt ery Pack

D1

B1

C2

Li-Ion/Li-Polymer

Batt ery Charger IC

D2

PROG

R1

C4

Reference

Description

Part Number - Manufacturer

B1

Li-Ion (or Li-Polymer) battery pack with 470  NTC

Generic manufacturer

C1

1 µF Capacitor Ceramic X7R 16 V

Generic manufacturer

C2

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C3

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150JA01 - Murata

C4

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

C5

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

C6

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1, D2

Low Capacitance ESD Protection

CG0402MLE-18G - Bourns

R1

10 k Resistor 0.1 W

Generic manufacturer

U1

Single Cell Li-Ion (or Li-Polymer) Battery Charger IC

MCP73833 - Microchip

 Constant voltage: when the battery voltage reaches the regulated output voltage, the Battery Charger

IC starts to reduce the current until the charge termination is done. The charging process ends when

the charging current reaches the value configured by an external resistor or when the charging timer

reaches the factory set value.

Using a battery pack with an internal NTC resistor, the Battery Charger IC can monitor the battery

temperature to protect the battery from operating under unsafe thermal conditions.

The Battery Charger IC, as linear charger, is more suitable for applications where the charging source has a

relatively low nominal voltage (~5 V), so that a switching charger is suggested for applications where the

charging source has a relatively high nominal voltage (e.g. ~12 V, see section 2.2.1.7 for the specific design-

in).

Figure 22: Li-Ion (or Li-Polymer) battery charging application circuit

Table 15: Suggested components for the Li-Ion (or Li-Polymer) battery charging application circuit

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 65 of 157

SARA-R4/N4 series - System Integration Manual

GND

Power path management IC

VoutVin

θ

Li-Ion/Li-Pol
Bat tery Pack

GND

Syst em

12 V

Primary

Source

Charge

controller

DC/DC convert er
and bat t ery FET

control logic

Vbat

2.2.1.7 Guidelines for external charging and power path management circuit

Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a

rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as a possible supply source,

should implement a suitable charger / regulator with integrated power path management function to supply

the module and the whole device while simultaneously and independently charging the battery.

Figure 23 reports a simplified block diagram circuit showing the working principle of a charger / regulator

with integrated power path management function. This component allows the system to be powered by a

permanent primary supply source (e.g. ~12 V) using the integrated regulator, which simultaneously and

independently recharges the battery (e.g. 3.7 V Li-Pol) that represents the back-up supply source of the

system. The power path management feature permits the battery to supplement the system current

requirements when the primary supply source is not available or cannot deliver the peak system currents.

A power management IC should meet the following prerequisites to comply with the module VCC

requirements summarized in Table 6:

 High efficiency internal step down converter, with characteristics as indicated in section 2.2.1.2
 Low internal resistance in the active path Vout – Vbat, typically lower than 50 m
 High efficiency switch mode charger with separate power path control

Figure 23: Charger / regulator with integrated power path management circuit block diagram

Figure 24 and the parts listed in Table 16 provide an application circuit example where the MPS MP2617H

switching charger / regulator with integrated power path management function provides the supply to the

cellular module. At the same time it also concurrently and autonomously charges a suitable Li-Ion (or Li-

Polymer) battery with the correct pulse and DC discharge current capabilities and the appropriate DC series

resistance according to the rechargeable battery recommendations described in section 2.2.1.4.

The MP2617H IC constantly monitors the battery voltage and selects whether to use the external main

primary supply / charging source or the battery as supply source for the module, and starts a charging

phase accordingly.

UBX-16029218 - R11 Design-in Page 66 of 157

SARA-R4/N4 series - System Integration Manual

The MP2617H IC normally provides a supply voltage to the module regulated from the external main

primary source allowing immediate system operation even under missing or deeply discharged battery: the

integrated switching step-down regulator is capable to provide up to 3 A output current with low output

ripple and fixed 1.6 MHz switching frequency in PWM mode operation. The module load is satisfied in

priority, then the integrated switching charger will take the remaining current to charge the battery.

Additionally, the power path control allows an internal connection from battery to the module with a low

series internal ON resistance (40 m typical), in order to supplement additional power to the module when

the current demand increases over the external main primary source or when this external source is

removed.

Battery charging is managed in three phases:
 Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with

a low current, set to 10% of the fast-charge current

 Fast-charge constant current: the battery is charged with the maximum current, configured by the

value of an external resistor to a value suitable for the application

 Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is

progressively reduced until the charge termination is done. The charging process ends when the

charging current reaches the 10% of the fast-charge current or when the charging timer reaches the

value configured by an external capacitor

Using a battery pack with an internal NTC resistor, the MP2617H can monitor the battery temperature to

protect the battery from operating under unsafe thermal conditions.

Several parameters as the charging current, the charging timings, the input current limit, the input voltage

limit, the system output voltage can be easily set according to the specific application requirements, as the

actual electrical characteristics of the battery and the external supply / charging source: suitable resistors

or capacitors must be accordingly connected to the related pins of the IC.

UBX-16029218 - R11 Design-in Page 67 of 157

SARA-R4/N4 series - System Integration Manual

C10 C13

GND

C12C11

SARA-R4/N4

52

VCC

53

VCC

51

VCC

+

Primary

Source

R3

U1

ENn

ILIM

ISET
TMR

AGND

VIN

C2C1

12V

NTC

PGND

SW

SYS

BAT

C4

R1

R2

D1

θ

Li-Ion/Li-Pol

Batt ery Pack

B1

C5

Li-Ion/Li-Polymer Batt ery

Charger / Regulat or with
Power Path Managment

VCC

C3 C6

L1

BST

D2

VLIM

R4

R5

C7 C8

D3

R6

SYSFB

R7

Reference

Description

Part Number - Manufacturer

B1

Li-Ion (or Li-Polymer) battery pack with 10 k NTC

Various manufacturer

C1, C6

22 µF Capacitor Ceramic X5R 1210 10% 25 V

GRM32ER61E226KE15 - Murata

C2, C4, C10

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

C3

1 µF Capacitor Ceramic X7R 0603 10% 25 V

GRM188R71E105KA12 - Murata

C5

330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m

T520D337M006ATE045 - KEMET

C7, C12

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

C8, C13

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E150JA01 - Murata

C11

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

D1, D2

Low Capacitance ESD Protection

CG0402MLE-18G - Bourns

D3

Schottky Diode 40 V 3 A

MBRA340T3G - ON Semiconductor

R1, R3, R5, R7

10 k Resistor 0402 1% 1/16 W

Generic manufacturer

R2

1.05 k Resistor 0402 1% 0.1 W

Generic manufacturer

R4

22 k Resistor 0402 1% 1/16 W

Generic manufacturer

R6

26.5 k Resistor 0402 1% 1/16 W

Generic manufacturer

L1

2.2 µH Inductor 7.4 A 13 m 20%

SRN8040-2R2Y - Bourns

U1

Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator with

integrated Power Path Management function

MP2617H - Monolithic Power Systems (MPS)

Figure 24: Li-Ion (or Li-Polymer) battery charging and power path management application circuit

Table 16: Suggested components for battery charging and power path management application circuit

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 68 of 157

SARA-R4/N4 series - System Integration Manual

C1 C4

GND

C3C2 C5

SARA-R412M

52

VCC

53

VCC

51

VCC

+

Li-Ion/Li-Pol
Batt ery

C6

SWVIN

SHDNn

GND

FB

C7

R1

R2

L1

U1

Step-up
Regulat or

D1

C8

Reference

Description

Part Number - Manufacturer

C1

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C2

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

C3

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

C4

56 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E560JA01 - Murata

C5

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E150JA01 - Murata

C6

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

GRM188R60J106ME47 - Murata

C7

22 µF Capacitor Ceramic X5R 1210 10% 25 V

GRM32ER61E226KE15 - Murata

C8

10 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E100JA01 - Murata

D1

Schottky Diode 40 V 1 A

SS14 - Vishay General Semiconductor

L1

10 µH Inductor 20% 1 A 276 m

SRN3015-100M - Bourns Inc.

R1

1 M Resistor 0402 5% 0.063 W

Generic manufacturer

R2

412 k Resistor 0402 5% 0.063 W

Generic manufacturer

U1

Step-up Regulator 350 mA

AP3015 - Diodes Incorporated

2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R412M

SARA-R412M modules have separate supply inputs over the VCC pins (see Figure 3):

 VCC pins #52 and #53: supply input for the internal RF Power Amplifier, demanding most of the total

current drawn of the module when RF transmission is enabled during a call

 VCC pin #51: supply input for the internal Power Management Unit, Base-Band and Transceiver parts,

demanding minor current

Generally, all the VCC pins are intended to be connected to the same external power supply circuit, but

separate supply sources can be implemented for specific (e.g. battery-powered) applications. The voltage

at the VCC pins #52 and #53 can drop to a value lower than the one at the VCC pin #51, keeping the

module still switched-on and functional. Figure 25 illustrates a possible application circuit.

Figure 25: VCC circuit example with separate supply for SARA-R412M modules

Table 17: Examples of components for the VCC circuit with separate supply for SARA-R412M modules

UBX-16029218 - R11 Design-in Page 69 of 157

SARA-R4/N4 series - System Integration Manual

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

UBX-16029218 - R11 Design-in Page 70 of 157

SARA-R4/N4 series - System Integration Manual

C3

GND

C2C1 C4

SARA-R4/N4

52

VCC

53

VCC

51

VCC

VCC Supply Source

GND

C5

U1

VOUTVIN
VBIAS
ON

CT

GND

4

V_INT

15

PWR_ON

R1

R2

T1

GPIO

Application

Processor

GPIO

GPIO

+

Reference

Description

Part Number - Manufacturer

C1

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

C2

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

C3

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

C4

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

C5

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E150JA01 - Murata

R1, R3

47 k Resistor 0402 5% 0.1 W

RC0402JR-0747KL - Yageo Phycomp

R2

10 k Resistor 0402 5% 0.1 W

RC0402JR-0710KL - Yageo Phycomp

T1

NPN BJT Transistor

BC847 - Infineon

U1

Ultra-Low Resistance Load Switch

TPS22967 - Texas Instruments

2.2.1.9 Guidelines for removing VCC supply

Removing the VCC power can be useful to minimize the current consumption when the SARA-R4/N4 series

modules are switched off or when the modules are in deep sleep Power Saving Mode.

In applications in which the module is paired to a host application processor equipped with a RTC, the

module can execute standard PSM procedures, store NAS protocol context in non-volatile memory, and

rely on the host application processor to run its RTC and to trigger wake-up upon need. The application
processor can disconnect the VCC supply source from the module and zero out the module’s PSM current.

The VCC supply source can be removed using an appropriate low-leakage load switch or p-channel MOSFET

controlled by the application processor as shown in Figure 26, given that the external switch has provide:

 Very low leakage current (for example, less than 1 µA), to minimize the current consumption
 Very low R

series resistance (for example, less than 50 m), to minimize voltage drops

DS(ON)

 Adequate maximum Drain current (see the SARA-R4/N4 series Data Sheet [1] for module current

consumption figures)

Figure 26: Example of application circuit for VCC supply removal

Table 18: Components for VCC supply removal application circuit

UBX-16029218 - R11 Design-in Page 71 of 157

SARA-R4/N4 series - System Integration Manual

☞ It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series

normal operations: the VCC supply can be removed only after V_INT goes low, indicating that the

module has entered Deep-Sleep Power Saving Mode or Power-Off Mode.

☞ See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be

provided if the application device integrates an internal antenna.

2.2.1.10 Additional guidelines for VCC supply circuit design

To reduce voltage drops, use a low impedance power source. The series resistance of the supply lines
(connected to the modules’ VCC and GND pins) on the application board and battery pack should also be

considered and minimized: cabling and routing must be as short as possible to minimize losses.

Three pins are allocated to VCC supply connection. Several pins are designated for GND connection. It is

recommended to correctly connect all of them to supply the module minimizing series resistance.

To reduce voltage ripple and noise, improving RF performance especially if the application device integrates
an internal antenna, place the following bypass capacitors near the VCC pins:

 68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata

GRM1555C1H680J), to filter EMI in the low cellular frequency bands

 15 pF capacitor with Self-Resonant Frequency in the 1800/1900 MHz range (as Murata

GRM1555C1H150J), to filter EMI in the high cellular frequency bands

 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise from clocks and data
 100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data

An additional capacitor is recommended to avoid undershoot and overshoot at the start and at the end of

RF transmission:

 100 µF low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA-R412M supporting 2G
 10 µF capacitor (or greater), for the other SARA-R4/N4 series modules that do not support 2G

An additional series ferrite bead is recommended for additional RF noise filtering, in particular if the

application device integrates an internal antenna:
 Ferrite bead specifically designed for EMI suppression in GHz band (e.g. Murata BLM18EG221SN1),

placed as close as possible to the VCC pins of the module, implementing the circuit described in Figure

27, to filter out EMI in all the cellular bands

UBX-16029218 - R11 Design-in Page 72 of 157

SARA-R4/N4 series - System Integration Manual

C5

GND plane

VCC line

Capacit or wit h
SRF ~900 MHz

C1 C3 C4

FB1

Ferrit e Bead

for GHz noise

C2

C1

GND

C2 C4

SARA-R4/N4

52

VCC

53

VCC

51

VCC

3V8

C5

+

FB1

C3

Capacit or wit h

SRF ~1900 MHz

SARA

Reference

Description

Part Number - Manufacturer

C1

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

C2

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150JA01 - Murata

C3

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

C4

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

C5

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m

T520B107M006ATE015 – Kemet

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

GRM188R60J106ME47 - Murata

FB1

Chip Ferrite Bead EMI Filter for GHz Band Noise

220  at 100 MHz, 260  at 1 GHz, 2000 mA

BLM18EG221SN1 - Murata

Figure 27: Suggested design to reduce ripple / noise on VCC, highly recommended when using an integrated antenna

Table 19: Suggested components to reduce ripple / noise on VCC

☞ The necessity of each part depends on the specific design, but it is recommended to provide all the

parts described in Figure 27 / Table 19 if the application device integrates an internal antenna.

☞ ESD sensitivity rating of the VCC supply pins is 1 kV (HBM according to JESD22-A114). Higher protection

level can be required if the line is externally accessible on the application board, e.g. if accessible battery

connector is directly connected to the supply pins. Higher protection level can be achieved by mounting

an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point.

2.2.1.11 Guidelines for VCC supply layout design

Good connection of the module VCC pins with DC supply source is required for correct RF performance.

Guidelines are summarized in the following list:

 All the available VCC pins must be connected to the DC source
 VCC connection must be as wide as possible and as short as possible
 Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be

avoided

 VCC connection must be routed through a PCB area separated from RF lines / parts, sensitive analog

signals and sensitive functional units: it is good practice to interpose at least one layer of PCB ground
between the VCC track and other signal routing

UBX-16029218 - R11 Design-in Page 73 of 157

SARA-R4/N4 series - System Integration Manual

SARA

VCC

ANT

Antenna

NOT OK

Antenna

SARA

VCC

ANT

OK

Antenna

SARA

VCC

ANT

NOT OK

 VCC connection must be routed as far as possible from the antenna, in particular if embedded in the

application device: see Figure 28

 Coupling between VCC and digital lines, especially USB, must be avoided.
 The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.10 should

be placed close to the VCC pins. If the main DC source is a switching DC-DC converter, place the large
capacitor close to the DC-DC output and minimize VCC track length. Otherwise consider using separate

capacitors for DC-DC converter and module tank capacitor

 The bypass capacitors in the pF range described in Figure 27 and Table 19 should be placed as close

as possible to the VCC pins, where the VCC line narrows close to the module input pins, improving the

RF noise rejection in the band centered on the Self-Resonant Frequency of the pF capacitors. This is

highly recommended if the application device integrates an internal antenna

 Since VCC input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may result

in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching

DC-DC converters, in which case it is better to select the highest operating frequency for the switcher

and add a large L-C filter before connecting to the SARA-R4/N4 series modules in the worst case

 Shielding of switching DC-DC converter circuit, or at least the use of shielded inductors for the switching

DC-DC converter, may be considered since all switching power supplies may potentially generate

interfering signals as a result of high-frequency high-power switching.

 If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings are not

exceeded, place the protecting device along the path from the DC source toward the module, preferably

closer to the DC source (otherwise protection function may be compromised)

Figure 28: VCC line routing guideline for designs integrating an embedded antenna

2.2.1.12 Guidelines for grounding layout design

Good connection of the module GND pins with application board solid ground layer is required for correct

RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module.

 Connect each GND pin with application board solid GND layer. It is strongly recommended that each

GND pad surrounding VCC pins have one or more dedicated via down to the application board solid

ground layer

 The VCC supply current flows back to main DC source through GND as ground current: provide

adequate return path with suitable uninterrupted ground plane to main DC source

UBX-16029218 - R11 Design-in Page 74 of 157

SARA-R4/N4 series - System Integration Manual

 It is recommended to implement one layer of the application board as ground plane as wide as possible
 If the application board is a multilayer PCB, then all the board layers should be filled with GND plane

as much as possible and each GND area should be connected together with complete via stack down

to the main ground layer of the board. Use as many vias as possible to connect the ground planes

 Provide a dense line of vias at the edges of each ground area, in particular along RF and high speed

lines

 If the whole application device is composed by more than one PCB, then it is required to provide a

good and solid ground connection between the GND areas of all the different PCBs

 Good grounding of GND pads also ensures thermal heat sink. This is critical during connection, when

the real network commands the module to transmit at maximum power: correct grounding helps prevent

module overheating.

2.2.2 Generic digital interfaces supply output (V_INT)

2.2.2.1 Guidelines for V_INT circuit design

SARA-R4/N4 series modules provide the V_INT generic digital interfaces 1.8 V supply output, which can be

mainly used to:
 Indicate when the module is switched on and it is not in the deep sleep power saving mode (as

described in sections 1.6.1, 1.6.2)

 Pull-up SIM detection signal (see section 2.5 for more details)
 Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. see

2.6.1)

 Enable external voltage regulators providing supply for external devices

☞ Do not apply loads which might exceed the maximum available current from V_INT supply (see SARA-

R4/N4 series Data Sheet [1]) as this can cause malfunctions in internal circuitry.

☞ V_INT can only be used as an output: do not connect any external supply source on V_INT.
☞ ESD sensitivity rating of the V_INT supply pin is 1 kV (HBM according to JESD22-A114). Higher protection

level could be required if the line is externally accessible and it can be achieved by mounting an ESD

protection (e.g. EPCOS CA05P4S14THSG) close to accessible point.

☞ It is recommended to monitor the V_INT pin to sense the end of the internal switch-off sequence of

SARA-R4/N4 series modules: VCC supply can be removed only after V_INT goes low.

☞ It is recommended to provide direct access to the V_INT pin on the application board by means of an

accessible test point directly connected to the V_INT pin.

UBX-16029218 - R11 Design-in Page 75 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/N4

15

PWR_ON

Power-on

push butt on

ESD

Open
Drain
Output

Application

Processor

SARA-R4/N4

15

PWR_ON

TP

TP

Reference

Description

Remarks

ESD

CT0402S14AHSG - EPCOS

Varistor array for ESD protection

2.3 System functions interfaces

2.3.1 Module power-on (PWR_ON)

2.3.1.1 Guidelines for PWR_ON circuit design

SARA-R4/N4 series PWR_ON input is equipped with an internal active pull-up resistor; an external pull-up

resistor is not required and should not be provided.

If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application

device. According to EMC/ESD requirements of the application, an additional ESD protection should be

provided close to the accessible point, as described in Figure 29 and Table 20.

☞ ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114).

Higher protection level can be required if the line is externally accessible on the application board, e.g.
if an accessible push button is directly connected to PWR_ON pin, and it can be achieved by mounting

an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to the accessible point.

An open drain or open collector output is suitable to drive the PWR_ON input from an application

processor, as described in Figure 29.

☞ PWR_ON input pin should not be driven high by an external device, as it may cause start up issues.

Figure 29: PWR_ON application circuits using a push button and an open drain output of an application processor

Table 20: Example ESD protection component for the PWR_ON application circuit

☞ It is recommended to provide direct access to the PWR_ON pin on the application board by means of

an accessible test point directly connected to the PWR_ON pin.

UBX-16029218 - R11 Design-in Page 76 of 157

SARA-R4/N4 series - System Integration Manual

2.3.1.2 Guidelines for PWR_ON layout design

The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on

and switch off the SARA-R4/N4 series modules. It is required to ensure that the voltage level is well defined

during operation and no transient noise is coupled on this line, otherwise the module might detect a

spurious power-on request.

UBX-16029218 - R11 Design-in Page 77 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/ N4

18

RESET_N

Power-on

push butt on

ESD

Open

Drain

Out put

Application

Processor

SARA-R4/N4

18

RESET_N

TP

TP

Reference

Description

Remarks

ESD

Varistor for ESD protection

CT0402S14AHSG - EPCOS

2.3.2 Module reset (RESET_N)

2.3.2.1 Guidelines for RESET_N circuit design

SARA-R4/N4 series RESET_N is equipped with an internal pull-up; an external pull-up resistor is not required.

If connecting the RESET_N input to a push button, the pin will be externally accessible on the application

device. According to EMC/ESD requirements of the application, an additional ESD protection device (e.g.

the EPCOS CA05P4S14THSG varistor) should be provided close to accessible point on the line connected

to this pin, as described in Figure 30 and Table 21.

☞ ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher protection

level can be required if the line is externally accessible on the application board, e.g. if an accessible
push button is directly connected to the RESET_N pin, and it can be achieved by mounting an ESD

protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point.

An open drain output or open collector output is suitable to drive the RESET_N input from an application

processor, as described in Figure 30.

☞ RESET_N input pin should not be driven high by an external device, as it may cause start up issues.

Figure 30: RESET_N application circuits using a push button and an open drain output of an application processor

Table 21: Example of ESD protection component for the RESET_N application circuits

☞ If the external reset function is not required by the customer application, the RESET_N input pin can be

left unconnected to external components, but it is recommended providing direct access on the
application board by means of an accessible test point directly connected to the RESET_N pin.

2.3.2.2 Guidelines for RESET_N layout design

The RESET_N circuit require careful layout due to the pin function: ensure that the voltage level is well

defined during operation and no transient noise is coupled on this line, otherwise the module might detect
a spurious reset request. It is recommended to keep the connection line to RESET_N pin as short as possible.

UBX-16029218 - R11 Design-in Page 78 of 157

SARA-R4/N4 series - System Integration Manual

2.4 Antenna interface

SARA-R4/N4 series modules provide an RF interface for connecting the external antenna: the ANT pin

represents the RF input/output for RF signals transmission and reception.

The ANT pin has a nominal characteristic impedance of 50  and must be connected to the physical

antenna through a 50  transmission line to allow clean transmission / reception of RF signals.

2.4.1 Antenna RF interface (ANT)

2.4.1.1 General guidelines for antenna selection and design

The antenna is the most critical component to be evaluated. Designers must take care of the antenna from

all perspective at the very start of the design phase when the physical dimensions of the application board

are under analysis/decision, since the RF compliance of the device integrating SARA-R4/N4 series modules

with all the applicable required certification schemes depends on antenna’s radiating performance.

Cellular antennas are typically available as:
 External antennas (e.g. linear monopole):

o External antennas basically do not imply physical restriction to the design of the PCB where the

SARA-R4/N4 series module is mounted.

o The radiation performance mainly depends on the antennas. It is required to select antennas with

optimal radiating performance in the operating bands.

o RF cables should be carefully selected to have minimum insertion losses. Additional insertion loss

will be introduced by low quality or long cable. Large insertion loss reduces both transmit and

receive radiation performance.

o A high quality 50  RF connector provides a clean PCB-to-RF-cable transition. It is recommended

to strictly follow the layout and cable termination guidelines provided by the connector

manufacturer.

 Integrated antennas (e.g. PCB antennas such as patches or ceramic SMT elements):

o Internal integrated antennas imply physical restriction to the design of the PCB: Integrated antenna

excites RF currents on its counterpoise, typically the PCB ground plane of the device that becomes

part of the antenna: its dimension defines the minimum frequency that can be radiated. Therefore,

the ground plane can be reduced down to a minimum size that should be similar to the quarter of

the wavelength of the minimum frequency that needs to be radiated, given that the orientation of

the ground plane relative to the antenna element must be considered. As numerical example, the

physical restriction to the PCB design can be considered as following:

Frequency = 750 MHz  Wavelength = 40 cm  Minimum GND plane size = 10 cm

o Radiation performance depends on the whole PCB and antenna system design, including product

mechanical design and usage. Antennas should be selected with optimal radiating performance in

the operating bands according to the mechanical specifications of the PCB and the whole product.

UBX-16029218 - R11 Design-in Page 79 of 157

SARA-R4/N4 series - System Integration Manual

o It is recommended to select a custom antenna designed by an antennas’ manufacturer if the required

ground plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm wide). The antenna

design process should begin at the start of the whole product design process

o It is highly recommended to strictly follow the detailed and specific guidelines provided by the

antenna manufacturer regarding correct installation and deployment of the antenna system,

including PCB layout and matching circuitry

o Further to the custom PCB and product restrictions, antennas may require tuning to obtain the

required performance for compliance with all the applicable required certification schemes. It is

recommended to consult the antenna manufacturer for the design-in guidelines for antenna

matching relative to the custom application

In both of cases, selecting external or internal antennas, these recommendations should be observed:

 Select an antenna providing optimal return loss (or VSWR) figure over all the operating frequencies.
 Select an antenna providing optimal efficiency figure over all the operating frequencies.
 Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency

figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified

in some countries (e.g. by FCC in the United States, as reported in the section 4.2.2).

2.4.1.2 Guidelines for antenna RF interface design

Guidelines for ANT pin RF connection design

A clean transition between the ANT pad and the application board PCB must be provided, implementing
the following design-in guidelines for the layout of the application PCB close to the ANT pad:

 On a multilayer board, the whole layer stack below the RF connection should be free of digital lines
 Increase GND keep-out (i.e. clearance, a void area) around the ANT pad, on the top layer of the

application PCB, to at least 250 µm up to adjacent pads metal definition and up to 400 µm on the area

below the module, to reduce parasitic capacitance to ground, as described in the left picture in Figure

31

 Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT pad if the top-

layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance to ground, as

described in the right picture in Figure 31

UBX-16029218 - R11 Design-in Page 80 of 157

SARA-R4/N4 series - System Integration Manual

Min.

250 µm

Min. 400 µm

GND

ANT

GND clearance

on buried layer very close to top layer

below ANT pad

GND clearance

on top layer

around ANT pad

35 µm

35 µm

35 µm

35 µm

270 µm

270 µm

760 µm

L1 Copper

L3 Copper

L2 Copper

L4 Copper

FR-4 dielectric

FR-4 dielectric

FR-4 dielectric

380 µm 500 µm500 µm

Figure 31: GND keep-out area on top layer around ANT pad and on very close buried layer below ANT pad

Guidelines for RF transmission line design

Any RF transmission line, such as the ones from the ANT pad up to the related antenna connector or up

to the related internal antenna pad, must be designed so that the characteristic impedance is as close as

possible to 50 .

RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from a

ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is sandwiched

between two parallel ground planes within a dielectric material). The micro strip, implemented as a coplanar

waveguide, is the most common configuration for printed circuit board.

Figure 32 and Figure 33 provide two examples of suitable 50  coplanar waveguide designs. The first

example of RF transmission line can be implemented in case of 4-layer PCB stack-up herein described, and

the second example of RF transmission line can be implemented in case of 2-layer PCB stack-up herein

described.

Figure 32: Example of 50  coplanar waveguide transmission line design for the described 4-layer board layup

UBX-16029218 - R11 Design-in Page 81 of 157

SARA-R4/N4 series - System Integration Manual

35 µm

35 µm

1510 µm

L2 Copper

L1 Copper

FR-4 dielectric

1200 µm 400 µm400 µm

Figure 33: Example of 50  coplanar waveguide transmission line design for the described 2-layer board layup

If the two examples do not match the application PCB stack-up, then the 50  characteristic impedance

calculation can be made using the HFSS commercial finite element method solver for electromagnetic

structures from Ansys Corporation, or using freeware tools like Avago / Broadcom AppCAD

(https://www.broadcom.com/appcad) taking care of the approximation formulas used by the tools for the

impedance computation.

To achieve a 50  characteristic impedance, the width of the transmission line must be chosen depending

on:

 the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 32 and Figure 33)
 the thickness of the dielectric material between the top layer (where the transmission line is routed) and

the inner closer layer implementing the ground plane (e.g. 270 µm in Figure 32, 1510 µm in Figure 33)

 the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material

in Figure 32 and Figure 33)

 the gap from the transmission line to the adjacent ground plane on the same layer of the transmission

line (e.g. 500 µm in Figure 32, 400 µm in Figure 33)

If the distance between the transmission line and the adjacent GND area (on the same layer) does not

exceed 5 times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50 

calculation.

Additionally to the 50  impedance, the following guidelines are recommended for transmission lines

design:
 Minimize the transmission line length: the insertion loss should be minimized as much as possible, in

the order of a few tenths of a dB,

 Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component

present on the RF transmission lines, if top-layer to buried layer dielectric thickness is below 200 µm, to

reduce parasitic capacitance to ground,

 The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible:

avoid abrupt changes of width and spacing to GND,

 Add GND stitching vias around transmission lines, as described in Figure 34,

UBX-16029218 - R11 Design-in Page 82 of 157

SARA-R4/N4 series - System Integration Manual

SARA module

SM A

connect or

SARA module

SM A

connect or

High-pass filt er

t o im prove

ESD imm unity

 Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer,

providing enough vias on the adjacent metal layer, as described in Figure 34,

 Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from

any sensitive circuit (as USB),

 Avoid stubs on the transmission lines,
 Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried metal

layer,

 Do not route microstrip lines below discrete component or other mechanics placed on top layer

Two examples of a suitable RF circuit design are illustrated in Figure 34, where the antenna detection circuit

is not implemented (if the antenna detection function is required by the application, follow the guidelines

for circuit and layout implementation detailed in section 2.4.2):
 In the first example shown on the left, the ANT pin is directly connected to an SMA connector by means

of a suitable 50  transmission line, designed with the appropriate layout.

 In the second example shown on the right, the ANT pin is connected to an SMA connector by means

of a suitable 50  transmission line, designed with the appropriate layout, with an additional high pass

filter to improve the ESD immunity at the antenna port. (The filter consists of a suitable series capacitor

and shunt inductor, for example the Murata GRM1555C1H150JA01 15 pF capacitor and the Murata

LQG15HN39NJ02 39 nH inductor with Self-Resonant Frequency ~1 GHz.).

Figure 34: Example of circuit and layout for antenna RF circuits on the application board

Guidelines for RF termination design

The RF termination must provide a characteristic impedance of 50  as well as the RF transmission line up
to the RF termination, to match the characteristic impedance of the ANT port.

UBX-16029218 - R11 Design-in Page 83 of 157

SARA-R4/N4 series - System Integration Manual

However, real antennas do not have a perfect 50  load on all the supported frequency bands. So to reduce

as much as possible any performance degradation due to antenna mismatching, the RF termination must

provide optimal return loss (or VSWR) figures over all the operating frequencies, as summarized in Table 7.

If an external antenna is used, the antenna connector represents the RF termination on the PCB:

 Use suitable a 50  connector providing a clean PCB-to-RF-cable transition.
 Strictly follow the connector manufacturer’s recommended layout, for example:

o SMA Pin-Through-Hole connectors require a GND keep-out (i.e. clearance, a void area) on all the

layers around the central pin up to the annular pads of the four GND posts, as shown in Figure 34

o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in the

area below the connector between the GND land pads.

 Cut out the GND layer under the RF connector and close to any buried vias, to remove stray capacitance

and thus keep the RF line at 50 , e.g. the active pad of UFL connector needs to have a GND keep-out

(i.e. clearance, a void area) at least on the first inner layer to reduce parasitic capacitance to ground.

If an integrated antenna is used, the integrated antenna represents the RF terminations. The following

guidelines should be followed:

 Use an antenna designed by an antenna manufacturer providing the best possible return loss (or VSWR).
 Provide a ground plane large enough according to the relative integrated antenna requirements. The

ground plane of the application PCB can be reduced down to a minimum size that must be similar to

one quarter of wavelength of the minimum frequency that needs to be radiated. As numerical example,

Frequency = 750 MHz  Wavelength = 40 cm  Minimum GND plane size = 10 cm

 It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna

manufacturer regarding correct installation and deployment of the antenna system, including the PCB

layout and matching circuitry.

 Further to the custom PCB and product restrictions, the antenna may require a tuning to comply with

all the applicable required certification schemes. It is recommended to consult the antenna manufacturer

for the design-in guidelines for the antenna matching relative to the custom application.

Additionally, these recommendations regarding the antenna system placement must be followed:

 Do not place the antenna within a closed metal case.
 Do not place the antenna in close vicinity to the end user since the emitted radiation in human tissue

is restricted by regulatory requirements.

 Place the antenna as far as possible from VCC supply line and related parts (refer to Figure 28), from

high speed digital lines (as USB) and from any possible noise source.

 Place the antenna far from sensitive analog systems or employ countermeasures to reduce EMC or EMI

issues.

 Be aware of interaction between co-located RF systems since the LTE transmitted power may interact

or disturb the performance of companion systems.

UBX-16029218 - R11 Design-in Page 84 of 157

SARA-R4/N4 series - System Integration Manual

UBX-16029218 - R11 Design-in Page 85 of 157

SARA-R4/N4 series - System Integration Manual

Manufacturer

Part Number

Product Name

Description

Taoglas

PA.710.A

Warrior

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz

40.0 x 6.0 x 5.0 mm

Taoglas

PCS.06.A

Havok

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2500..2690 MHz

42.0 x 10.0 x 3.0 mm

Taoglas

MCS6.A

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2690 MHz

42.0 x 10.0 x 3.0 mm

Antenova

SR4L002

Lucida

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz

35.0 x 8.5 x 3.2 mm

Ethertronics

P822601

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2490..2700 MHz

50.0 x 8.0 x 3.2 mm

Ethertronics

P822602

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2490..2700 MHz

50.0 x 8.0 x 3.2 mm

Ethertronics

1002436

GSM / WCDMA / LTE Vertical Mount Antenna

698..960 MHz, 1710..2700 MHz

50.6 x 19.6 x 1.6 mm

Pulse

W3796

Domino

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz

42.0 x 10.0 x 3.0 mm

TE Connectivity

2118310-1

GSM / WCDMA / LTE Vertical Mount Antenna

698..960 MHz, 1710..2170 MHz, 2300..2700 MHz

74.0 x 10.6 x 1.6 mm

Molex

1462000001

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1700..2700 MHz

40.0 x 5.0 x 5.0 mm

Cirocomm

DPAN0S07

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2500..2700 MHz

37.0 x 5.0 x 5.0 mm

Examples of antennas

Table 22 lists some examples of possible internal on-board surface-mount antennas.

Table 22: Examples of internal surface-mount antennas

UBX-16029218 - R11 Design-in Page 86 of 157

SARA-R4/N4 series - System Integration Manual

Manufacturer

Part Number

Product Name

Description

Taoglas

FXUB63.07.0150C

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz

96.0 x 21.0 mm

Taoglas

FXUB66.07.0150C

Maximus

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700

MHz, 3400..3600 MHz, 4800..6000 MHz

120.2 x 50.4 mm

Antenova

SRFL029

Moseni

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz

110.0 x 20.0 mm

Antenova

SRFL026

Mitis

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz

110.0 x 20.0 mm

Ethertronics

1002289

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

698..960 MHz, 1710..2700 MHz

140.0 x 75.0 mm

EAD

FSQS35241-UF-10

SQ7

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

690..960 MHz, 1710..2170 MHz, 2500..2700 MHz

110.0 x 21.0 mm

Manufacturer

Part Number

Product Name

Description

Taoglas

GSA.8827.A.101111

Phoenix

GSM / WCDMA / LTE adhesive-mount antenna with cable and SMA(M)

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz

105 x 30 x 7.7 mm

Taoglas

TG.30.8112

GSM / WCDMA / LTE swivel dipole antenna with SMA(M)

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz

148.6 x 49 x 10 mm

Taoglas

MA241.BI.001

Genesis

GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination antenna

waterproof IP67 rated with cable and SMA(M)

698..960 MHz, 1710..2170 MHz, 2400..2700 MHz

205.8 x 58 x 12.4 mm

Laird Tech.

TRA6927M3PW-001

GSM / WCDMA / LTE screw-mount antenna with N-type(F)

698..960 MHz, 1710..2170 MHz, 2300..2700 MHz

83.8 x Ø 36.5 mm

Laird Tech.

CMS69273

GSM / WCDMA / LTE ceiling-mount antenna with cable and N-type(F)

698..960 MHz, 1575.42 MHz, 1710..2700 MHz

Table 23 lists some examples of possible internal off-board PCB-type antennas with cable and connector.

Table 23: Examples of internal antennas with cable and connector

Table 24 lists some examples of possible external antennas.

UBX-16029218 - R11 Design-in Page 87 of 157

SARA-R4/N4 series - System Integration Manual

Manufacturer

Part Number

Product Name

Description

86 x Ø 199 mm

Laird Tech.

OC69271-FNM

GSM / WCDMA / LTE pole-mount antenna with N-type(M)

698..960 MHz, 1710..2690 MHz

248 x Ø 24.5 mm

Pulse

Electronics

WA700/2700SMA

GSM / WCDMA / LTE clip-mount MIMO antenna with cables and SMA(M)

698..960 MHz,1710..2700 MHz

149 x 127 x 5.1 mm

Application Board

Antenna Cable

SARA-R4/N4

56

ANT

62

ANT_DET

R1

C1 D1

L1

C2

J1

Z0= 50 Ω Z0= 50 Ω

Z0= 50 ohm

Antenna Assembly

R2

C4

L3

Radiat ing

Element

Diagnostic

Circuit

GND

L2

C3

Reference

Description

Part Number - Manufacturer

C1

27 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H270J - Murata

C2

33 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H330J - Murata

D1

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

L1

68 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HS68NJ02 - Murata

R1

10 k Resistor 0402 1% 0.063 W

RK73H1ETTP1002F - KOA Speer

J1

SMA Connector 50  Through Hole Jack

SMA6251A1-3GT50G-50 - Amphenol

C3

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150J - Murata

L2

39 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HN39NJ02 - Murata

C4

22 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1H220J - Murata

L3

68 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HS68NJ02 - Murata

Table 24: Examples of external antennas

2.4.2 Antenna detection interface (ANT_DET)

2.4.2.1 Guidelines for ANT_DET circuit design

Figure 35 and Table 25 describe the recommended schematic / components for the antenna detection

circuit that must be provided on the application board and for the diagnostic circuit that must be provided

on the antenna’s assembly to achieve antenna detection functionality.

Figure 35: Suggested schematic for antenna detection circuit on application PCB and diagnostic circuit on antenna assembly

UBX-16029218 - R11 Design-in Page 88 of 157

SARA-R4/N4 series - System Integration Manual

R2

15 k Resistor for Diagnostics

Various Manufacturers

Table 25: Suggested parts for antenna detection circuit on application PCB and diagnostic circuit on antennas assembly

The antenna detection circuit and diagnostic circuit suggested in Figure 35 and Table 25 are here explained:
 When antenna detection is forced by the +UANTR AT command, the ANT_DET pin generates a DC

current measuring the resistance (R2) from the antenna connector (J1) provided on the application

board to GND.

 DC blocking capacitors are needed at the ANT pin (C2) and at the antenna radiating element (C4) to

decouple the DC current generated by the ANT_DET pin.

 Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series at

the ANT_DET pin (L1) and in series at the diagnostic resistor (L3), to avoid a reduction of the RF

performance of the system, improving the RF isolation of the load resistor.

 Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR AT

command. It also acts as an ESD protection.

 Additional components (C1 and D1 in Figure 35) are needed at the ANT_DET pin as ESD protection.
 Additional high pass filter (C3 and L2 in Figure 35) is provided at the ANT pin as ESD immunity

improvement

 The ANT pin must be connected to the antenna connector by means of a transmission line with nominal

characteristics impedance as close as possible to 50 .

The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short

to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 35, the

measured DC resistance is always at the limits of the measurement range (respectively open or short), and

there is no mean to distinguish between a defect on antenna path with similar characteristics (respectively:

removal of linear antenna or RF cable shorted to GND for PIFA antenna).

Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element

will alter the measurement and produce invalid results for antenna detection.

☞ It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k

to assure good antenna detection functionality and avoid a reduction of module RF performance. The

choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to

improve the RF isolation of load resistor.

For example:

Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module

reports the resistance value evaluated from the antenna connector provided on the application board to

GND:

UBX-16029218 - R11 Design-in Page 89 of 157

SARA-R4/N4 series - System Integration Manual

 Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if

a 15 k diagnostic resistor is used) indicate that the antenna is correctly connected.

 Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit

“over range” report (see the SARA-R4/N4 series AT Commands Manual [2]) means that that the antenna

is not connected or the RF cable is broken.

 Reported values below the measurement range minimum limit (1 k) highlights a short to GND at

antenna or along the RF cable.

 Measurement inside the valid measurement range and outside the expected range may indicate an

unclean connection, a damaged antenna or incorrect value of the antenna load resistor for diagnostics.

 Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the

antenna assembly due to antenna cable length, antenna cable capacity and the used measurement

method.

☞ If the antenna detection function is not required by the customer application, the ANT_DET pin can be

left not connected and the ANT pin can be directly connected to the antenna connector by means of

a 50  transmission line as described in Figure 34.

UBX-16029218 - R11 Design-in Page 90 of 157

SARA-R4/N4 series - System Integration Manual

SARA module

C2

R1

D1
C1

L1

J1

C3 L2

2.4.2.2 Guidelines for ANT_DET layout design

Figure 36 describes the recommended layout for the antenna detection circuit to be provided on the

application board to achieve antenna detection functionality, implementing the recommended schematic

described in the previous Figure 35 and Table 25:
 The ANT pin must be connected to the antenna connector by means of a 50  transmission line,

implementing the design guidelines described in section 2.4.1 and the recommendations of the SMA

connector manufacturer.

 DC blocking capacitor at ANT pin (C2) must be placed in series to the 50  RF line.
 The ANT_DET pin must be connected to the 50  transmission line by means of a sense line.
 Choke inductor in series at the ANT_DET pin (L1) must be placed so that one pad is on the 50 

transmission line and the other pad represents the start of the sense line to the ANT_DET pin.

 The additional components (R1, C1 and D1) on the ANT_DET line must be placed as ESD protection.
 The additional high pass filter (C3 and L2) on the ANT line are placed as ESD immunity improvement

Figure 36: Suggested layout for antenna detection circuit on application board

UBX-16029218 - R11 Design-in Page 91 of 157

SARA-R4/N4 series - System Integration Manual

2.5 SIM interface

2.5.1 Guidelines for SIM circuit design

2.5.1.1 Guidelines for SIM cards, SIM connectors and SIM chips selection

The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical

and functional characteristics of Universal Integrated Circuit Cards (UICC), which contains the Subscriber

Identification Module (SIM) integrated circuit that securely stores all the information needed to identify and

authenticate subscribers over the LTE network.

Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as follows:

 Contact C1 = VCC (Supply)  It must be connected to VSIM
 Contact C2 = RST (Reset)  It must be connected to SIM_RST
 Contact C3 = CLK (Clock)  It must be connected to SIM_CLK
 Contact C4 = AUX1 (Auxiliary contact)  It must be left not connected
 Contact C5 = GND (Ground)  It must be connected to GND
 Contact C6 = VPP (Programming supply)  It can be left not connected
 Contact C7 = I/O (Data input/output)  It must be connected to SIM_IO
 Contact C8 = AUX2 (Auxiliary contact)  It must be left not connected

A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the auxiliary

contacts C4 and C8. Only 6 contacts are required and must be connected to the module SIM interface.

Removable SIM cards are suitable for applications requiring a change of SIM card during the product

lifetime.

A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it

can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch

integrated in the SIM connector for the mechanical card presence detection are provided. Select a SIM

connector providing 6+2 or 8+2 positions if the optional SIM detection feature is required by the custom

application, otherwise a connector without integrated mechanical presence switch can be selected.

Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as:

 Case Pin 8 = UICC Contact C1 = VCC (Supply)  It must be connected to VSIM
 Case Pin 7 = UICC Contact C2 = RST (Reset)  It must be connected to SIM_RST
 Case Pin 6 = UICC Contact C3 = CLK (Clock)  It must be connected to SIM_CLK
 Case Pin 5 = UICC Contact C4 = AUX1 (Aux.contact)  It must be left not connected
 Case Pin 1 = UICC Contact C5 = GND (Ground)  It must be connected to GND
 Case Pin 2 = UICC Contact C6 = VPP (Progr. supply)  It can be left not connected
 Case Pin 3 = UICC Contact C7 = I/O (Data I/O)  It must be connected to SIM_IO
 Case Pin 4 = UICC Contact C8 = AUX2 (Aux. contact)  It must be left not connected

UBX-16029218 - R11 Design-in Page 92 of 157

SARA-R4/N4 series - System Integration Manual

A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other uses,

but only 6 contacts are required and must be connected to the module SIM card interface as described

above.

Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once

installed.

2.5.1.2 Guidelines for single SIM card connection without detection

A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of SARA-

R4/N4 series modules as described in Figure 37, where the optional SIM detection feature is not

implemented.

Follow these guidelines to connect the module to a SIM connector without SIM presence detection:

 Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
 Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
 Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
 Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
 Connect the UICC / SIM contact C5 (GND) to ground.
 Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the

relative pad of the SIM connector, to prevent digital noise.

 Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line,

very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF

antenna is placed closer than 10 - 30 cm from the SIM card holder.

 Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on each

externally accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity rating of

the SIM interface pins is 1 kV (HBM). So that, according to EMC/ESD requirements of the custom

application, higher protection level can be required if the lines are externally accessible on the

application device.

 Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is

the maximum allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on data and

reset lines).

UBX-16029218 - R11 Design-in Page 93 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/ N4

41

VSIM

39

SIM_IO

38

SIM_CLK

40

SIM_RST

SIM CARD

HOLDER

C5C6C

7

C1C2C

3

SIM Card

Bott om View

(cont act s side)

C1

VPP (C6)

VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)

C2 C3 C5

J1

C4

D1 D2 D3 D4

C

8
C

4

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

C5

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1, D2, D3, D4

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

J1

SIM Card Holder, 6 p, without card presence

switch

Various manufacturers, as C707 10M006 136 2 - Amphenol

Figure 37: Application circuits for the connection to a single removable SIM card, with SIM detection not implemented

Table 26: Example of components for the connection to a single removable SIM card, with SIM detection not implemented

UBX-16029218 - R11 Design-in Page 94 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/N4

41

VSIM

39

SIM _IO

38

SIM _CLK

40

SIM _RST

SIM CHIP

SIM Chip

Bot tom View

(cont act s side)

C1

VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)

C2 C3 C5

U1

C4

2

8
3
6
7

1

C1 C5
C2 C6
C3 C7
C4 C8

8
7
6
5

1
2
3
4

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

C5

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

U1

SIM chip (M2M UICC Form Factor)

Various Manufacturers

2.5.1.3 Guidelines for single SIM chip connection

A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of the SARA-

R4/N4 series modules as described in Figure 38.

Follow these guidelines to connect the module to a solderable SIM chip without SIM presence detection:

 Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
 Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
 Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
 Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
 Connect the UICC / SIM contact C5 (GND) to ground.
 Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the

relative pad of the SIM chip, to prevent digital noise.

 Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line,

to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM

lines.

 Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is

the maximum allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on data and

reset lines).

Figure 38: Application circuits for the connection to a single solderable SIM chip, with SIM detection not implemented

Table 27: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented

2.5.1.4 Guidelines for single SIM card connection with detection

An application circuit for the connection to a single removable SIM card placed in a SIM card holder is

described in Figure 39, where the optional SIM card detection feature is implemented.

UBX-16029218 - R11 Design-in Page 95 of 157

SARA-R4/N4 series - System Integration Manual

SARA-R4/N4

41

VSIM

39

SIM_IO

38

SIM_CLK

40

SIM_RST

4

V_INT

42

GPIO5

SIM CARD

HOLDER

C5C6C

7

C1C2C

3

SIM Card

Bottom View

(contacts side)

C1

VPP (C6)

VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)

C2 C3 C5

J1

C4

SW1

SW2

D1 D2 D3 D4 D5 D6

R2

R1

C
8

C
4

TP

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection:

 Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
 Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
 Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
 Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
 Connect the UICC / SIM contact C5 (GND) to ground.
 Connect one pin of the normally-open mechanical switch integrated in the SIM connector (as the SW2

pin in Figure 39) to the GPIO5 input pin, providing a weak pull-down resistor (e.g. 470 k, as R2 in

Figure 39).

 Connect the other pin of the normally-open mechanical switch integrated in the SIM connector (SW1

pin in Figure 39) to V_INT 1.8 V supply output by means of a strong pull-up resistor (e.g. 1 k, as R1

in Figure 39)

 Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close

to the related pad of the SIM connector, to prevent digital noise.

 Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line

(VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the SIM connector, to prevent RF

coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder.

 Provide a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on

each externally accessible SIM line, close to each related pad of the SIM connector. The ESD sensitivity

rating of SIM interface pins is 1 kV (HBM according to JESD22-A114), so that, according to the EMC/ESD

requirements of the custom application, higher protection level can be required if the lines are externally

accessible.

 Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM

interface (18.7 ns = maximum rise time on SIM_CLK, 1.0 µs = maximum rise time on SIM_IO and

SIM_RST).

Figure 39: Application circuit for the connection to a single removable SIM card, with SIM detection implemented

UBX-16029218 - R11 Design-in Page 96 of 157

SARA-R4/N4 series - System Integration Manual

C5

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1 – D6

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

R1

1 k Resistor 0402 5% 0.1 W

RC0402JR-071KL - Yageo Phycomp

R2

470 k Resistor 0402 5% 0.1 W

RC0402JR-07470KL- Yageo Phycomp

J1

SIM Card Holder

6 + 2 positions, with card presence switch

Various Manufacturers,

CCM03-3013LFT R102 - C&K Components

Table 28: Example of components for the connection to a single removable SIM card, with SIM detection implemented

2.5.2 Guidelines for SIM layout design

The layout of the SIM card interface lines (VSIM, SIM_CLK, SIM_IO, SIM_RST may be critical if the SIM card

is placed far away from the SARA-R4/N4 series modules or in close proximity to the RF antenna: these two

cases should be avoided or at least mitigated as described below.

In the first case, the long connection can cause the radiation of some harmonics of the digital data frequency

as any other digital interface. It is recommended to keep the traces short and avoid coupling with RF line

or sensitive analog inputs.

In the second case, the same harmonics can be picked up and create self-interference that can reduce the

sensitivity of LTE receiver channels whose carrier frequency is coincidental with harmonic frequencies. It is

strongly recommended to place the RF bypass capacitors suggested in Figure 37 near the SIM connector.

In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges.

Add adequate ESD protection as suggested to protect module SIM pins near the SIM connector.

Limit capacitance and series resistance on each SIM signal to match the SIM specifications. The connections

should always be kept as short as possible.

Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some

harmonics of the digital data frequency.

UBX-16029218 - R11 Design-in Page 97 of 157

SARA-R4/N4 series - System Integration Manual

TxD

Applicat ion Processor

(1.8V DTE)

RxD
RTS
CTS
DTR

DSR

RI
DCD
GND

SARA-R4/N4

(1.8V DCE)

12

TXD

9

DTR

13

RXD

10

RTS

11

CTS

6

DSR

7

RI

8

DCD
GND

0Ω

TP

0Ω

TP

0Ω

TP

0Ω

TP

4

V_INT

TxD

Applicat ion Processor

(3.0V DTE)

RxD
RTS
CTS

DTR
DSR

RI

DCD

GND

SARA-R4/N4

(1.8V DCE)

12

TXD

9

DTR

13

RXD

10

RTS

11

CTS

6

DSR

7

RI

8

DCD

GND

1V8

B1 A1

GND

U1

B3A3

VCCBVCCA

Unid irect ional
Volt age Translat or

C1

C2

3V0

DIR3

DIR2 OE

DIR1

VCC

B2 A2

B4A4

DIR4

1V8

B1 A1

GND

U2

B3A3

VCCBVCCA

Unid irect ional
Volt age Translat or

C3

C4

3V0

DIR1

DIR3 OE

B2 A2

B4A4

DIR4

DIR2

TP

0Ω

TP

0Ω

TP

0Ω

TP

0Ω

TP

12

2.6 Data communication interfaces

2.6.1 UART interface

2.6.1.1 Guidelines for UART circuit design

Providing the full RS-232 functionality (using the complete V.24 link)12

If RS-232 compatible signal levels are needed, two different external voltage translators can be used to

provide full RS-232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for the

translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the translation from 3.3 V to RS-232

compatible signal level.

If a 1.8 V Application Processor (DTE) is used and complete RS-232 functionality is required, then the

complete 1.8 V UART of the module (DCE) should be connected to a 1.8 V DTE, as in Figure 40.

Figure 40: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART of the

module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output

as 1.8 V supply for the voltage translators on the module side, as described in Figure 41.

Figure 41: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)

Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on

‘00’ and ‘01’ versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

UBX-16029218 - R11 Design-in Page 98 of 157

SARA-R4/N4 series - System Integration Manual

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

U1, U2

Unidirectional Voltage Translator

SN74AVC4T77413 - Texas Instruments

TxD

Application Processor

(1.8V DTE)

RxD

RTS

CTS
DTR
DSR

RI

DCD
GND

SARA-R4/N4

(1.8V DCE)

12

TXD

9

DTR

13

RXD

10

RTS

11

CTS

6

DSR

7

RI

8

DCD
GND

0 Ω
0 Ω

TP
TP

0 Ω
0 Ω

TP
TP

13

14

Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)

Providing the TXD, RXD, RTS, CTS and DTR lines only 14

If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available:

 Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD

If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim

MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the

translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to RS-232

compatible signal level.

Figure 42 describes the circuit that should be implemented as if a 1.8 V Application Processor (DTE) is used,

given that the DTE will behave correctly regardless of the DSR input setting.

Figure 42: UART interface application circuit with partial V.24 link (6-wire) in the DTE/DCE serial communication (1.8 V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface

of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT

output as 1.8 V supply for the voltage translators on the module side, as described in Figure 43, given that
the DTE will behave correctly regardless of the DSR input setting.

Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply
Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on

‘00’ and ‘01’ versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

UBX-16029218 - R11 Design-in Page 99 of 157

SARA-R4/N4 series - System Integration Manual

4

V_INT

TxD

Application Processor

(3.0V DTE)

RxD
RTS
CTS

DTR
DSR

RI

DCD
GND

SARA-R4/N4

(1.8V DCE)

12

TXD

9

DTR

13

RXD

10

RTS

11

CTS

6

DSR

7

RI

8

DCD
GND

0 Ω
0 Ω

TP

TP
0 Ω
0 Ω

TP

TP

1V8

B1 A1

GND

U1

B3A3

VCCBVCCA

Unid irect ional

Volt age Tran slator

C1

C2

3V0

DIR3

DIR2 OE

DIR1

VCC

B2 A2

B4A4

DIR4

1V8

B1 A1

GND

U2

VCCBVCCA

Unid irect ional

Volt age Translat or

C3

3V0

DIR1

OE

B2 A2

DIR2

C4

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

U1

Unidirectional Voltage Translator

SN74AVC4T77415 - Texas Instruments

U2

Unidirectional Voltage Translator

SN74AVC2T24515 - Texas Instruments

15

16

Figure 43: UART interface application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE)

Table 30: UART application circuit components with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE)

Providing the TXD, RXD, RTS and CTS lines only 16

If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:

 Connect the module DTR input to GND using a 0  series resistor, since it may be useful to set DTR

active if not specifically handled, in particular to have URCs presented over the UART interface (see the

SARA-R4/N4 series AT Commands Manual [1] for the &D, S0, +CNMI AT commands)

 Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD

If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used.

This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application

Processor is used, the circuit should be implemented as described in Figure 44.

Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply
Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on

‘00’ and ‘01’ versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

UBX-16029218 - R11 Design-in Page 100 of 157