u-blox SARA-R4 User Manual

UBX-16029218 - R20 C1-Public www.u-blox.com

SARA-R4 series

Multi-band LTE-M / NB-IoT / EGPRS modules

System integration manual

Abstract

This document describes the features and the integration of the size-optimized SARA-R4 series cellular modules. These modules are a complete, cost efficient, performance optimized, multi-mode and multi band LTE-M / NB-IoT / EGPRS solution in the compact SARA form factor.

SARA-R4

SARA-R4 series - System integration manual

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Document information

Title

SARA-R4 series

Subtitle

Multi-band LTE-M / NB-IoT / EGPRS modules

Document type

System integration manual

Document number

UBX-16029218

Revision and date

R20

02-Apr-2021

Disclosure restriction

C1-Public

Product status

Corresponding content status

Functional sample

Draft

For functional testing. Revised and supplementary data will be published later.

In development / Prototype

Objective specification

Target values. Revised and supplementary data will be published later.

Engineering sample

Advance information

Data based on early testing. Revised and supplementary data will be published later.

Initial production

Early production information

Data from product verification. Revised and supplementary data may be published later.

Mass production / End of life

Production information

Document contains the final product specification.

This document applies to the following products:

Product name

Type number

Modem version

Application version

PCN reference

Product status

SARA-R410M

SARA-R410M-01B-00

L0.0.00.00.02.03

UBX-18059854

Obsolete

SARA-R410M-02B-00

L0.0.00.00.05.06

A02.00

UBX-18010263

Obsolete

L0.0.00.00.05.06

A02.01

UBX-18070443

Obsolete

SARA-R410M-02B-01

L0.0.00.00.05.08

A02.04

UBX-19041392

Mass production

SARA-R410M-02B-02

L0.0.00.00.05.11

A.02.16

UBX-20033274

Mass production

SARA-R410M-02B-03

L0.0.00.00.05.12

A.02.19

UBX-20058104

Initial production

SARA-R410M-52B-00

L0.0.00.00.06.05

A02.06

UBX-18045915

Obsolete

SARA-R410M-52B-01

L0.0.00.00.06.08

A02.11

UBX-19024506

Mass production

SARA-R410M-52B-02

L0.0.00.00.06.11

A.02.16

UBX-20033274

Mass production

SARA-R410M-63B-00

L0.08.12

A.01.11

UBX-20006293

End of life

SARA-R410M-63B-01

L0.08.12

A.01.12

UBX-20053055

Initial production

SARA-R410M-73B-00

L0.08.12

A.01.11

UBX-20006294

End of life

SARA-R410M-73B-01

L0.08.12

A.01.12

UBX-20049254

Initial production

SARA-R410M-83B-00

L0.08.12

A01.11

UBX-20027231

End of life

SARA-R410M-83B-01

L0.08.12

A.01.12

UBX-20049255

Initial production

SARA-R412M

SARA-R412M-02B-00

M0.09.00

A.02.11

UBX-19004091

Obsolete

SARA-R412M-02B-01

M0.10.00

A.02.14

UBX-19016568

Mass production

SARA-R412M-02B-02

M0.11.01

A.02.17

UBX-20031249

Mass production

SARA-R412M-02B-03

M0.12.00

A.02.19

UBX-20058105

Initial production

SARA-R422

SARA-R422-00B-00

00.10

A00.00

UBX-21007232

Engineering sample 2

SARA-R422S

SARA-R422S-00B-00

00.10

A00.00

UBX-21007232

Engineering sample 2

SARA-R422M8S

SARA-R422M8S-00B-00

00.10

A00.00

UBX-21007232

Engineering sample 2

u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. Copyright © u-blox AG.

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Document information ................................................................................................................................ 2

Contents .......................................................................................................................................................... 3

1 System description ............................................................................................................................... 6

1.1 Overview ........................................................................................................................................................ 6

1.2 Architecture ...............................................................................................................................................10

1.3 Pin-out .........................................................................................................................................................13

1.4 Operating modes .......................................................................................................................................18

1.5 Supply interfaces ......................................................................................................................................21

1.5.1 Module supply input (VCC) .............................................................................................................21

1.5.2 Generic digital interfaces supply output (V_INT) .......................................................................27

1.6 System function interfaces ....................................................................................................................28

1.6.1 Module power-on ..............................................................................................................................28

1.6.2 Module power-off ..............................................................................................................................29

1.6.3 Module reset ......................................................................................................................................31

1.7 Antenna interfaces ...................................................................................................................................32

1.7.1 Cellular antenna RF interface (ANT) .............................................................................................32

1.7.2 GNSS antenna RF interface (ANT_GNSS) ...................................................................................33

1.7.3 Antenna detection interface (ANT_DET).....................................................................................34

1.8 SIM interface ..............................................................................................................................................34

1.8.1 SIM interface .....................................................................................................................................34

1.8.2 SIM detection interface ...................................................................................................................34

1.9 Data communication interfaces ............................................................................................................35

1.9.1 UART interfaces ................................................................................................................................35

1.9.2 USB interface .....................................................................................................................................37

1.9.3 SPI interface ......................................................................................................................................38

1.9.4 SDIO interface ...................................................................................................................................38

1.9.5 DDC (I2C) interface ...........................................................................................................................38

1.10 Audio ............................................................................................................................................................39

1.11 General Purpose Input/Output ...............................................................................................................39

1.12 GNSS peripheral input output ................................................................................................................40

1.13 Reserved pins (RSVD) ..............................................................................................................................40

2 Design-in ................................................................................................................................................ 41

2.1 Overview ......................................................................................................................................................41

2.2 Supply interfaces ......................................................................................................................................42

2.2.1 Module supply (VCC) ........................................................................................................................42

2.2.2 Generic digital interfaces supply output (V_INT) .......................................................................58

2.3 System functions interfaces ..................................................................................................................59

2.3.1 Module PWR_ON / PWR_CTRL input ............................................................................................59

2.3.2 Module RESET_N input ...................................................................................................................60

2.4 Antenna interfaces ...................................................................................................................................61

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2.4.1 General guidelines for antenna interfaces ..................................................................................61

2.4.2 Cellular antenna RF interface (ANT) .............................................................................................65

2.4.3 GNSS antenna RF interface (ANT_GNSS) ...................................................................................68

2.4.4 Cellular and GNSS RF coexistence ................................................................................................72

2.4.5 Antenna detection interface (ANT_DET).....................................................................................75

2.5 SIM interface ..............................................................................................................................................78

2.5.1 Guidelines for SIM circuit design ...................................................................................................78

2.5.2 Guidelines for SIM layout design ...................................................................................................82

2.6 Data communication interfaces ............................................................................................................83

2.6.1 UART interface ..................................................................................................................................83

2.6.2 USB interface .....................................................................................................................................88

2.6.3 SPI interface ......................................................................................................................................91

2.6.4 SDIO interface ...................................................................................................................................91

2.6.5 DDC (I2C) interface ...........................................................................................................................91

2.7 Audio ............................................................................................................................................................94

2.7.1 Guidelines for Audio circuit design ................................................................................................94

2.8 General Purpose Input/Output ...............................................................................................................94

2.8.1 Guidelines for GPIO circuit design .................................................................................................94

2.8.2 Guidelines for general purpose input/output layout design ....................................................95

2.9 GNSS peripheral input output ................................................................................................................95

2.9.1 Guidelines for GNSS peripheral input output circuit design ....................................................95

2.9.2 Guidelines for GNSS peripheral input output layout design ....................................................95

2.10 Reserved pins (RSVD) ..............................................................................................................................96

2.11 Module placement ....................................................................................................................................96

2.12 Module footprint and paste mask .........................................................................................................97

2.13 Thermal guidelines ...................................................................................................................................98

2.14 Schematic for SARA-R4 series module integration ..........................................................................99

2.14.1 Schematic for SARA-R4 series modules .....................................................................................99

2.15 Design-in checklist ................................................................................................................................. 100

2.15.1 Schematic checklist ...................................................................................................................... 100

2.15.2 Layout checklist ............................................................................................................................. 100

2.15.3 Antenna checklist .......................................................................................................................... 101

3 Handling and soldering ................................................................................................................... 102

3.1 Packaging, shipping, storage and moisture preconditioning ....................................................... 102

3.2 Handling ................................................................................................................................................... 102

3.3 Soldering .................................................................................................................................................. 103

3.3.1 Soldering paste .............................................................................................................................. 103

3.3.2 Reflow soldering ............................................................................................................................. 103

3.3.3 Optical inspection .......................................................................................................................... 104

3.3.4 Cleaning ........................................................................................................................................... 104

3.3.5 Repeated reflow soldering ........................................................................................................... 105

3.3.6 Wave soldering ............................................................................................................................... 105

3.3.7 Hand soldering ............................................................................................................................... 105

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3.3.8 Rework ............................................................................................................................................. 105

3.3.9 Conformal coating ......................................................................................................................... 105

3.3.10 Casting ............................................................................................................................................. 105

3.3.11 Grounding metal covers ............................................................................................................... 106

3.3.12 Use of ultrasonic processes ........................................................................................................ 106

4 Approvals ............................................................................................................................................. 107

4.1 Product certification approval overview ............................................................................................ 107

4.2 US Federal Communications Commission notice ........................................................................... 111

4.2.1 Safety warnings review the structure ....................................................................................... 111

4.2.2 Declaration of Conformity ............................................................................................................ 112

4.2.3 Modifications .................................................................................................................................. 113

4.3 Innovation, Science, Economic Development Canada notice ....................................................... 114

4.3.1 Declaration of Conformity ............................................................................................................ 114

4.3.2 Modifications .................................................................................................................................. 115

4.4 European Conformance CE mark ....................................................................................................... 116

4.5 National Communication Commission Taiwan ............................................................................... 117

4.6 ANATEL Brazil ........................................................................................................................................ 118

4.7 Australian Conformance ...................................................................................................................... 118

4.8 GITEKI Japan .......................................................................................................................................... 118

4.9 KC South Korea ...................................................................................................................................... 118

5 Product testing ................................................................................................................................. 119

5.1 u-blox in-series production test .......................................................................................................... 119

5.2 Test parameters for OEM manufacturers ........................................................................................ 120

5.2.1 “Go/No go” tests for integrated devices ................................................................................... 120

5.2.2 RF functional tests ........................................................................................................................ 120

Appendix ..................................................................................................................................................... 122

A Migration between SARA modules ............................................................................................. 122

B Glossary ............................................................................................................................................... 122

Related documentation ......................................................................................................................... 125

Revision history ........................................................................................................................................ 126

Contact ........................................................................................................................................................ 128

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1 System description

1.1 Overview

The SARA-R4 series modules are a multi-band LTE-M / NB-IoT / EGPRS multi-mode solution in the miniature SARA LGA form factor (26.0 x 16.0 mm, 96-pin). They allow an easy integration into compact designs and a seamless drop-in migration from other u-blox cellular module families.

SARA-R4 series modules provide software-based multi-band configurability enabling international multi-regional coverage in LTE-M / NB-IoT and (E)GPRS radio access technologies.

SARA-R4 series modules offer data communications over an extended operating temperature range of –40 °C to +85 °C, with low power consumption, and with coverage enhancement for deeper range into buildings and basements (and underground with NB-IoT).

SARA-R4 series modules are form-factor compatible with the u-blox LISA, LARA and TOBY cellular module families and are pin-to-pin compatible with the u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates migration from other u-blox LPWA, GSM/GPRS, CDMA, UMTS/HSPA and higher LTE categories modules, maximizing customer investments, simplifying logistics, and enabling very short time-to-market.

With many interface options and an integrated IP stack, SARA-R4 series modules are the optimal choice for LPWA applications with low to medium data throughput rates, as well as devices that require long battery lifetimes, such as used in smart metering, smart lighting, telematics, asset tracking, remote monitoring, alarm panels, and connected health.

Secure cloud product versions are available within the SARA-R4 series modules, including a unique and immutable root-of-trust. This provides the foundation for a trusted set of advanced security functionalities. The scalable, pre-shared key management system offers best-in-class data encryption and decryption, both on-device as well as from device-to-cloud. Utilizing the latest (D)TLS stack and cipher suites with hardware-based crypto acceleration provides robust, efficient, and protected communication.

Furthermore, the SARA-R422 series modules support a comprehensive set of 3GPP Rel. 14 features for LTE Cat M1 and Cat NB2 that are relevant for IoT applications.

The dedicated SARA-R422M8S module is pre-integrated with the u-blox M8 GNSS receiver chip and a separate GNSS antenna interface which provides highly reliable, accurate positioning data simultaneously with LTE communication. In addition, the module offers unique hybrid positioning, in which the GNSS position is enhanced with u-blox CellLocate® data, providing location always and everywhere.

Customers can future-proof their solutions by means of Over-The-Air firmware updates, thanks to the uFOTA client/server solution that utilizes LWM2M, a light and compact protocol ideal for IoT.

SARA-R4 series modules will also support VoLTE over Cat M1 and CSFB over 2G RAT. The flexibility extends further through dynamic mode selection as M1-only/preferred or NB-IoT-only/preferred.

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Product version

Region

RAT

Positioning

Interfaces

Features

Grade

3GPP release baseline 3GPP L

TE category

LTE FDD

bands

(E)GPRS 4

-band

Integrated GNSS receiver External GNSS control via modem AssistNow software CellLocate® UART

USB

SPI

SDIO

DDC (I2C) GPIOs

I2S audio interface Security services Root of trust: secure element Ultra-low power consum

ption in PSM

Embedded TCP/UDP stack Embedded HTTPS, FTPS, TLS DTLS

FW update via serial u-blox Firmware update

Over the Air

(uFOTA) LwM2M device management MQTT / MQTT

-SN

Last gasp Jamming detection Antenna and SIM detection Standard Professional Automoti

SARA-R410M-01B

North

America

2,4

5,12

● ●

●

● ● ● ● ● ● ● ●

SARA-R410M-02B

Multi region

NB1

● ● ● ● ●

●

● ● ● ● ● ● ● ● ● ●

SARA-R410M-52B

North

America

2,4,5

12,13

●

● ●

●

● ● ● ● ● ● ● ● ● ●

SARA-R410M-63B

Japan

1,8,19

● ● ● ● ●

●

● ● ● ● ● ● ● ● ● ● ● ● ● ●

SARA-R410M-73B

Korea

3,5

● ● ● ● ●

●

● ● ● ● ● ● ● ● ● ● ● ● ● ●

SARA-R410M-83B

APAC

Multi Region

NB1

3,5,8

20,28

● ● ● ● ●

● ● ● ● ● ● ● ● ● ● ● ●

● ● ●

SARA-R412M-02B

Multi region

NB1

** ●

● ● ● ● ●

● ● ● ● ● ● ● ● ●

● ● ●

SARA-R422-00B

Multi region

NB2

*** ●

● ■

● ● ● ● ● ● ● ●

● ●

SARA-R422S-00B

Multi region

NB2

*** ●

● ● ● ● ■

● ● ○ ● ● ● ● ● ● ● ● ● ● ● ●

● ●

SARA-R422M8S-00B

Multi region

NB2

***

●

● ● ● ●

■

● ● ○ ● ● ● ● ● ● ● ● ● ● ● ●

● ●

● = supported by available FW version ■ = supported for FW update and diagnostic only ○ = supported by future FW versions

* = LTE bands may include 1, 2, 3, 4, 5, 8, 12, 13, 18, 19, 20, 25, 26, 28 ** = LTE bands may include 2, 3, 4, 5, 8, 12, 13, 20, 26, 28 *** = LTE bands include 1, 2, 3, 4, 5, 8, 12, 13, 20, 25, 26, 28, 66, 85 in M1 and NB2

Table 1: SARA-R4 series main features summary

☞ See Table 2 for the detailed list of Radio Access Technologies (RATs) and bands supported by each

product version of the SARA-R4 series modules.

☞ See Table 48 and Table 49 for the detailed list of RATs and bands included in each certification

approval of the SARA-R4 series modules product versions.

☞ See Table 50 for the model / marketing name of each product variant of the SARA-R4 series

modules, as identified by various certification bodies.

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SARA-R4 series modules include the following variants / product versions:

• SARA-R410M-01B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12

• SARA-R410M-02B LTE Cat M1 / NB1 module,

mainly designed for operation in LTE bands 1, 2, 3, 4, 5, 8, 12, 13, 18, 19, 20, 25, 26, 28

• SARA-R410M-52B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12, 13

• Secure Cloud SARA-R410M-63B LTE Cat M1 module,

mainly designed for operation in LTE bands 1, 8, 19

• Secure Cloud SARA-R410M-73B LTE Cat M1 module,

mainly designed for operation in LTE bands 3, 5, 26

• Secure Cloud SARA-R410M-83B LTE Cat M1 / NB1 module,

mainly designed for operation in LTE bands 3, 5, 8, 20, 28

• SARA-R412M-02B LTE Cat M1 / NB1 and 2G module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28 and 2G 4-band

• SARA-R422 LTE Cat M1 / NB2 and 2G module,

designed for operation in LTE bands 1, 2, 3, 4, 5, 8, 12, 13, 20, 25, 26, 28, 66, 85 and 2G 4-band

• Secure Cloud SARA-R422 LTE Cat M1 / NB2 and 2G module,

designed for operation in LTE bands 1, 2, 3, 4, 5, 8, 12, 13, 20, 25, 26, 28, 66, 85 and 2G 4-band

• Secure Cloud SARA-R422M8 LTE Cat M1 / NB2 and 2G module, integrating UBX-M8 GNSS,

designed for operation in LTE bands 1, 2, 3, 4, 5, 8, 12, 13, 20, 25, 26, 28, 66, 85 and 2G 4-band

Table 2 summarizes cellular radio access technologies characteristics and features of the modules.

☞ See Table 48 and Table 49 for the detailed list of RATs and bands included in each certification

approval of the SARA-R4 series modules product versions.

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Item

SARA-R410M

SARA-R412M

SARA-R422 /-R422S /-R422M8S

Protocol stack

3GPP Release 13

3GPP Release 14

RAT

LTE Cat M1 LTE Cat NB1

1, 3, 4, 6

LTE Cat M1 LTE Cat NB1 2G GPRS / EGPRS

LTE FDD bands

Band 1 (2100 MHz)

1, 4, 7

Band 2 (1900 MHz)

6, 7

Band 3 (1800 MHz)

1, 4

Band 4 (1700 MHz)

6, 7

Band 5 (850 MHz) Band 8 (900 MHz)

1, 4

Band 12 (700 MHz)

6, 7

Band 13 (750 MHz)

1, 6, 7

Band 18 (850 MHz)

1, 3, 4, 6, 7

Band 19 (850 MHz)

1, 3, 4, 7

Band 20 (800 MHz)

1, 4, 6

Band 25 (1900 MHz)

1, 2, 3, 4, 5, 6, 7

Band 26 (850 MHz)

1, 3, 4, 7

Band 28 (700 MHz)

1, 4, 6

Band 2 (1900 MHz) Band 3 (1800 MHz) Band 4 (1700 MHz) Band 5 (850 MHz) Band 8 (900 MHz) Band 12 (700 MHz) Band 13 (750 MHz) Band 20 (800 MHz) Band 26 (850 MHz) 8 Band 28 (700 MHz) 8

Band 1 (2100 MHz) Band 2 (1900 MHz) Band 3 (1800 MHz) Band 4 (1700 MHz) Band 5 (850 MHz) Band 8 (900 MHz) Band 12 (700 MHz) Band 13 (750 MHz) Band 20 (800 MHz) Band 25 (1900 MHz) Band 26 (850 MHz) Band 28 (700 MHz) Band 66 (1700 MHz) Band 85 (700 MHz)

2G bands

GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz

Power class

LTE Cat M1 / NB19:

Class 3 (23 dBm)

LTE category M1 / NB1:

Class 3 (23 dBm)

2G GMSK:

Class 4 (33 dBm) in 850/900, Class 1 (30 dBm) in 1800/1900

2G 8-PSK:

Class E2 (27 dBm) in 850/900, Class E2 (26 dBm) in 1800/1900

LTE category M1 / NB2:

Class 3 (23 dBm)

2G GMSK:

Class 4 (33 dBm) in 850/900, Class 1 (30 dBm) in 1800/1900

2G 8-PSK:

Class E2 (27 dBm) in 850/900, Class E2 (26 dBm) in 1800/1900

Data rate

LTE category M1:

up to 375 kb/s UL, 300 kb/s DL

LTE category NB19:

up to 62.5 kb/s UL, 27.2 kb/s DL

LTE category M1:

up to 375 kb/s UL, 300 kb/s DL

LTE category NB1:

up to 62.5 kb/s UL, 27.2 kb/s DL

GPRS multi-slot class 3310:

up to 85.6 kb/s UL, 107 kb/s DL

EGPRS multi-slot class 3310:

up to 236.8 kb/s UL, 296 kb/s DL

LTE category M1: up to 1119 kbit/s UL, 588 kbit/s DL

LTE category NB2: up to 158.5 kbit/s UL, 127 kbit/s DL GPRS multi-slot class 3310:

up to 85.6 kb/s UL, 107 kb/s DL

EGPRS multi-slot class 3310:

up to 236.8 kb/s UL, 296.0 kb/s DL

GNSS receiver

SARA-R422M8S only: 72-channel, u-blox M8 engine GPS L1C/A, SBAS L1C/A, QZSS L1C/A, QZSS L1-SAIF, GLONASS L10F, BeiDou B1I, Galileo E1B/C

Table 2: SARA-R4 series modules cellular and GNSS characteristics summary

Not supported by the SARA-R410M-01B product version.

Not supported by the SARA-R410M-02B-00 product version.

Not supported by the SARA-R410M-52B-00 product version.

Not supported by the SARA-R410M-52B-01 and SARA-R410M-52B-02 product version.

Not supported in LTE Cat NB1 by SARA-R410M-02B-01, SARA-R410M-02B-02, or SARA-R410M-02B-03 product versions.

Not supported by the SARA-R410M-63B or SARA-R410M-73B product versions.

Not supported by the SARA-R410M-83B product version.

Not supported by the SARA-R412M-02B-00 product version.

LTE Cat NB1 not supported by SARA-R410M-01B, SARA-R410M-52B, SARA-R410M-63B, or SARA-R410M-73B versions.

GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total.

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1.2 Architecture

Figure 1 summarizes the internal architecture of SARA-R410M and SARA-R412M modules.

Memory

V_INT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UART

Power-on

Reset

GPIOs

Antenna detection

19.2 MHz

Cellular BaseBand Processor

Power

Management

SDIO

SPI / Digital audio

ANT

Switch

PAs

transceiver

Filters

Figure 1: SARA-R410M and SARA-R412M modules simplified block diagram

☞ The SARA-R410M-01B modules, i.e. the “01B” product version of the SARA-R410M modules, do

not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o DDC (I2C) interface o SDIO interface o SPI interface o Digital audio interface

☞ The SARA-R410M-02B, the SARA-R410M-52B, the SARA-R410M-63B, the SARA-R410M-73B,

the SARA-R410M-83B, the SARA-R412M-02B modules, i.e. the “02B”, “52B”, “63B”, “73B” and “83B” product versions of the SARA-R410M and SARA-R412M modules, do not support the

following interfaces, which should be left unconnected and should not be driven by external devices:

o SDIO interface o SPI interface o Digital audio interface

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Figure 2 summarizes the internal architecture of SARA-R422 and SARA-R422S modules.

Memory

V_INT

ANT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UARTs

Power-control

GPIOs

Antenna detection

Switch

PAs

transceiver

19.2 MHz

Cellular

BaseBand

Processor

Power

Management

Digital audio

Filters

Figure 2: SARA-R422 and SARA-R422S modules simplified block diagram

Figure 3 summarizes the internal architecture of SARA-R422M8S modules.

Memory

V_INT

ANT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UARTs

Power-control

GPIOs

Antenna detection

Switch

PAs

transceiver

19.2 MHz

Cellular

BaseBand

Processor

Power

Management

Digital audio

ANT_GNSS

SAW

LNA

UBX-M8

GNSS chipset

TIMEPULSE

EXTINT

ANT_ON

Filters

TCXO

26 MHz

TXD_GNSS

Figure 3: SARA-R422M8S modules simplified block diagram

☞ SARA-R422-00B, SARA-R422S-00B and SARA-R422M8S-00B modules, i.e. the “00B” product

versions of SARA-R422, SARA-R422S and SARA-R422M8S modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o Digital audio interface

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SARA-R4 series modules internally consist of the following sections described herein with more details than the simplified block diagrams of Figure 1, Figure 2 and Figure 3.

RF section

The RF section is composed of the following main elements:

• RF switch connecting the antenna port (ANT) to the suitable RF Tx / Rx paths for LTE Cat M1 /

NB-IoT Half-Duplex operations

• Power Amplifiers (PA) amplifying the Tx signal modulated and pre-amplified by the RF transceiver

• RF filters along the Tx and Rx signal paths providing RF filtering

• RF transceiver, performing modulation, up-conversion and pre-amplification of the baseband

signals for LTE transmission, and performing down-conversion and demodulation of the RF signal for LTE reception

• 19.2 MHz Temperature-Controlled Crystal Oscillator (TCXO) generating the reference clock signal

for the RF transceiver and the baseband system, when the related system is in active mode or connected mode.

Baseband and power management section

The baseband and power management section, is composed of the following main elements:

• On-chip modem processor, vector signal processor, with dedicated hardware assistance for signal

processing and system timing

• On-chip modem processor, with interfaces control functions

• On-chip voltage regulators to derive all the internal or external (V_SIM, V_INT) supply voltages

from the module supply input VCC

• Dedicated flash memory IC

• 32.768 kHz crystal oscillator to provide the clock reference in the low power idle mode, which can

be enabled using the +UPSV AT command, and in the PSM deep-sleep mode, which can be enabled using the +CPSMS AT command

GNSS section (SARA-R422M8S modules only)

The GNSS section, is composed of the following main elements illustrated in Figure 4:

• u-blox UBX-M8030-CT concurrent GNSS chipset with SPG 3.01 firmware version

• Dedicated SAW filter

• Additional Low Noise Amplifier (LNA)

• 26 MHz Temperature-Controlled Crystal Oscillator (TCXO) generating the reference clock signal

for the GNSS system

ANT_GNSS

UART1 UART2

Base Band

Processor

Power

Management

Flash memory

SAW

LNA

UBX-M8030

GNSS chipset

LNA_EN (PIO16)

RF_IN

V_BCKPVCC 26 MHz

VCC

RTC

19.2 MHz

SQI

EXTINT

TIMEPULSE

TCXO

ANT_ON

Time-Pulse (PIO11)

Ext-Int (PIO13)

Tx-Ready (PIO15)

I2C (PIO8/PIO9)

Cellular chipset

TXD (PIO6)

TXD_GNSS

Power ClockCtrl

SARA-R422M8S

Figure 4: SARA-R422M8S modules GNSS section block diagram

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1.3 Pin-out

Table 3 lists the pin-out of the SARA-R4 series modules, with pins grouped by function.

Function

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

51,52,53

Module supply input

VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes.

See section 1.5.1 for functional description / requirements. See section 2.2.1 for external circuit design-in.

GND

1,3,5,14, 20-22,30, 32,43,50, 54,55, 57-61, 63-96

N/A

Ground

GND pins are internally connected each other. External ground connection affects the RF and thermal

performance of the device. See section 1.5.1 for functional description. See section 2.2.1 for external circuit design-in.

V_INT

Generic digital interfaces supply output

V_INT = 1.8 V (typical) generated by internal regulator when the module is switched on, outside the low power PSM deep sleep mode.

Test-Point for diagnostic / FW update strongly recommended. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.

System

PWR_ON11

Power-on / -off input

Internal 200 k pull-up resistor. Test-Point for diagnostic / FW update strongly recommended. See section 1.6.1 and 1.6.2 for functional description. See section 2.3.1 for external circuit design-in.

PWR_CTRL12

Power-on / -off / Reset input

Internal pull-up resistor. Test-Point for diagnostic / FW update strongly recommended. See section 1.6.1, 1.6.2 and 1.6.3 for functional description. See section 2.3.1 for external circuit design-in.

RESET_N11

18 I Reset input

Internal 37 k pull-up resistor. Test-Point for diagnostic access is recommended. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in.

Antenna

ANT

I/O

Cellular antenna RF input/output

RF input/output for external Cellular antenna. 50  nominal characteristic impedance. Antenna circuit affects the RF performance and application

device compliance with required certification schemes. See section 1.7.1 for functional description / requirements. See section 2.4 for external circuit design-in.

ANT_GNSS13

GNSS antenna RF input

RF input for external GNSS antenna. 50  nominal characteristic impedance. See section 1.7.2 for functional description / requirements.

See section 2.4.3 for external circuit design-in.

ANT_DET

62 I Antenna detection

ADC for antenna presence detection function See section 1.7.3 for functional description. See section 2.4.5 for external circuit design-in.

SARA-R410M, SARA-R412M modules only

SARA-R422, SARA-R422S, SARA-R422M8S modules only

SARA-R422M8S modules only

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Function

Pin Name

Pin No

I/O

Description

Remarks

SIM

VSIM

41 O SIM supply output

Supply output for external SIM / UICC. See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_IO

I/O

SIM data

Data input/output for external SIM / UICC. Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_CLK

38 O SIM clock

Clock output for external SIM / UICC See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_RST

40 O SIM reset

Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in.

UART

RXD

13 O UART data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for AT commands, data communication, FOAT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

TXD

12 I UART data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT commands, data communication, FOAT. Internal pull-down to GND on the SARA-R410M-02B version Internal pull-up to V_INT on other product versions See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

CTS

UART clear to send output

1.8 V output, Circuit 106 (CTS) in ITU-T V.24. Not supported by SARA-R410M-01B, SARA-R410M-02B-00. See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

RTS

UART ready to send input

1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. Not supported by SARA-R410M-01B, SARA-R410M-02B-00. See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DSR

O / I UART DSR / AUX UART RTS

1.8 V, Circuit 107 (Data Set Ready output) in ITU-T V.24, configurable as Second Auxiliary UART RTS input.14

See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

O / O UART RI / AUX UART CTS

1.8 V, Circuit 125 (Ring Indicator output) in ITU-T V.24, configurable as Second Auxiliary UART CTS output.14

See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DTR

I / I UART DTR / AUX UART input

1.8 V, Circuit 108/2 (Data Terminal Ready input) in ITU-T V.24, configurable as Second Auxiliary UART data input.14

Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DCD

O / O UART DCD / AUX UART output

1.8 V, Circuit 109 (Data carrier detect output) in ITU-T V.24, configurable as Second Auxiliary UART data output.14 See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

The Second Auxiliary UART interface is not supported by SARA-R410M and SARA-R412M modules

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Function

Pin Name

Pin No

I/O

Description

Remarks

USB

VUSB_DET15

17 I USB detect input

VBUS (5 V typ.) sense input pin to enable the USB interface. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_5V016

17 I USB detect input

VBUS (5 V typ.) sense input pin to enable the USB interface. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

USB_3V316

2 I USB 3V3 input

3.3 V (typical) supply input pin to supply the USB interface. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D-

I/O

USB Data Line D-

USB interface for AT commands, data communication, FOAT, FW update by u-blox tool, diagnostics.

90  nominal differential impedance (Z0) 30  nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [6] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D+

I/O

USB Data Line D+

USB interface for AT commands, data communication, FOAT, FW update by u-blox tool, diagnostics.

RSVD

N/A

RESERVED pin

This pin can be connected to GND by 0  series jumper. Test-Point for diagnostic strongly recommended.

SPI

I2S_WA / SPI_MOSI15

34 O SPI MOSI

SPI data output, alternatively configurable as 2S word alignment

SPI and I2S are not supported by current product versions. See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

I2S_RXD / SPI_MISO15

37 I SPI MISO

SPI data input, alternatively configurable as 2S receive data

SPI and I2S are not supported by current product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

I2S_CLK / SPI_CLK15

36 O SPI clock

SPI clock, alternatively configurable as I2S clock SPI and I2S are not supported by current product versions. See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

I2S_TXD / SPI_CS15

35 O SPI Chip Select

SPI Chip Select, alternatively settable as I2S transmit data SPI and I2S are not supported by current product versions. See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

SARA-R410M, SARA-R412M modules only

SARA-R422, SARA-R422S, SARA-R422M8S modules only

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Function

Pin Name

Pin No

I/O

Description

Remarks

SDIO

SDIO_D017

I/O

SDIO serial data [0]

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_D117

I/O

SDIO serial data [1]

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SDIO_D217

I/O

SDIO serial data [2]

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_D317

I/O

SDIO serial data [3]

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SDIO_CLK17

45 O SDIO serial clock

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

SDIO_CMD17

I/O

SDIO command

SDIO interface is not supported by current product versions. See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

DDC

SCL

27 O I2C bus clock line

1.8 V open drain, for communication with I2C devices. Internal pull-up to V_INT: external pull-up is not required. Not supported by SARA-R410M-01B product version. See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDA

I/O

I2C bus data line

See section 2.6.5 for external circuit design-in.

Audio

I2S_TXD18

35 O I2S transmit data

I2S digital audio interface transmit data output I2S interface not supported by current product versions. See section 1.9.5 for functional description. See section 2.7 for external circuit design-in.

I2S_RXD18

I2S receive data

I2S digital audio interface receive data input I2S interface not supported by current product versions. See section 1.9.5 for functional description. See section 2.7 for external circuit design-in.

I2S_CLK18

I/O

I2S clock

I2S digital audio interface clock I2S interface not supported by current product versions. See section 1.9.5 for functional description. See section 2.7 for external circuit design-in.

I2S_WA18

I/O

I2S word alignment

I2S digital audio interface word alignment I2S interface not supported by current product versions. See section 1.9.5 for functional description. See section 2.7 for external circuit design-in.

SARA-R410M, SARA-R412M modules only

SARA-R422S, SARA-R422M8S modules only

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Function

Pin Name

Pin No

I/O

Description

Remarks

GPIO

GPIO1

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GPIO2

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GPIO3

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GPIO4

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GPIO5

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GPIO6

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in.

GNSS PIOs

TXD_GNSS19

47 O GNSS data output

GNSS UART data output from internal u-blox M8 chipset. Test-Point for diagnostic access is recommended. See section 1.12 for functional description.

EXTINT19

GNSS external interrupt

GNSS external interrupt connected to u-blox M8 chipset. See section 1.12 for functional description.

TIMEPULSE19

45 O GNSS Time Pulse

GNSS time pulse output driven by u-blox M8 chipset. See section 1.12 for functional description.

ANT_ON19

Antenna / LNA enable

External GNSS active antenna and/or LNA on/off signal driven by u-blox M8 chipset, connected to internal LNA.

See section 1.12 for functional description.

Reserved

RSVD20

N/A

Reserved pin

Internally not connected. See sections 1.13 and 2.10

RSVD21

N/A

Reserved pin

Internally not connected. See sections 1.13 and 2.10

RSVD22

18, 48,49

N/A

Reserved pin

Internally not connected. See sections 1.13 and 2.10

RSVD23

34,35, 36,37

N/A

Reserved pin

Leave unconnected. See sections 1.13 and 2.10

RSVD24

44,45, 46,47

N/A

Reserved pin

Internally not connected. See sections 1.13 and 2.10

Table 3: SARA-R4 series modules pin definition, grouped by function

SARA-R422M8S modules only

SARA-R410M, SARA-R412M modules only

SARA-R410M, SARA-R412M, SARA-R422, SARA-R422S modules only

SARA-R422, SARA-R422S, SARA-R422M8S modules only

SARA-R422 modules only

SARA-R422, SARA-R422S modules only

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1.4 Operating modes

SARA-R4 series modules have several operating modes. The operating modes are defined in Table 4 and described in detail in Table 5, providing general guidelines for operation.

General status

Operating mode

Definition

Power-down

Not-powered mode

VCC supply not present or below operating range: module is switched off.

Power-off mode

VCC supply within operating range and module is switched off.

Normal Operation

Deep-sleep mode

Only the RTC runs, with 32 kHz reference internally generated.

Idle mode

Module processor runs with 32 kHz reference generated by the internal oscillator.

Active mode

Module processor runs with 19.2 MHz reference generated by the internal oscillator.

Connected mode

RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.

Table 4: SARA-R4 series modules operating modes definition

Mode

Description

Transition between operating modes

Not-Powered

Module is switched off. Application interfaces are not accessible.

When VCC supply is removed, the modules enter not-powered mode.

When in not-powered mode, the module can enter power-off mode applying VCC supply (see 1.6.1).

Power-Off

Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2).

Application interfaces are not accessible.

The modules enter power-off mode from active mode when the host processor implements a clean switch-off procedure, by sending the +CPWROFF AT command or by using the PWR_ON / PWR_CTRL pin (see 1.6.2).

When in power-off mode, the modules can be switched on by the host processor using the PWR_ON / PWR_CTRL input pin (see

1.6.1).

When in power-off mode, the modules enter not-powered mode by removing VCC supply.

Deep-Sleep

Module is in RTC-only mode: only the internal 32 kHz Real Time Clock is active.

The RF section and the application interfaces are temporarily disabled and switched off: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption to the minimum possible (see section 1.5.1.4).

The modules automatically switch from the active mode to the ultra low power deep sleep mode whenever possible, upon expiration of the T3324 active timer set by the network (entering the Power Saving Mode defined in 3GPP Rel.13, depending on the configuration set by +CPSMS AT command), upon expiration of the 6 s AT inactivity timer (depending on the configuration set by the +UPSV AT command), in-between eDRX cycles when not listening to paging (depending on the configuration set by the +UPSMVER AT command), if no concurrent GNSS activities are executed (considering the SARA-R422M8S and SARA-R422S modules).

When the module is in the ultra low power deep sleep mode, it automatically switches on to the active mode upon expiration of the T3412 periodic TAU timer set by the network according to the Power Saving Mode defined in 3GPP Rel.13, it automatically switches on in-between eDRX cycles when listening to paging according to the timing set by the network, or it can be switched on to the active mode by the host processor using the PWR_ON / PWR_CTRL input pin (see 1.6.1).

For further details, see u-blox application development guide [4] and the u-blox AT commands manual [2].

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Mode

Description

Transition between operating modes

Idle

Module is switched on with application interfaces temporarily disabled: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption (see section 1.5.1.5).

The modules automatically switch from the active mode to low power idle mode whenever possible, depending on concurrent activities executed by the module, upon expiration of the 6 seconds AT inactivity timer (with AT+UPSV=4 setting), or upon DTR set to OFF (with AT+UPSV=3 setting), if low power configuration is enabled (see the SARA-R4 series AT commands manual [2], +UPSV AT command).

When in low power idle mode, the module switches to the active mode upon data reception over UART serial interface (with AT+UPSV=4 setting, and in this case the first character received in low power idle mode wakes up the system, it is not recognized as valid communication character, and the recognition of the subsequent characters is guaranteed only after the complete system wake-up), or upon DTR set to ON (with AT+UPSV=3 setting).

Active

Module is switched on with application interfaces enabled or not suspended: the module is ready to communicate with an external device by means of the application interfaces, with related necessary current consumption (see section 1.5.1.6).

The modules enter active mode from power-off mode when the host processor implements a clean switch-on procedure by using the PWR_ON / PWR_CTRL pin (see 1.6.1).

The modules enter active mode from the ultra low power deep sleep mode upon expiration of the T3412 periodic TAU timer set by the network, to receive the paging in-between eDRX cycles according to the timing set by the network, or if the host processor wakes up the module using the PWR_ON / PWR_CTRL input pin (see 1.6.1).

The modules enter power-off mode from active mode when the host processor implements a switch-off procedure (see 1.6.2).

The modules automatically switch from active to ultra low power deep sleep mode whenever possible, upon expiration of the T3324 active timer set by the network (depending on +CPSMS AT command setting), upon expiration of the 6 s AT inactivity timer (depending on the +UPSV AT command setting), inbetween eDRX cycles when not listening to paging (depending on the +UPSMVER AT command setting), if no concurrent GNSS activities are executed (for SARA-R422M8S and SARA-R422S).

The module switches from active to connected mode when a RF Tx/Rx data connection is initiated or when RF Tx/Rx activity is required due to a connection previously initiated.

The module switches from connected to active mode when a RF Tx/Rx data connection is terminated or suspended.

Connected

RF Tx/Rx data connection is in progress, with related necessary current consumption (see sections 1.5.1.2 and 1.5.1.3).

The module is prepared to accept data signals from an external device.

When a data connection is initiated, the module enters connected mode from active mode.

Connected mode is suspended if Tx/Rx data is not in progress. In such cases the module automatically switches from connected to active mode and then, depending on the +UPSV, +CPSMS and +UPSMVER AT commands settings, the module automatically switches to the low power idle mode and/or to the ultra low power deep sleep mode whenever possible. Vice-versa, the module wakes up from low power idle mode and/or from ultra low power deep sleep mode to active mode and then connected mode if RF Tx/Rx activity is necessary.

When a data connection is terminated, the module returns to the active mode.

Table 5: SARA-R4 series modules operating modes description

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The initial operating mode of SARA-R4 series modules is the one with VCC supply not present or below the operating range: the modules are switched off in not-powered mode.

Once a valid VCC supply is applied to the SARA-R4 series modules, they remain switched off in the power-off mode. Then the proper toggling of the PWR_ON / PWR_CTRL input line is necessary to trigger the switch-on routine of the modules that subsequently enter the active mode.

SARA-R4 series modules are fully ready to operate when in active mode: the available communication interfaces are completely functional and the module can accept and respond to AT commands, entering connected mode upon cellular RF signal reception / transmission.

The internal GNSS functionality can be concurrently enabled on the SARA-R422M8S modules by the dedicated +UGPS AT command, as well as the external GNSS functionality can be concurrently enabled using SARA-R410M, SARA-R412M or SARA-R422S modules by the same AT command.

SARA-R4 series modules switch from active mode to the low power idle mode whenever possible, if the low power configuration is enabled by the dedicated +UPSV AT command. The low power idle mode can last for different time periods according to the specific +UPSV AT command setting, according to the DRX / eDRX setting, and according to the concurrent activities executed by the module, as in particular according to the concurrent GNSS activities.

SARA-R4 series modules enter the User Equipment Power Saving Mode defined in 3GPP Rel.13 whenever possible, if the use of the PSM is enabled by the +CPSMS / +UCPSMS AT commands, and according to the +UMNOPROF AT command settings. The PSM can last for different time periods according to the T3412 periodic TAU timer set by the network. Then, the modules enter the ultra-low power deep-sleep mode whenever possible, if no other concurrent activities are executed by the module, in particular if no concurrent GNSS activities are executed by the SARA-R422M8S modules.

SARA-R422, SARA-R422S and SARA-R422M8S modules may automatically enter the ultra low power deep sleep mode in-between eDRX cycles, whenever possible, if the functionality is enabled using the +UPSMVER AT command.

Once the modules enter the ultra-low power deep-sleep mode, the available communication interfaces are not functional: a wake-up event, consisting in proper toggling of the PWR_ON / PWR_CTRL input input line or the expiration of the timer set by the network, is necessary to trigger the wake-up routine of the modules that subsequently enter back into the active mode.

SARA-R4 series modules can be gracefully switched off by the dedicated +CPWROFF AT command, or by proper toggling of the PWR_ON / PWR_CTRL input.

Figure 5 describes the transition between the different operating modes.

Remove VCC

Switch ON:

• PWR_ON

• PWR_CTRL

Not powered

Power off

Switch OFF:

• AT+CPWROFF

• PWR_ON

• PWR_CTRL

Apply VCC

If PSM mode is enabled (AT+CPSMS=1), if AT Inactivity Timer and Active Timer are expired, if no other concurrent activity is executed

• Up on expiration of the Periodic Update Timer

• Us ing PWR_ON pin

Incoming/outgoing data, or other dedicated network communication

No RF Tx/Rx in progress, Communication dropped

ActiveConnected Deep Sleep

If low power idle mode is enabled (AT+UPSV≠0),

if AT Inactivity Timer is expired,

if there is none concurrent activity

Idle

Data received over UART (if AT+UPSV=4),

DTR assert to ON (if AT+UPSV=3), Other concurrent activity

Figure 5: SARA-R4 series modules operating modes transitions

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1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input.

Voltage must be stable, because during operation, the current drawn by the SARA-R4 series modules through the VCC pins can vary by several orders of magnitude, depending on the operating mode and state (as described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.6).

It is important that the supply source is able to withstand both the maximum pulse current occurring during a transmit burst at maximum power level and the average current consumption occurring during Tx / Rx call at maximum RF power level (see the SARA-R4 series data sheet [1]).

SARA-R412M, SARA-R422, SARA-R422S, SARA-R422M8S modules, supporting 2G radio access technology, provide separate supply inputs over the three VCC pins:

• VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding

most of the total current drawn of the module when RF transmission is enabled during a call

• VCC pin #51 represents the supply input for the internal baseband power management unit,

demanding minor part of the total current drawn of the module when RF transmission is enabled during a call

The 3 VCC pins of SARA-R410M modules are internally connected each other to both the internal RF Power Amplifier and the internal baseband power management unit.

Figure 6 provides a simplified block diagram of SARA-R4 series modules’ internal VCC supply routing.

VCC

SARA-R410M

Power

Management

Unit

Memory

Baseband Processor

Transceiver

Power

Amplifier

VCC

SARA-R412M

SARA-R422 / SARA-R422S / SARA-R422M8S

Power

Management

Unit

Memory

Baseband Processor

Transceiver

Power

Amplifier

Figure 6: Block diagram of SARA-R4 series modules’ internal VCC supply routing

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1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions

to correctly design a VCC supply circuit compliant with the requirements listed in Table 6.

⚠ The supply circuit affects the RF compliance of the device integrating SARA-R4 series modules

with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the requirements summarized in the Table 6 are fulfilled.

Item

Requirement

Remark

VCC nominal voltage

Within VCC normal operating range: SARA-R410M:

3.2 V / 4.2 V SARA-R412M / -R422 / -R422S / -R422M8S:

3.2 V / 4.5 V

RF performance is guaranteed when VCC voltage is inside the normal operating range limits. RF performance may be affected when VCC voltage is outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits.

VCC voltage during normal operation

Within VCC extended operating range: SARA-R410M:

3.0 V / 4.2 V SARA-R412M/ -R422 / -R422S / -R422M8S:

3.0 V / 4.5 V

VCC voltage must be above the extended operating range minimum limit to switch-on the module.

The module may switch-off when the VCC voltage drops below the extended operating range minimum limit.

Operation above VCC extended operating range is not recommended and may affect device reliability.

VCC average current

Support with adequate margin the highest averaged VCC current consumption value in connected mode conditions specified in the SARA-R4 series data sheet [1]

The maximum average current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage. Section 1.5.1.2 describes current consumption profiles in connected mode.

VCC peak current

Support with adequate margin the highest peak VCC current consumption value in Tx connected mode conditions specified in the SARA-R4 series data sheet [1]

The maximum peak Tx current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage.

Section 1.5.1.2 describes current consumption profiles in connected mode.

VCC voltage drop during Tx slots

Lower than 400 mV

VCC voltage drop directly affects the RF compliance with applicable certification schemes.

Figure 9 describes VCC voltage drop during 2G Tx

slots.

VCC voltage ripple during Tx

Noise in the supply pins must be minimized

High supply voltage ripple values during RF transmissions in connected mode directly affect the RF compliance with the applicable certification schemes.

VCC under/overshoot at start/end of Tx slots

Absent or at least minimized

VCC under/over-shoot directly affects the RF compliance with applicable certification schemes.

Figure 9 describes VCC voltage under/over-shoot.

Table 6: Summary of VCC modules supply requirements

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1.5.1.2 VCC current consumption in LTE connected mode

During an LTE connection, the SARA-R4 series modules transmit and receive in half duplex mode.

The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz.

Figure 7 shows an example of SARA-R4 series modules’ current consumption profile versus time in

connected mode: transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-duplex connected mode.

Detailed current consumption values can be found in the SARA-R4 series data sheet [1].

Time [ms]

Current [mA]

300

200

100

500

400

Current consumption value

depends on TX power and

actual antenna load

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Frame

(10 ms)

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Frame

(10 ms)

Figure 7: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection

1.5.1.3 VCC current consumption in 2G connected mode

When a 2G call is established, the VCC consumption is determined by the current consumption profile typical of the 2G transmitting and receiving bursts.

The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption.

If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can reach a high peak / pulse (see the SARA-R4 series data sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are much lower than during transmission in the low bands, due to the 3GPP transmitter output power specifications.

During a 2G call, current consumption is not significantly high while receiving or in monitor bursts, and it is low in the bursts unused to transmit / receive.

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Figure 8 shows an example of the module current consumption profile versus time in 2G single-slot.

Time

[ms]

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200 mA

60-120 mA

1900 mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5

1.0

0.5

0.0

2.0

60-120 mA

10 -40 mA

Figure 8: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)

Figure 9 illustrates the VCC voltage profile versus time during a 2G single-slot call, according to the

related VCC current consumption profile described in Figure 8.

Time

undershoot

overshoot

ripple

drop

Voltage

3.8 V (typ)

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

GSM frame

4.615 ms

(1 frame = 8 slots)

Figure 9: Description of the VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)

When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption. But according to GPRS specifications, the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the case of a GSM call.

If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level, the consumption can reach a quite a high peak but lower than the one achievable in 2G singleslot mode. This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA.

If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower than in the 850 or 900 MHz band because of the 3GPP Tx power specifications.

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Figure 10 illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz

bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.

Time

[ms]

slot

unused

slot

MON

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

60-120mA

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5

1.0

0.5

0.0

60-120mA

10 -40mA

200mA

Peak current depends

on TX power and

actual antenna load

1600 mA

Figure 10: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)

In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one during GPRS connections: the current consumption profile in GPRS multi-slot class 12 connected mode illustrated in the Figure 10 is representative for the EDGE multi-slot class 12 connected mode as well.

1.5.1.4 VCC current consumption in ultra low power deep sleep mode

The use of the User Equipment Power Saving Mode defined in 3GPP Rel.13 is by default disabled, but it can be enabled using the +CPSMS AT command (see the SARA-R4 series AT commands manual [2] the application development guide [4]). When the use of the PSM is enabled, the module automatically enters the PSM and the ultra low power deep sleep mode whenever possible.

When in ultra low power deep sleep mode, the current consumption is reduced down to a steady value in the µA range: only the RTC runs with internal 32 kHz reference clock frequency.

Detailed current consumption values can be found in the SARA-R4 series data sheet [1].

☞ Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the

RC oscillator, as a consequence, a very low spike in current consumption will be observed.

DEEP SLEEP MODE

Time [h]

Current [mA]

100

Figure 11: Example of VCC current consumption profile in ultra low power deep sleep mode with the use of the PSM enabled enabled (AT+CPSMS≠0), module registered with the network: the module is in ultra low power deep sleep mode, with no concurrent activities executed, and it does not periodically wake up for paging block reception, but it wakes up upon the expiration of the periodic update timer set by the network or due to proper toggling of the PWR_ON / PWR_CTRL input line

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1.5.1.5 VCC current consumption in low power idle mode

The low power idle mode configuration is by default disabled, but it can be enabled using the +UPSV AT command (see the SARA-R4 series AT commands manual [2]).

When low power idle mode is enabled, the module automatically enters the low power mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active mode to enable the reception of the paging block. In between, the module switches to low power mode. This is known as discontinuous reception (DRX) or extended discontinuous reception (eDRX).

Figure 12 illustrates an example of the module current consumption profile when low power mode

configuration is enabled: the module is registered with the network, automatically enters the low power idle mode, and periodically wakes up to active mode to monitor the paging channel for the paging block reception in discontinuous reception (DRX) mode.

Detailed current consumption values can be found in the SARA-R4 series data sheet [1].

IDLE MODE ACTIVE MODE IDLE MODE

Active Mode

Enabled

Idle Mode

Enabled

Time [s]

Current [mA]

Time [ms]

Current [mA]

Enabled

100

Paging period

Figure 12: Example of VCC current consumption profile with low power mode enabled (AT+UPSV≠0), module registered with the network: the module is in low-power idle mode, with no concurrent activities executed, and it periodically wakes up to active mode for paging block reception

1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)

The active mode is the state where the module is switched on and ready to communicate with an external device by means of the application interfaces (as the USB or the UART serial interface). The module processor core is active, and the 19.2 MHz reference clock frequency is used.

If power saving mode and/or low power mode configurations are disabled, as it is by default (see the SARA-R4 series AT commands manual [2], +CPSMS, +UCPSMS, +UPSMVER, +UPSV AT commands for details), the module remains in active mode. Otherwise, if PSM mode and/or low power mode configurations are enabled, the module enters PSM mode and/or low power mode whenever possible.

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Figure 13 illustrates a typical example of the module current consumption profile when the module is

in active mode. In such case, the module is registered with the network and, while active mode is maintained, the receiver is periodically activated to monitor the paging channel for paging block reception.

Detailed current consumption values can be found in the SARA-R4 series data sheet [1].

ACTIVE MODE

Paging period

Time [s]

Current [mA]

Time [ms]

Current [mA]

Enabled

100

Figure 13: Example of VCC current consumption profile with low power mode disabled (AT+UPSV=0), module registered with the network: active mode is held, the receiver is periodically temporarily activated for paging block reception

1.5.2 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the SARA-R4 series modules is generated by the module internal power management circuitry when the module is switched on and it is not in the deep sleep power saving mode.

The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4 series data sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a reference voltage rail for external components.

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1.6 System function interfaces

1.6.1 Module power-on

When the SARA-R4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied), they can be switched on as follows:

• Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set

at the PWR_ON / PWR_CTRL input pin for a valid time.

When the SARA-R4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving Mode (PSM), with a valid VCC supply applied, they can be switched on as follows:

• Low pulse on the PWR_ON / PWR_CTRL pin for a valid time period

The PWR_ON / PWR_CTRL input pin is equipped with an internal active pull-up resistor. Detailed characteristics with voltages and timings are described in the SARA-R4 series data sheet [1].

Figure 14 shows the module switch-on sequence from the not-powered mode, with following phases:

• The external power supply is applied to the VCC module pins

• The PWR_ON / PWR_CTRL pin is held low for a valid time

• All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).

• The internal reset signal is held low: the baseband core and all digital pins are held in reset state.

When the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to the default operational configured state. The duration of this phase differs within generic digital interfaces and USB interface due to host / device enumeration timings.

• The module is fully ready to operate after all interfaces are configured.

VCC

PWR_ON / PW R_CTRL

RESET_N

V_INT

Internal Reset

GPIO

System State

BB Pads State Operational

OFF

Internal Reset → Operational

Tristate / Floating

Internal Reset

Start o f interface

configuration

Module interfaces

are configured

Start-up

event

Figure 14: SARA-R4 series switch-on sequence description

☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:

o the V_INT pin, to sense the start of the SARA-R4 series module switch-on sequence o the GPIO pin configured to provide the module operating status indication (see SARA-R4 series

commands manual [2], +UGPIOC AT command), to sense when the module is ready to operate

☞ Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage

driven by an external application should be applied to any generic digital interface of the module.

☞ Before the SARA-R4 series module is fully ready to operate, the host application processor should

not send any AT command over AT communication interfaces (USB, UART) of the module.

☞ The duration of the SARA-R4 series modules’ switch-on routine can largely vary depending on the

application / network settings and the concurrent module activities.

⚠ An abrupt removal of the VCC supply, or forcing an abrupt emergency reset / switch off by

asserting the RESET_N / PWR_CTRL input, once the boot of SARA-R4 series modules has been triggered may lead to an unrecoverable faulty state!

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1.6.2 Module power-off

SARA-R4 series modules can be gracefully switched off by:

• AT+CPWROFF command (see SARA-R4 series AT commands manual [2]).

• Low pulse on the PWR_ON / PWR_CTRL pin for a valid time period (for detailed characteristics see

the SARA-R4 series data sheet [1]).

These events listed above trigger the storage of the current parameter settings in the non-volatile memory of the module, and a clean network detach procedure.

An emergency faster and safe power-off procedure of SARA-R422, SARA-R422S, SARA-R422M8S modules, without proper network detach, can be triggered by:

• AT+CFUN=10 command (see SARA-R4 series AT commands manual [2])

• Toggling the GPIO input pin configured with the fast and safe power-off function (see section 1.11)

☞ The graceful switched off procedure triggered by the +CPWROFF AT command or by proper low

pulse at the PWR_ON / PWR_CTRL input pin must be preferred rather than the faster and safe power-off procedure triggered by the AT+CFUN=10 command or by toggling the configured GPIO pin, as the faster and safe power-off procedure is intended to be used in case of emergency only.

An abrupt under-voltage shutdown occurs on SARA-R4 series modules when the VCC module supply is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the module’s non-volatile memory or to perform the clean network detach.

☞ It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series

modules normal operations.

⚠ An abrupt removal of the VCC supply during SARA-R4 series modules normal operations may lead

to an unrecoverable faulty state!

An abrupt hardware shutdown occurs on SARA-R410M and SARA-R412M modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a clean network detach is not performed.

☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low

level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in SARA-R4 series AT commands manual [2].

⚠ Forcing a low level on the RESET_N input during SARA-R4 series modules normal operations may

lead to an unrecoverable faulty state!

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Figure 15 and Figure 16 describe the SARA-R4 series modules switch-off sequence started by means

of the AT+CPWROFF command and by means of the PWR_ON / PWR_CTRL input pin respectively, allowing storage of current parameter settings in the module’s non-volatile memory and a clean network detach, with the following phases:

• When the +CPWROFF AT command is sent, or when a low pulse with appropriate time duration

(see the SARA-R4 series data sheet [1]) is applied at the PWR_ON / PWR_CTRL input pin, the module starts the switch-off routine.

• Then, if the +CPWROFF AT command has been sent, the module replies OK on the AT interface:

the switch-off routine is in progress.

• At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage

regulators are turned off, including the generic digital interfaces supply (V_INT).

• Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g.

applying a low level to PWR_ON / PWR_CTRL input pin), and it enters not-powered mode if the VCC supply is removed.

VCC

PWR_ON / PWR_CTRL

RESET_N

V_INT

Internal Reset

System State

BB Pads State Operational

OFF

Tristate / Floating

Operational → Tristate

AT+CPWROFF

sent to the module

replied by the module

VCC can be

removed

Figure 15: SARA-R4 series modules switch-off sequence by means of AT+CPWROFF command

VCC

PWR_ON / PWR_CTRL

RESET_N

V_INT

Internal Reset

System State

BB Pads State

OFF

Tristate / Floating

Operational -> Tristate

Operational

The module starts the

switch-off routine

VCC can be

removed

Figure 16: SARA-R4 series modules switch-off sequence by means of PWR_ON / PWR_CTRL pin

☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor

the V_INT pin to sense the end of the switch-off sequence.

⚠ VCC supply can be removed only after V_INT goes low: an abrupt removal of the VCC supply during

SARA-R4 series modules normal operations may lead to an unrecoverable faulty state!

☞ The duration of each phase in the SARA-R4 series modules’ switch-off routines can largely vary

depending on the application / network settings and the concurrent module activities.

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Document information

Contents

1 System description

1.1 Overview

1.2 Architecture

1.3 Pin-out

1.4 Operating modes

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

1.5.1.1 VCC supply requirements

1.5.1.2 VCC current consumption in LTE connected mode

1.5.1.3 VCC current consumption in 2G connected mode

1.5.1.4 VCC current consumption in ultra low power deep sleep mode

1.5.1.5 VCC current consumption in low power idle mode

1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)

1.5.2 Generic digital interfaces supply output (V_INT)

1.6 System function interfaces

1.6.1 Module power-on

1.6.2 Module power-off