Ublox SARA-R4 Series, SARA-N4 Series, SARA-R404M, SARA-R410M, SARA-N410 System Integration Manual
...
Abstract
This document describes the features and the integration of the size-optimized SARA-R4/N4 series cellular
modules. These modules are a complete, cost efficient, performance optimized, multi-mode and multi
band LTE Cat M1 / NB1 and EGPRS solution in the compact SARA form factor.
www.u-blox.com
UBX-16029218 - R11
SARA-R4/N4
SARA-R4/N4 series
System Integration Manual
System Integration Manual
SARA-R4/N4 series - System Integration Manual
Title
SARA-R4/N4 series
Subtitle
System Integration Manual
Document type
System Integration Manual
Document number
UBX-16029218
Revision and date
R11
20-Feb-2019
Disclosure Restriction
Product status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Production Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Document contains the final product specification.
Product name
Type number
Modem version
Application version
PCN reference
Product status
SARA-R404M
SARA-R404M-00B-00
K0.0.00.00.07.06
UBX-17047084
End of Life
SARA-R404M-00B-01
K0.0.00.00.07.08
UBX-18053670
Initial Production
SARA-R410M
SARA-R410M-01B-00
L0.0.00.00.02.03
UBX-17051617
Initial Production
SARA-R410M-02B-00
L0.0.00.00.05.06
A02.00
UBX-18010263
Initial Production
SARA-R410M-52B-00
L0.0.00.00.06.05
A02.06
UBX-18045915
Initial Production
SARA-R412M
SARA-R412M-02B-00
M0.09.00
A02.11
UBX-19004091
Initial Production
SARA-N410
SARA-N410-02B-00
L0.0.00.00.07.07
A02.09
UBX-18057459
Initial Production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document.
Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the
express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents,
visit www.u-blox.com.
Copyright © u-blox AG.
Document Information
This document applies to the following products:
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Contents
Document Information ............................................................................................................................ 2
Contents...................................................................................................................................................... 3
1 System description ............................................................................................................................ 7
1.1 Overview ........................................................................................................................................................................................... 7
1.2 Architecture ................................................................................................................................................................................... 11
1.3 Pin-out ............................................................................................................................................................................................. 12
1.4 Operating modes ....................................................................................................................................................................... 17
1.5 Supply interfaces ........................................................................................................................................................................ 21
1.5.1 Module supply input (VCC) ......................................................................................................................................... 21
1.5.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 28
1.6 System function interfaces ..................................................................................................................................................... 30
1.6.1 Module power-on ............................................................................................................................................................ 30
1.6.2 Module power-off ............................................................................................................................................................ 31
1.6.3 Module reset ...................................................................................................................................................................... 33
1.7 Antenna interface ....................................................................................................................................................................... 35
1.7.1 Antenna RF interface (ANT) ......................................................................................................................................... 35
1.7.2 Antenna detection interface (ANT_DET) ................................................................................................................ 36
1.8 SIM interface................................................................................................................................................................................. 36
1.8.1 SIM interface ...................................................................................................................................................................... 36
1.8.2 SIM detection interface ................................................................................................................................................. 37
1.9 Data communication interfaces ........................................................................................................................................... 38
1.9.1 UART interface ................................................................................................................................................................... 38
1.9.2 USB interface ...................................................................................................................................................................... 40
1.9.3 SPI interface ........................................................................................................................................................................ 42
1.9.4 SDIO interface .................................................................................................................................................................... 42
1.9.5 DDC (I2C) interface........................................................................................................................................................... 42
1.10 Audio ................................................................................................................................................................................................ 42
1.11 General Purpose Input/Output ............................................................................................................................................ 44
1.12 Reserved pins (RSVD) ............................................................................................................................................................... 44
1.13 System features ........................................................................................................................................................................... 45
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1.13.1 Network indication .......................................................................................................................................................... 45
1.13.2 Antenna supervisor.......................................................................................................................................................... 45
1.13.3 Dual stack IPv4/IPv6........................................................................................................................................................ 45
1.13.4 TCP/IP and UDP/IP .......................................................................................................................................................... 45
1.13.5 FTP ........................................................................................................................................................................................... 45
1.13.6 HTTP ....................................................................................................................................................................................... 46
1.13.7 Firmware update Over AT (FOAT) ............................................................................................................................ 46
1.13.8 Firmware update Over The Air (uFOTA) ................................................................................................................ 46
1.13.9 Power saving ...................................................................................................................................................................... 47
2 Design-in ........................................................................................................................................... 51
2.1 Overview ......................................................................................................................................................................................... 51
2.2 Supply interfaces ........................................................................................................................................................................ 53
2.2.1 Module supply (VCC) ..................................................................................................................................................... 53
2.2.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 75
2.3 System functions interfaces ................................................................................................................................................... 76
2.3.1 Module power-on (PWR_ON)..................................................................................................................................... 76
2.3.2 Module reset (RESET_N) ................................................................................................................................................ 78
2.4 Antenna interface ....................................................................................................................................................................... 79
2.4.1 Antenna RF interface (ANT) ......................................................................................................................................... 79
2.4.2 Antenna detection interface (ANT_DET) ................................................................................................................ 88
2.5 SIM interface................................................................................................................................................................................. 92
2.5.1 Guidelines for SIM circuit design ............................................................................................................................. 92
2.5.2 Guidelines for SIM layout design ............................................................................................................................. 97
2.6 Data communication interfaces ........................................................................................................................................... 98
2.6.1 UART interface ................................................................................................................................................................... 98
2.6.2 USB interface ................................................................................................................................................................... 105
2.6.3 SPI interface ..................................................................................................................................................................... 107
2.6.4 SDIO interface ................................................................................................................................................................. 107
2.6.5 DDC (I2C) interface........................................................................................................................................................ 107
2.7 Audio ............................................................................................................................................................................................. 111
2.7.1 Guidelines for Audio circuit design ...................................................................................................................... 111
2.8 General Purpose Input/Output ......................................................................................................................................... 111
2.8.1 Guidelines for GPIO circuit design ........................................................................................................................ 111
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2.8.2 Guidelines for general purpose input/output layout design ................................................................... 112
2.9 Reserved pins (RSVD) ............................................................................................................................................................ 113
2.10 Module placement .................................................................................................................................................................. 113
2.11 Module footprint and paste mask .................................................................................................................................. 114
2.12 Thermal guidelines ................................................................................................................................................................. 115
2.13 Schematic for SARA-R4/N4 series module integration ......................................................................................... 116
2.13.1 Schematic for SARA-R4/N4 series modules ..................................................................................................... 116
2.14 Design-in checklist .................................................................................................................................................................. 118
2.14.1 Schematic checklist ...................................................................................................................................................... 118
2.14.2 Layout checklist .............................................................................................................................................................. 118
2.14.3 Antenna checklist .......................................................................................................................................................... 119
3 Handling and soldering ................................................................................................................ 120
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................................. 120
3.2 Handling ...................................................................................................................................................................................... 120
3.3 Soldering ..................................................................................................................................................................................... 122
3.3.1 Soldering paste .............................................................................................................................................................. 122
3.3.2 Reflow soldering ............................................................................................................................................................ 122
3.3.3 Optical inspection ......................................................................................................................................................... 124
3.3.4 Cleaning ............................................................................................................................................................................. 124
3.3.5 Repeated reflow soldering ........................................................................................................................................ 124
3.3.6 Wave soldering .............................................................................................................................................................. 124
3.3.7 Hand soldering ............................................................................................................................................................... 125
3.3.8 Rework ................................................................................................................................................................................ 125
3.3.9 Conformal coating ........................................................................................................................................................ 125
3.3.10 Casting................................................................................................................................................................................ 125
3.3.11 Grounding metal covers ............................................................................................................................................ 125
3.3.12 Use of ultrasonic processes ...................................................................................................................................... 126
4 Approvals......................................................................................................................................... 127
4.1 Product certification approval overview ....................................................................................................................... 127
4.2 US Federal Communications Commission notice .................................................................................................... 130
4.2.1 Safety warnings review the structure .................................................................................................................. 130
4.2.2 Declaration of Conformity ........................................................................................................................................ 130
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4.2.3 Modifications ................................................................................................................................................................... 131
4.3 Innovation, Science, Economic Development Canada notice ............................................................................ 132
4.3.1 Declaration of Conformity ........................................................................................................................................ 132
4.3.2 Modifications ................................................................................................................................................................... 133
4.4 European Conformance CE mark ..................................................................................................................................... 136
4.5 Taiwanese National Communication Commission .................................................................................................. 137
5 Product testing ............................................................................................................................... 138
5.1 u-blox in-series production test ....................................................................................................................................... 138
5.2 Test parameters for OEM manufacturers ..................................................................................................................... 139
5.2.1 “Go/No go” tests for integrated devices ........................................................................................................... 139
5.2.2 RF functional tests ........................................................................................................................................................ 140
Appendix ................................................................................................................................................ 142
A Migration between SARA modules ............................................................................................ 142
A.1 Overview ...................................................................................................................................................................................... 142
A.2 Pin-out comparison ................................................................................................................................................................ 144
B Glossary ........................................................................................................................................... 151
Related documents ............................................................................................................................... 154
Revision history ..................................................................................................................................... 155
Contact .................................................................................................................................................... 156
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Model
Region
Bands
Positioning
Interfaces
Audio
Features
Grade
-band
®
2
C)
(FOTA)
SARA-R404M
USA
13
M1
13
●
●
●
●
● ● ● ● ● ●
SARA-R410M-01B
North America
13
M1
2,4
5,12
●
●
●
●
● ● ● ● ● ●
SARA-R410M-02B
Multi Region
13
M1
NB1
*
● ● ○ ● ● ○ ○ ● ● ○ ● ● ● ● ● ●
● ●
SARA-R410M-52B
North America
13
M1
2,4,5
12,13
● ● ○ ● ● ○ ○ ● ●
● ● ● ● ● ● ● ●
1 System description
1.1 Overview
The SARA-R4/N4 series comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode modules in the miniature
SARA LGA form-factor (26.0 x 16.0 mm, 96-pin), that allow easy integration in compact designs and a
seamless drop-in migration from u-blox cellular module families.
SARA-R4/N4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module
families and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families.
This facilitates migration from u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules,
maximizes customer investments, simplifies logistics, and enables very short time-to-market. See Table 1
for a summary of the main features and interfaces.
The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices
that require long battery lifetimes, such as connected health, smart metering, smart cities and wearables.
The modules support handover capability and delivers the technology necessary for use in applications such
as vehicle, asset and people tracking where mobility is a pre-requisite. Other applications where the modules
are well-suited include and are not limited to: smart home, security systems, industrial monitoring and
control.
The modules support data communication over an extended operating temperature range of –40 to +85
°C, with extremely low power consumption, and with coverage enhancement for deeper range into buildings
and basements (and underground with NB1).
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SARA-R412M-02B
Multi Region
13
M1
NB1
*
● ● ● ○ ● ● ○ ○ ●
●
● ● ● ● ● ● ● ●
SARA-N410-02B
Multi Region
13
NB1 *
● ● ○ ● ● ○ ○ ● ●
● ● ● ● ● ● ● ●
* = LTE Cat M1/NB1 Bands may include 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only)
● = supported by all FW versions
○ = supported by future FW versions
Item
SARA-R404M
SARA-R410M
SARA-R412M
SARA-N410
Protocol stack
3GPP Release 13
3GPP Release 13
3GPP Release 13
3GPP Release 13
RAT
LTE Cat M1 Half-Duplex
LTE Cat M1 Half-Duplex
LTE Cat NB1 Half-Duplex 1
LTE Cat M1 Half-Duplex
LTE Cat NB1 Half-Duplex
2G GPRS / EGPRS
LTE Cat NB1 Half-Duplex
1
Table 1: SARA-R4/N4 series main features summary
SARA-R4/N4 series modules include the following variants / product versions:
SARA-R404M LTE Cat M1 module,
mainly designed for operation in LTE band 13
SARA-R410M-01B LTE Cat M1 module,
mainly designed for operation in LTE bands 2, 4, 5, 12
SARA-R410M-02B LTE Cat M1 / NB1 module,
mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28
SARA-R410M-52B LTE Cat M1 module,
mainly designed for operation in LTE bands 2, 4, 5, 12, 13
SARA-R412M-02B LTE Cat M1 / NB1 and 2G module,
mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad-band
SARA-N410-02B LTE Cat NB1 module,
mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 28
Table 2 summarizes cellular radio access technologies characteristics and features of the modules.
Not supported by the “01” product version.
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Item
SARA-R404M
SARA-R410M
SARA-R412M
SARA-N410
LTE FDD bands
Band 13 (750 MHz)
Band 12 (700 MHz)
Band 17 (700 MHz)
1, 2, 3
Band 28 (700 MHz) 1
Band 13 (750 MHz) 1
Band 20 (800 MHz) 1
Band 26 (850 MHz)
1, 2
Band 18 (850 MHz)
1, 2
Band 5 (850 MHz)
Band 19 (850 MHz)
1, 2
Band 8 (900 MHz) 1
Band 4 (1700 MHz)
Band 3 (1800 MHz) 1
Band 2 (1900 MHz)
Band 25 (1900 MHz)
1, 2, 3
Band 1 (2100 MHz) 1
Band 12 (700 MHz)
Band 13 (750 MHz)
Band 20 (800 MHz)
Band 5 (850 MHz)
Band 8 (900 MHz)
Band 4 (1700 MHz)
Band 3 (1800 MHz)
Band 2 (1900 MHz)
Band 12 (700 MHz)
Band 28 (700 MHz)
Band 13 (750 MHz)
Band 20 (800 MHz)
Band 5 (850 MHz)
Band 8 (900 MHz)
Band 4 (1700 MHz)
Band 3 (1800 MHz)
Band 2 (1900 MHz)
LTE TDD bands
Band 39 (1900 MHz)
3, 4
2G bands
GSM 850 MHz
E-GSM 900 MHz
DCS 1800 MHz
PCS 1900 MHz
Power class
LTE Cat M1:
Class 3 (23 dBm)
LTE Cat M1 / NB15:
Class 3 (23 dBm)
LTE category M1 / NB1:
Class 3 (23 dBm)
2G GMSK:
Class 4 (33 dBm) for
GSM/E-GSM bands
Class 1 (30 dBm) for
DCS/PCS bands
2G 8-PSK:
Class E2 (27 dBm) for
GSM/E-GSM bands
Class E2 (26 dBm) for
DCS/PCS bands
LTE category NB1:
Class 3 (23 dBm)
2
3
4
5
Not supported by the “52” product version.
Not supported in signaling mode by the “02” product version
Not supported in LTE category NB1. Not supported by the “01” and “52” product versions.
Not supported by the “01” product version.
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Item
SARA-R404M
SARA-R410M
SARA-R412M
SARA-N410
Data rate
LTE category M1:
up to 375 kb/s UL
up to 300 kb/s DL
LTE category M1:
up to 375 kb/s UL
up to 300 kb/s DL
LTE category NB15:
up to 62.5 kb/s UL
up to 27.2 kb/s DL
LTE category M1:
up to 375 kb/s UL
up to 300 kb/s DL
LTE category NB1:
up to 62.5 kb/s UL
up to 27.2 kb/s DL
GPRS multi-slot class 336:
Up to 85.6 kb/s UL
Up to 107 kb/s DL
EGPRS multi-slot class 336:
Up to 236.8 kb/s UL
Up to 296.0 kb/s DL
LTE category NB1:
up to 62.5 kb/s UL
up to 27.2 kb/s DL
6
Table 2: SARA-R4/N4 series modules LTE Cat M1, LTE Cat NB1, EGPRS and GPRS characteristics summary
GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total.
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Memory
V_INT
RF
transceiver
Cellular
BaseBand
Processor
ANT
VCC (Supply)
USB
DDC (I2C)
SIM card det ection
SIM
UART
Power-On
Reset
GPIOs
Antenna detect ion
Switch
PA
19.2 MHz
Power
Management
Filter
SDIO
SPI / Digit al Audio
1.2 Architecture
Figure 1 summarizes the internal architecture of SARA-R4/N4 series modules.
☞ SARA-R404M-00B and SARA-R410M-01B modules, i.e. the “00” and “01” product versions of the
☞ SARA-R410M-02B, SARA-R410M-52B, SARA-R412M-02B and SARA-N410-02B modules, i.e. the “02” and
Figure 1: SARA-R4/N4 series modules simplified block diagram
SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected
and should not be driven by external devices:
o DDC (I
2
C) interface
o SDIO interface
o SPI interface
o Digital audio interface
“52” product versions of the SARA-R4/N4 series modules, do not support the following interfaces, which
should be left unconnected and should not be driven by external devices:
o SDIO interface
o SPI interface
o Digital audio interface
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Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply
input
VCC supply circuit affects the RF performance and compliance
of the device integrating the module with applicable required
certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14,
20-22, 30,
32, 43, 50,
54, 55, 57-
61, 63-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1for functional description.
See section 2.2.1 for external circuit design-in.
V_INT
4 O Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator when
the module is switched on, outside the low power PSM deep
sleep mode.
Test-Point for diagnostic access is recommended.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
System
PWR_ON
15 I Power-on input
Internal 200 k pull-up resistor.
Test-Point for diagnostic access is recommended.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
18 I External reset input
Internal 37 k pull-up resistor.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Antenna
ANT
56
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT_DET
62 I Antenna detection
ADC for antenna presence detection function
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
SIM
VSIM
41 O SIM supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
1.3 Pin-out
Table 3 lists the pin-out of the SARA-R4/N4 series modules, with pins grouped by function.
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Function
Pin Name
Pin No
I/O
Description
Remarks
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38 O SIM clock
4.8 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40 O SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UART
RXD
13 O UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12 I UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT.
Internal pull-down to GND on “00” and R410M-02B versions
Internal pull-up to V_INT on other product versions
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11 O UART clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
Not supported by ‘00’, ‘01’ and R410M-02B versions.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10 I UART ready to send
input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
Not supported by ‘00’, ‘01’ and R410M-02B versions.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR 6 O
UART data set
ready output
1.8 V, Circuit 107 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI 7 O
UART ring indicator
output
1.8 V, Circuit 125 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR 9 I
UART data terminal
ready input
1.8 V, Circuit 108/2 in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD 8 O
UART data carrier
detect output
1.8 V, Circuit 109 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
USB
VUSB_DET
17 I USB detect input
VBUS (5 V typical) USB supply generated by the host must be
connected to this input pin to enable the USB interface.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D-
28
I/O
USB Data Line D-
USB interface for AT commands, data communication, FOAT,
FW update by u-blox tool, diagnostics.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [4] are part of the USB
pin driver and need not be provided externally.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D+
29
I/O
USB Data Line D+
USB interface for AT commands, data communication, FOAT,
FW update by u-blox tool, diagnostics.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [4] are part of the USB
pin driver and need not be provided externally.
Test-Point for diagnostic / FW update strongly recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
SPI
I2S_WA /
SPI_MOSI
34 O SPI MOSI
SPI Master Output Slave Input, alternatively configurable as I2S
word alignment
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_RXD /
SPI_MISO
37 I SPI MISO
SPI Master Input Slave Output, alternatively configurable as I2S
receive data
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_CLK /
SPI_CLK
36 O SPI clock
SPI clock, alternatively configurable as I2S clock
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_TXD /
SPI_CS
35 O SPI Chip Select
SPI Chip Select, alternatively settable as I2S transmit data
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
SDIO
SDIO_D0
47
I/O
SDIO serial data [0]
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D1
49
I/O
SDIO serial data [1]
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D2
44
I/O
SDIO serial data [2]
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D3
48
I/O
SDIO serial data [3]
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CLK
45 O SDIO serial clock
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CMD
46
I/O
SDIO command
Not supported by “00”, “01” and “x2” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
DDC
SCL
27 O I2C bus clock line
1.8 V open drain, for communication with I2C-slave devices.
Internal pull-up to V_INT: external pull-up is not required.
Not supported by “00” and “01” product versions.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDA
26
I/O
I2C bus data line
1.8 V open drain, for communication with I2C-slave devices.
Internal pull-up to V_INT: external pull-up is not required.
Not supported by “00” and “01” product versions.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
Audio
I2S_TXD /
SPI_CS
35 O I2S transmit data
I2S transmit data, alternatively configurable as SPI Chip Select
Not supported by “00”, “01” and “x2” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S_RXD /
SPI_MISO
37
I
I2S receive data
I2S receive data, alternatively configurable as SPI Master Input
Slave Output
Not supported by “00”, “01” and “x2” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S_CLK /
SPI_CLK
36
I/O
I2S clock
I2S clock, alternatively configurable as SPI clock
Not supported by “00”, “01” and “x2” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
I2S_WA /
SPI_MOSI
34
I/O
I2S word alignment
I2S word alignment, alternatively configurable as
SPI Master Output Slave Input
Not supported by “00”, “01” and “x2” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
GPIO
GPIO1
16
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO6
19
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
33
N/A
Reserved pin
This pin can be connected to GND.
See sections 1.12 and 2.9
RSVD
2, 31
N/A
Reserved pin
Leave unconnected.
See sections 1.12 and 2.9
Table 3: SARA-R4/N4 series modules pin definition, grouped by function
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General Status
Operating Mode
Definition
Power-down
Not-Powered Mode
VCC supply not present or below operating range: module is switched off.
Power-Off Mode
VCC supply within operating range and module is switched off.
Normal Operation
Deep-Sleep Mode
RTC runs with 32 kHz reference internally generated.
Idle Mode
Module processor runs with 32 kHz reference generated by the internal oscillator.
Active Mode
Module processor runs with 19.2 MHz reference generated by the internal oscillator.
Connected Mode
RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.
Mode
Description
Transition between operating modes
Not-Powered
Module is switched off.
Application interfaces are not accessible.
When VCC supply is removed, the modules enter not-powered
mode.
When in not-powered mode, the module can enter power-off mode
applying VCC supply (see 1.6.1).
Power-Off
Module is switched off: normal shutdown by
an appropriate power-off event (see 1.6.2).
Application interfaces are not accessible.
The modules enter power-off mode from active mode when the
host processor implements a clean switch-off procedure, by sending
the AT+CPWROFF command or by using the PWR_ON pin (see
1.6.2).
When in power-off mode, the modules can be switched on by the
host processor using the PWR_ON input pin (see 1.6.1).
When in power-off mode, the modules enter not-powered mode by
removing VCC supply.
1.4 Operating modes
SARA-R4/N4 series modules have several operating modes. The operating modes are defined in Table 4
and described in detail in Table 5, providing general guidelines for operation.
Table 4: SARA-R4/N4 series modules operating modes definition
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Mode
Description
Transition between operating modes
Deep-Sleep
Only the internal 32 kHz reference is active.
The RF section and the application interfaces
are temporarily disabled and switched off: the
module is temporarily not ready to
communicate with an external device by
means of the application interfaces as
configured to reduce the current consumption.
The module enters the low power deep sleep
mode (entering the Power Saving Mode
defined in 3GPP Rel.13) whenever possible, if
power saving configuration is enabled by
AT+CPSMS command (see the SARA-R4/N4
series AT Commands Manual [2]), reducing
current consumption (see 1.13.9).
Power saving configuration is not enabled by
default; it can be enabled by AT+CPSMS (see
the SARA-R4/N4 series AT Commands Manual
[2]).
The modules automatically switch from the active mode to low
power deep sleep mode whenever possible, upon expiration of the
6 seconds AT inactivity timer, and upon expiration of “Active Timer”,
entering in the Power Saving Mode defined in 3GPP Rel.13, if power
saving configuration is enabled (see 1.13.9 and the SARA-R4/N4
series AT Commands Manual [2], AT+CPSMS command).
When in low power deep sleep mode, the module switches on to
the active mode upon expiration of “Periodic Update Timer”
according to the Power Saving Mode defined in 3GPP Rel.13 (see
1.13.9 and the SARA-R4/N4 series AT Commands Manual [2],
AT+CPSMS command), or it can be switched on to the active mode
by the host processor using the PWR_ON input pin (see section
1.6.1).
Idle
Module is switched on with application
interfaces temporarily disabled: the module is
temporarily not ready to communicate with an
external device by means of the application
interfaces as configured to reduce the current
consumption.
The module enters the low power idle mode
whenever possible, if low power configuration
is enabled by AT+UPSV command (see the
SARA-R4/N4 series AT Commands Manual [2]),
reducing current consumption.
Low power configuration is not enabled by
default; it can be enabled by AT+UPSV (see
the SARA-R4/N4 series AT Commands Manual
[2]).
The modules automatically switch from the active mode to low
power idle mode whenever possible, upon expiration of the 6
seconds AT inactivity timer, if low power configuration is enabled
(see the SARA-R4/N4 series AT Commands Manual [2], AT+UPSV
command).
When in low power idle mode, the module switches to the active
mode upon data reception over UART serial interface. The first
character received in low power idle mode wakes up the system: it
is not recognized as valid communication character, and the
recognition of the subsequent characters is guaranteed only after
the complete system wake-up.
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Mode
Description
Transition between operating modes
Active
Module is switched on with application
interfaces enabled or not suspended: the
module is ready to communicate with an
external device by means of the application
interfaces unless power saving configuration is
enabled by AT+CPSMS (see the SARA-R4/N4
series AT Commands Manual [2]).
The modules enter active mode from power-off mode when the
host processor implements a clean switch-on procedure by using
the PWR_ON pin (see 1.6.1).
The modules enter active mode from low power deep sleep mode
upon expiration of “Periodic Update Timer” (see 1.13.9), or when the
host processor implements a clean switch-on procedure by using
the PWR_ON pin (see 1.6.1).
The modules enter power-off mode from active mode when the
host processor implements a clean switch-off procedure (see 1.6.2).
The modules automatically switch from active to low power deep
sleep mode whenever possible, if power saving is enabled (see
1.13.9).
The module switches from active to connected mode when a RF
Tx/Rx data connection is initiated or when RF Tx/Rx activity is
required due to a connection previously initiated.
The module switches from connected to active mode when a RF
Tx/Rx data connection is terminated or suspended.
Connected
RF Tx/Rx data connection is in progress.
The module is prepared to accept data signals
from an external device.
When a data connection is initiated, the module enters connected
mode from active mode.
Connected mode is suspended if Tx/Rx data is not in progress. In
such cases the module automatically switches from connected to
active mode and then, if power saving configuration is enabled by
the AT+CPSMS command, the module automatically switches to low
power deep sleep mode whenever possible. Vice-versa, the module
wakes up from low power deep sleep mode to active mode and
then connected mode if RF Tx/Rx activity is necessary.
When a data connection is terminated, the module returns to the
active mode.
Table 5: SARA-R4/N4 series modules operating modes description
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If PSM mode is enabled,
if AT Inact ivity Timer and
Active Timer are expired
• Upon expirat ion of the
Periodic Update Timer
• Using PWR_ON pin
Incoming/outgoing data
or ot her dedicated device
net work communication
No RF Tx/Rx in progress,
Communicat ion dropped
Remove VCC
Swit ch ON:
• PWR_ON
Not
powered
Power off
ActiveConnected
Deep
Sleep
Swit ch OFF:
• AT+CPWROFF
• PWR_ON
Apply VCC
If low power mode is enabled,
if AT Inactivity Timer is expired
Idle
Data received over UART
Figure 2 describes the transition between the different operating modes.
Figure 2: SARA-R4/N4 series modules operating modes transitions
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53
VCC
52
VCC
51
VCC
SARA-R404M / SARA-R410M / SARA-N410
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
Power
Amplifier
53
VCC
52
VCC
51
VCC
SARA-R412M
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
Power
Amplifier
1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via the three VCC pins that represent the module power supply input.
Voltage must be stable, because during operation, the current drawn by the SARA-R4/N4 series modules
through the VCC pins can vary by several orders of magnitude, depending on the operating mode and
state (as described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.6).
It is important that the supply source is able to withstand both the maximum pulse current occurring during
a transmit burst at maximum power level and the average current consumption occurring during Tx / Rx
call at maximum RF power level (see the SARA-R4 Data Sheet [1]).
SARA-R412M modules provide separate supply inputs over the three VCC pins:
VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most
of the total current drawn of the module when RF transmission is enabled during a call
VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding
minor part of the total current drawn of the module when RF transmission is enabled during a call
The 3 VCC pins of SARA-R404M, SARA-R410M, SARA-N410 modules are internally connected each other
to both the internal RF Power Amplifier and the internal baseband Power Management Unit.
Figure 3 provides a simplified block diagram of SARA-R4/N4 series modules’ internal VCC supply routing.
Figure 3: Block diagram of SARA-R4/N4 series modules’ internal VCC supply routing
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Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
SARA-R404M / SARA-R410M / SARA-N410:
3.2 V / 4.2 V
SARA-R412M:
3.2 V / 4.5 V
RF performance is guaranteed when VCC voltage is
inside the normal operating range limits.
RF performance may be affected when VCC voltage is
outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is
inside the extended operating range limits.
VCC voltage during
normal operation
Within VCC extended operating range:
SARA-R404M / SARA-R410M / SARA-N410:
3.0 V / 4.2 V
SARA-R412M:
3.0 V / 4.5 V
VCC voltage must be above the extended operating
range minimum limit to switch-on the module.
The module may switch-off when the VCC voltage drops
below the extended operating range minimum limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.
VCC average current
Support with adequate margin the highest
averaged VCC current consumption value in
connected mode conditions specified in the SARA-
R4/N4 series Data Sheet [1]
The maximum average current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Section 1.5.1.2 describes current consumption profiles in
connected mode.
VCC peak current
Support with adequate margin the highest peak
VCC current consumption value in Tx connected
mode conditions specified in the SARA-R4/N4
series Data Sheet [1]
The maximum peak Tx current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Section 1.5.1.2 describes current consumption profiles in
connected mode.
VCC voltage drop
during Tx slots
Lower than 400 mV
VCC voltage drop directly affects the RF compliance with
applicable certification schemes.
Figure 6 describes VCC voltage drop during 2G Tx slots.
VCC voltage ripple
during Tx
Noise in the supply pins must be minimized
High supply voltage ripple values during RF
transmissions in connected mode directly affect the RF
compliance with the applicable certification schemes.
VCC under/over-shoot
at start/end of Tx slots
Absent or at least minimized
VCC under/over-shoot directly affects the RF compliance
with applicable certification schemes.
Figure 6 describes VCC voltage under/over-shoot.
1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to
correctly design a VCC supply circuit compliant with the requirements listed in Table 6.
⚠ The supply circuit affects the RF compliance of the device integrating SARA-R4/N4 series modules with
applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if
the requirements summarized in the Table 6 are fulfilled.
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Table 6: Summary of VCC modules supply requirements
SARA-R4/N4 series - System Integration Manual
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Time
[ms]
Current [mA]
0
300
200
100
500
400
Current consumption value
depends on TX power and
act ual antenna load
1 Slot
1 Resource Block
(0.5 ms)
1 LTE Radio Fram e
(10 ms)
1 Slot
1 Resource Block
(0.5 ms)
1 LTE Radio Fram e
(10 ms)
1.5.1.2 VCC current consumption in LTE connected mode
During an LTE connection, the SARA-R4/N4 series modules transmit and receive in half duplex mode.
The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control commands are
logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change
can reach a maximum rate of 2 kHz.
Figure 4 shows an example of SARA-R4/N4 series modules’ current consumption profile versus time in
connected mode: transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-
duplex connected mode.
Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].
Figure 4: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection
1.5.1.3 VCC current consumption in 2G connected mode
When a 2G call is established, the VCC consumption is determined by the current consumption profile
typical of the 2G transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted power,
which is regulated by the network. The transmitted power in the transmit slot is also the more relevant
factor for determining the average current consumption.
If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands at the maximum RF
power control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can
reach a high peak / pulse (see the SARA-R4/N4 series Data Sheet [1]) for 576.9 µs (width of the transmit
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Time
[ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-120 mA
190 0 mA
Peak current depends
on TX power and
act ual antenna load
GSM frame
4.615 ms
(1 frame = 8 slot s)
1.5
1.0
0.5
0.0
2.0
60-120 mA
10 -40 mA
Time
undershoot
overshoot
ripple
drop
Volt age
3.8 V
(typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slot s)
GSM frame
4.615 ms
(1 fram e = 8 slot s)
slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 duty cycle
according to GSM TDMA (Time Division Multiple Access).
If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current
consumption figures are much lower than during transmission in the low bands, due to the 3GPP transmitter
output power specifications.
During a 2G call, current consumption is not significantly high while receiving or in monitor bursts, and it
is low in the bursts unused to transmit / receive.
Figure 5 shows an example of the module current consumption profile versus time in 2G single-slot.
Figure 5: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)
Figure 6 illustrates the VCC voltage profile versus time during a 2G single-slot call, according to the related
VCC current consumption profile described in Figure 5.
Figure 6: Description of the VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)
When a GPRS connection is established, more than one slot can be used to transmit and/or more than one
slot can be used to receive. The transmitted power depends on network conditions, which set the peak
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Time
[ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 fram e = 8 slot s)
Current [A]
60-120mA
GSM frame
4.615 ms
(1 fram e = 8 slot s)
1.5
1.0
0.5
0.0
60-120mA
10-40 mA
200m A
Peak current depends
on TX power and
act ual antenna load
1600 mA
current consumption. But according to GPRS specifications, the maximum transmitted RF power is reduced
if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the
case of a GSM call.
If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level,
the consumption can reach a quite a high peak but lower than the one achievable in 2G single-slot mode.
This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity
of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA.
If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower
than in the 850 or 900 MHz band because of the 3GPP Tx power specifications.
Figure 7 illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz bands,
with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.
Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)
In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one
during GPRS connections: the current consumption profile in GPRS multi-slot class 12 connected mode
illustrated in the Figure 7 is representative for the EDGE multi-slot class 12 connected mode as well.
1.5.1.4 VCC current consumption in low power deep sleep mode (PSM enabled)
The power saving mode configuration is by default disabled, but it can be enabled using the AT+CPSMS
command (see the SARA-R4/N4 series AT Commands Manual [2] and section 1.13.9).
When power saving mode is enabled, the module automatically enters the PSM low power deep sleep
mode whenever possible, reducing current consumption down to a steady value in the µA range: only the
RTC runs with internal 32 kHz reference clock frequency.
Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].
☞ Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the RC
UBX-16029218 - R11 System description Page 26 of 157
oscillator, as a consequence, a very low spike in current consumption will be observed.
SARA-R4/N4 series - System Integration Manual
1.5.1.5 VCC current consumption in low power idle mode (low power enabled)
The low power idle mode configuration is by default disabled, but it can be enabled using the AT+UPSV
command (see the SARA-R4/N4 series AT Commands Manual [2]).
When low power idle mode is enabled, the module automatically enters the low power mode whenever
possible, but it must periodically monitor the paging channel of the current base station (paging block
reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled by
the application. When the module monitors the paging channel, it wakes up to the active mode to enable
the reception of the paging block. In between, the module switches to low power mode. This is known as
discontinuous reception (DRX) or extended discontinuous reception (eDRX).
Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].
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ACTIVE MODE
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)
The active mode is the state where the module is switched on and ready to communicate with an external
device by means of the application interfaces (as the USB or the UART serial interface). The module
processor core is active, and the 19.2 MHz reference clock frequency is used.
If power saving mode and/or low power mode configurations are disabled, as it is by default (see the SARA-
R4/N4 series AT Commands Manual [2], +CPSMS, +UPSV AT commands for details), the module remains in
active mode. Otherwise, if PSM mode and/or low power mode configurations are enabled, the module
enters PSM mode and/or low power mode whenever possible.
Figure 8 illustrates a typical example of the module current consumption profile when the module is in
active mode. In such case, the module is registered with the network and, while active mode is maintained,
the receiver is periodically activated to monitor the paging channel for paging block reception.
Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].
Figure 8: VCC current consumption profile with power saving disabled and module registered with the network: active mode is
always held and the receiver is periodically activated to monitor the paging channel for paging block reception
1.5.2 Generic digital interfaces supply output (V_INT)
The V_INT output pin of the SARA-R4/N4 series modules is generated by the module internal power
management circuitry when the module is switched on and it is not in the deep sleep power saving mode.
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SARA-R4/N4 series - System Integration Manual
The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4/N4 series
Data Sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a
reference voltage rail for external components.
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SARA-R4/N4 series - System Integration Manual
VCC
PWR_ON
RESET_N
V_INT
Internal Rese t
GPIO
System State
BB Pads State Operati onal
OFF
ON
Interna l Re set → Operationa l
Tristate / Floa ting
Interna l Re set
Start of interface
configuration
Module interfaces
are configured
Start-up
event
~4.5 s
0 s
1.6 System function interfaces
1.6.1 Module power-on
When the SARA-R4/N4 series modules are in the not-powered mode (i.e. the VCC module supply is not
applied), they can be switched on as follows:
Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set
at the PWR_ON input pin for a valid time.
When the SARA-R4/N4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving
Mode (PSM), with a valid VCC supply applied, they can be switched on as follows:
Low pulse on the PWR_ON pin for a valid time period
The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics
with voltages and timings are described in the SARA-R4/N4 series Data Sheet [1].
Figure 9 shows the module switch-on sequence from the not-powered mode, with following phases:
The external power supply is applied to the VCC module pins
The PWR_ON pin is held low for a valid time
All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).
The internal reset signal is held low: the baseband core and all digital pins are held in reset state. When
the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to
the default operational configured state. The duration of this phase differs within generic digital
interfaces and USB interface due to host / device enumeration timings.
The module is fully ready to operate after all interfaces are configured.
Figure 9: SARA-R4/N4 series switch-on sequence description
☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:
o the V_INT pin, to sense the start of the SARA-R4/N4 series module switch-on sequence
o the GPIO pin configured to provide the module operating status indication (see SARA-R4/N4 series
Commands Manual [2], AT+UGPIOC), to sense when the module is ready to operate
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