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u-blox SARA-N2, SARA-N3 User Manual

UBX-17005143 - R13 C1-Public www.u-blox.com
SARA-N2 / N3 series
Multi-band NB-IoT (LTE Cat NB1 / NB2) modules
System integration manual
Abstract
This document describes the features and the system integration of the SARA-N2 series and the SARA-N3 series NB-IoT modules. These modules are a complete and cost efficient solution offering from single-band up to multi-band data transmission for the Internet of Things technology in the compact SARA form factor.
SARA-N2 / N3
SARA-N2 / N3 series - System integration manual
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Document information

Title
SARA-N2 / N3 series
Subtitle
Multi-band NB-IoT (LTE Cat NB1 / NB2) modules
Document type
System integration manual
Document number
UBX-17005143
Revision and date
R13
14-Oct-2020
Disclosure restriction
C1-Public
Product status
Corresponding content status
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development / Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production / End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Type number
Modem version
Application version
PCN reference
Product status
SARA-N200
SARA-N200-02B-00
06.57
A07.03
UBX-18005015
End of life
SARA-N200-02B-01
06.57
A09.06
UBX-18048558
End of life
SARA-N200-02B-02
06.57
A10.08
UBX-19030865
End of life
SARA-N201
SARA-N201-02B-00
06.57
A07.03
UBX-18005015
End of life
SARA-N201-02B-01
06.57
A08.05
UBX-19030865
End of life
SARA-N210
SARA-N210-02B-00
06.57
A07.03
UBX-18005015
End of life
SARA-N210-02B-01
06.57
A09.06
UBX-18048558
End of life
SARA-N210-02B-02
06.57
A10.08
UBX-19030865
End of life
SARA-N211
SARA-N211-02X-00
06.57
A07.03
UBX-18005015
End of life
SARA-N211-02X-01
06.57
A09.06
UBX-18048558
End of life
SARA-N211-02X-02
06.57
A10.08
UBX-19030865
End of life
SARA-N280
SARA-N280-02B-00
06.57
A07.03
UBX-18005015
End of life
SARA-N280-02B-01
06.57
A09.06
UBX-19030865
End of life
SARA-N300
SARA-N300-00B-00
18.10
A01.04
UBX-20026729
Engineering sample
SARA-N310
SARA-N310-00X-00
18.13
A01.00
UBX-20033555
Initial production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com.
Copyright © u-blox AG.
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Contents

Document information ................................................................................................................................ 2
Contents .......................................................................................................................................................... 3
1 System description ............................................................................................................................... 6
1.1 Overview ........................................................................................................................................................ 6
1.2 Architecture ................................................................................................................................................. 8
1.3 Pin-out ........................................................................................................................................................... 9
1.4 Operating modes ....................................................................................................................................... 13
1.5 Supply interfaces ...................................................................................................................................... 15
1.5.1 Module supply input (VCC) ............................................................................................................. 15
1.5.2 RTC supply (V_BCKP) ....................................................................................................................... 16
1.5.3 Interfaces supply output (V_INT) ................................................................................................... 17
1.6 System function interfaces .................................................................................................................... 18
1.6.1 Module power-on .............................................................................................................................. 18
1.6.2 Module power-off .............................................................................................................................. 20
1.6.3 Module reset .......................................................................................................................................21
1.6.4 Voltage selection of interfaces (VSEL) .........................................................................................21
1.7 Antenna interface ..................................................................................................................................... 22
1.7.1 Cellular antenna RF interface (ANT) ............................................................................................. 22
1.7.2 Bluetooth antenna RF interface (ANT_BT) ................................................................................. 23
1.7.3 Antenna detection interface (ANT_DET)..................................................................................... 23
1.8 SIM interface .............................................................................................................................................. 23
1.9 Serial interfaces ........................................................................................................................................ 24
1.9.1 Main primary UART interface ........................................................................................................ 24
1.9.2 Secondary auxiliary UART interface ............................................................................................. 27
1.9.3 Additional UART interface .............................................................................................................. 27
1.9.4 DDC (I2C) interface ........................................................................................................................... 28
1.10 ADC .............................................................................................................................................................. 28
1.11 General Purpose Input/Output (GPIO) .................................................................................................. 28
1.12 Reserved pins (RSVD) .............................................................................................................................. 29
2 Design-in ................................................................................................................................................ 30
2.1 Overview ......................................................................................................................................................30
2.2 Supply interfaces ...................................................................................................................................... 31
2.2.1 Module supply input (VCC) ............................................................................................................. 31
2.2.2 RTC supply (V_BCKP) ....................................................................................................................... 40
2.2.3 Interfaces supply output (V_INT) .................................................................................................. 41
2.3 System functions interfaces .................................................................................................................. 42
2.3.1 Module power-on (PWR_ON) .......................................................................................................... 42
2.3.2 Module reset (RESET_N) ................................................................................................................. 43
2.3.3 Voltage selection of interfaces (VSEL) ........................................................................................ 44
2.4 Antenna interface ..................................................................................................................................... 45
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2.4.1 Cellular antenna RF interface (ANT) ............................................................................................. 45
2.4.2 Bluetooth antenna RF interface (ANT_BT) ................................................................................. 52
2.4.3 Antenna detection interface (ANT_DET)..................................................................................... 52
2.5 SIM interface .............................................................................................................................................. 55
2.6 Serial interfaces ........................................................................................................................................ 60
2.6.1 Main primary UART interface ........................................................................................................ 60
2.6.2 Secondary auxiliary UART interface ............................................................................................. 65
2.6.3 Additional UART interface .............................................................................................................. 66
2.6.4 DDC (I2C) interface ........................................................................................................................... 66
2.7 ADC .............................................................................................................................................................. 67
2.8 General Purpose Input/Output (GPIO) .................................................................................................. 68
2.9 Reserved pins (RSVD) .............................................................................................................................. 68
2.10 Module placement .................................................................................................................................... 69
2.11 Module footprint and paste mask ......................................................................................................... 70
2.12 Integration in devices intended for use in potentially explosive environments ............................ 71
2.12.1 General guidelines ............................................................................................................................. 71
2.12.2 Guidelines for VCC supply circuit design ..................................................................................... 72
2.12.3 Guidelines for antenna RF interface design ................................................................................ 74
2.13 Schematic for SARA-N2 / N3 series module integration .................................................................. 75
2.14 Design-in checklists ................................................................................................................................. 77
2.14.1 Schematic checklist ......................................................................................................................... 77
2.14.2 Layout checklist ................................................................................................................................ 77
2.14.3 Antenna checklist ............................................................................................................................. 77
3 Handling and soldering ...................................................................................................................... 78
3.1 Packaging, shipping, storage and moisture preconditioning .......................................................... 78
3.2 Handling ...................................................................................................................................................... 78
3.3 Soldering ..................................................................................................................................................... 79
3.3.1 Soldering paste ................................................................................................................................. 79
3.3.2 Reflow soldering ................................................................................................................................ 79
3.3.3 Optical inspection ............................................................................................................................ 80
3.3.4 Cleaning ............................................................................................................................................. 80
3.3.5 Repeated reflow soldering .............................................................................................................. 81
3.3.6 Wave soldering .................................................................................................................................. 81
3.3.7 Hand soldering .................................................................................................................................. 81
3.3.8 Rework ................................................................................................................................................ 81
3.3.9 Conformal coating ............................................................................................................................ 81
3.3.10 Casting ................................................................................................................................................ 82
3.3.11 Grounding metal covers .................................................................................................................. 82
3.3.12 Use of ultrasonic processes ........................................................................................................... 82
4 Approvals ............................................................................................................................................... 83
4.1 Approvals overview ................................................................................................................................... 83
4.2 European Conformance ........................................................................................................................... 84
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4.3 ATEX / IECEx conformance ..................................................................................................................... 85
4.4 Chinese conformance .............................................................................................................................. 86
4.5 Taiwanese conformance ......................................................................................................................... 87
4.6 Australian conformance .......................................................................................................................... 87
5 Product testing ................................................................................................................................... 88
5.1 u-blox in-series production test ............................................................................................................. 88
5.2 Test parameters for OEM manufacturer ............................................................................................. 88
5.2.1 “Go/No go” tests for integrated devices ...................................................................................... 89
5.2.2 RF functional tests ........................................................................................................................... 89
Appendix ........................................................................................................................................................ 91
A Migration between SARA modules ................................................................................................ 91
B Glossary .................................................................................................................................................. 91
Related documents ................................................................................................................................... 93
Revision history .......................................................................................................................................... 94
Contact .......................................................................................................................................................... 95
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1 System description

1.1 Overview

SARA-N2 / N3 series modules are Narrow Band Internet of Things (NB-IoT) solutions in the miniature SARA LGA form factor (26.0 x 16.0 mm, 96-pin), offering LTE Cat NB1 / NB2 data communication over an extended operating temperature range of –40 to +85 °C, with extremely low power consumption.
SARA-N2 series include four variants supporting single-band LTE Cat NB1 data communication for Europe, China, APAC and South America, plus a dual-band variant mainly designed for Europe.
SARA-N3 series offer multi-band LTE Cat NB2 data communication enabling multi-regional coverage, supporting several new functionalities for NB-IoT products, including features like TCP, MQTT, MQTT-SN, DTLS, SSL/TLS, LwM2M, HTTP(S) and many others.
SARA-N2 / N3 series modules are ideally suited to battery-powered IoT applications characterized by occasional communications of small amounts of data.
The modules are the optimal choice for IoT devices designed to operate in locations with very limited coverage and requiring low energy consumption to permit a very long operating life with the primary batteries. Examples of applications include and are not limited to: smart grids, smart metering, telematics, street lighting, environmental monitoring and control, security and asset tracking.
Table 1 describes a summary of interfaces and features provided by SARA-N2 / N3 series modules.
Module
Region
Cellular RAT
Interfaces
Features
Grade
3GPP release baseline 3GPP LTE Category LTE FDD bands UARTs USB
DDC (I2C) USIM
ADCs
GPIOs Antenna supervisor Power Save Mode eDRX
Bluetooth 4.2 (BR/EDR and BLE) Embedded TCP/UDP stack Embedded CoAP
, MQTT
, MQTT
-SN
Embedded HTTP, FTP, PPP, DNS Embedded
TLS, DTLS
IPv4
IPv4 / IPv6 LwM2M
Device Management
Last gasp FW update over AT (FOAT) FW update over the air (FOTA) Standard Professional Automotive
SARA-N200
Europe
APAC
13
NB1
8 ●
● ● ● ●
●
1
●
2
● ● ● ●
SARA-N201
APAC
13
NB1
5 ●
● ● ● ●
●
1
●
2
● ● ● ●
SARA-N210
Europe
13
NB1
20 ●
● ● ● ●
●
1
●
2
● ● ● ●
SARA-N211
Europe
13
NB1
8,20
● ● ● ● ●
●
1
●
2
● ● ● ●
SARA-N280
S.America
APAC
13
NB1
28 ●
● ● ● ●
●
1
●
2
● ● ● ●
SARA-N300
China
14
NB2
3,5,8
● ○ ● ● ● ● ● ● ○ ●
●3 ● ● ● ● ● ● ● ●
SARA-N310
Global
14
NB2
3,5,8
20,28,★
● ○ ● ● ● ● ● ● ○ ● ● ●
● ● ● ● ● ● ● ●
● = Supported ○ = Available in future FW ★ = Additional bands (1, 2, 4, 12, 13, 18, 19, 26, 66, 71, 85) available in future FW
Table 1: SARA-N2 / N3 series characteristics summary
1
Only embedded UDP stack is supported
2
Only embedded CoAP is supported
3
Only embedded CoAP and MQTT-SN are supported
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Table 2 summarizes cellular radio access technology characteristics of SARA-N2 / N3 series modules.
Item
SARA-N2 series
SARA-N3 series
Protocol stack
3GPP release 13
3GPP release 144
Radio Access Technology
LTE Category NB1 Half-Duplex Single-tone Single HARQ process eDRX Power Saving Mode Coverage enhancement A and B
LTE Category NB2 Half-Duplex Multi-tone Two HARQ process eDRX Power Saving Mode Coverage enhancement A and B
Operating band
SARA-N200:
• Band 8 (900 MHz) SARA-N201:
• Band 5 (850 MHz) SARA-N210:
• Band 20 (800 MHz) SARA-N211:
• Band 8 (900 MHz)
• Band 20 (800 MHz)
SARA-N280:
• Band 28 (700 MHz)
SARA-N300:
• Band 5 (850 MHz)
• Band 8 (900 MHz)
• Band 20 (800 MHz)
SARA-N3105:
• Band 3 (1800 MHz)
• Band 5 (850 MHz)
• Band 8 (900 MHz)
• Band 20 (800 MHz)
• Band 28 (700 MHz)
Power Class
Class 3 (23 dBm)6
Class 3 (23 dBm)6
Deployment mode
In-Band Guard-Band Standalone
In-Band Guard-Band Standalone
Data rate
Up to 31.25 kb/s UL Up to 27.2 kb/s DL
Up to 140 kb/s UL Up to 125 kb/s DL
Protocols and other
UDP IP CoAP
TCP IP / UDP IP CoAP DTLS MQTT7 MQTT-SN LwM2M Device Management Objects7 HTTP/HTTPS FTP PPP/DNS SSL, TLS Radio Policy Manager7 SIM provisioning7
Table 2: SARA-N2 / N3 series NB-IoT characteristics summary
4
Key subset of features
5
Additional bands (1, 2, 4, 12, 13, 18, 19, 26, 66, 71, 85) available in future FW versions
6
Configurable to other Power Class by AT command
7
Not supported by SARA-N300-00B
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1.2 Architecture

Figure 1 and Figure 2 summarize the architecture of SARA-N2 series and SARA-N3 series modules
respectively, describing the internal blocks of the modules, consisting of the RF, Baseband and Power Management main sections, and the available interfaces.
Memory
V_INT
38.4 MHz
32.768 kHz
RF
transceiver
Power
management
Baseband
ANT
SAW Filter
Switch
PA
VCC (supply)
DDC (I2C)
UART
SIM
Secondary UART
RESET_N
GPIO
Antenna detection
Figure 1: SARA-N2 series modules block diagram
☞ The “02" product version of SARA-N2 series modules do not support the following interfaces,
which should not be driven by external devices:
o Antenna detection o DDC (I2C) interface
26 MHz
32.768 kHz
RF
transceiver
Baseband
ANT
Switch
PA
V_BCKP (RTC)
V_INT (I/O)
Power
management
VCC (supply)
Memory
Reset
Power-on
SIM
SIM card detection
UART (Primary main)
UART (Secondary auxiliary)
DDC (I2C)
ADC
GPIOs
Antenna detection
VSEL (I/O voltage selection)
UART (Flashing & tracing)
BT
ANT_BT
Figure 2: SARA-N3 series block diagram
☞ The “00" product version of SARA-N3 series modules do not support the following interfaces,
which should not be driven by external devices:
o Bluetooth interface (ANT_BT) o Secondary auxiliary UART interface (UART AUX) o DDC (I2C) interface
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The RF section is composed of the following main elements:
• LTE power amplifier, which amplifies the signals modulated by the RF transceiver
• RF switches, which connect the antenna input/output pin (ANT) of the module to the suitable
RX/TX path
• RX low-loss filters
• 38.4 MHz (SARA-N2 series) / 26.0 MHz (SARA-N3 series) crystal oscillator for the clock reference
in active-mode and connected-mode
The Baseband and Power Management section is composed of the following main elements:
• Baseband processor
• Flash memory
• Voltage regulators to derive all the system supply voltages from the module supply VCC
• Circuit for the RTC clock reference in low power deep-sleep

1.3 Pin-out

Table 3 lists the pin-out of the SARA-N2 / N3 series modules, with pins grouped by function
Function
Pin name
Modules
Pin No
I/O
Description
Remarks
Power
VCC
All
51,52,53
I
Module supply input
All VCC pins must be connected to external supply. VCC supply circuit affects the RF performance and
compliance of the device integrating the module with applicable required certification schemes.
See section 1.5.1 for description and requirements. See section 2.2.1 for external circuit design-in.
GND
All
1,3,5,14, 20,22,30, 32,43,50, 54,55,57, 58,60,61, 63-96
N/A
Ground
All GND pins have to be connected to external ground. External ground connection affects the RF and thermal
performance of the device. See section 2.2.1.8 for external circuit design-in.
GND
SARA-N2
21,59
N/A
Ground
All GND pins have to be connected to external ground. External ground connection affects the RF and thermal
performance of the device. See section 2.2.1.8 for external circuit design-in.
V_BCKP
SARA-N3
2
I/O
RTC supply input/output
See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.
V_INT
All 4 O
Generic Digital Interfaces supply output
SARA-N2 series modules:
• Supply output generated by internal linear LDO
regulator when the radio is on
• Voltage domain of I2C and GPIOs
• V_INT = 1.8 V (typical)
SARA-N3 series modules:
• Supply output generated by internal linear LDO
regulator when the module is on
• Voltage domain of UARTs, I2C and GPIOs
• V_INT = 1.8 V (typ.), if VSEL is connected to GND
• V_INT = 2.8 V (typ.), if VSEL is unconnected
Provide a test point on this pin for diagnostic purpose. See section 1.5.3 for functional description. See section 2.2.3 for external circuit design-in.
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Function
Pin name
Modules
Pin No
I/O
Description
Remarks
System
PWR_ON
SARA-N3
15 I Power-on input
Internal pull-up. Provide a test point on this pin for diagnostic purpose. See section 1.6.1, 1.6.2 for functional description. See section 2.3.1 for external circuit design-in.
RESET_N
All
18 I HW reset input
Internal pull-up. Provide a test point on this pin for diagnostic purpose. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in.
VSEL
SARA-N3
21 I Voltage selection
Input to select the operating voltage of the V_INT supply output, voltage domain of UARTs, I2C, GPIOs.
V_INT = 1.8 V (typical), if VSEL pin is connected to GND V_INT = 2.8 V (typical), if VSEL pin is unconnected
See section 1.6.4 for functional description. See section 2.3.3 for external circuit design-in.
Antenna
ANT
All
56
I/O
Cellular RF input/output
50 nominal characteristic impedance. Antenna circuit affects the RF performance and
compliance of the device integrating the module with applicable required certification schemes. See section 1.7.1 for description and requirements. See section 2.4.1 for external circuit design-in.
ANT_BT
SARA-N3
59
I/O
Bluetooth RF input/output
50 nominal characteristic impedance. See section 1.7.2 for description and requirements. See section 2.4.2 for external circuit design-in.
ANT_DET
All
62
I
Input for antenna detection
ANT_DET not supported by SARA-N2 modules. ADC input usable for antenna detection function. See section 1.7.3 for functional description. See section 2.4.3 for external circuit design-in.
SIM
VSIM
All
41
O
SIM supply output
Supply output for external SIM / UICC See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_IO
All
39
I/O
SIM data
Data line for communication with external SIM, operating at VSIM voltage level.
Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_CLK
All
38 O SIM clock
Clock for external SIM, operating at VSIM voltage level. See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_RST
All
40 O SIM reset
Reset for external SIM, operating at VSIM voltage level See section 1.8 for functional description. See section 2.5 for external circuit design-in.
UART
(main)
RXD
All
13 O Data output
Circuit 104 (RXD) in ITU-T V.24 SARA-N2 series modules:
• Supporting AT communication, FOAT and FW
upgrade via dedicated tool
• VCC voltage level SARA-N3 series modules:
• Supporting AT communication and FOAT
• V_INT voltage level
Provide a test point on this pin for diagnostic purpose. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
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Function
Pin name
Modules
Pin No
I/O
Description
Remarks
TXD
All
12 I Data input
Circuit 103 (TXD) in ITU-T V.24 SARA-N2 series modules:
• Supporting AT communication, FOAT and FW
upgrade via dedicated tool
• VCC voltage level, without internal pull-up/down SARA-N3 series modules:
• Supporting AT communication and FOAT
• V_INT voltage level, with internal pull-up
Provide a test point on this pin for diagnostic purpose. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
CTS
All
11
O
Clear To Send output
Circuit 106 (CTS) in ITU-T V.24 SARA-N2 series modules:
• HW flow control not supported by “02” versions
• Configurable as RI and other
• VCC voltage level
SARA-N3 series modules:
• HW flow control output
• Configurable as RI and other
• V_INT voltage level
See section 1.9.1 and 1.11 for functional description. See section 2.6.1 for external circuit design-in.
RTS
All
10
I
Request To Send input
Circuit 105 (RTS) in ITU-T V.24 SARA-N2 series modules:
• HW flow control not supported by “02” versions
• VCC voltage level, with internal pull-up
SARA-N3 series modules:
• HW flow control input
• V_INT voltage level, with internal pull-up by default
See section 1.9.1 and 1.11 for functional description. See section 2.6.1 for external circuit design-in.
RI
SARA-N3
7 O Ring Indicator
Circuit 125 (RI) in ITU-T V.24, at V_INT voltage level See section 1.9.1 and 1.11 for functional description. See section 2.6.1 for external circuit design-in.
DSR
SARA-N3
6 O Data Set Ready
Circuit 107 (DSR) in ITU-T V.24, at V_INT voltage level DSR not supported by ‘00’ product versions. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
DCD
SARA-N3
8
O
Data Carrier Detect
Circuit 109 (DCD) in ITU-T V.24, at V_INT voltage level DCD not supported by ‘00’ product versions. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
DTR
SARA-N3
9
I
Data Terminal Ready
Circuit 108/2 (DTR) in ITU-T V.24, at V_INT voltage level DTR not supported by ‘00’ product versions. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
UART
(auxiliary)
RXD_AUX
SARA-N3
19 O Data output
Circuit 104 (RXD) in ITU-T V.24, at V_INT voltage level UART AUX not supported by ‘00’ product versions. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.
TXD_AUX
SARA-N3
17 I Data input
Circuit 103 (TXD) in ITU-T V.24, at V_INT voltage level UART AUX not supported by ‘00’ product versions. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.
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Function
Pin name
Modules
Pin No
I/O
Description
Remarks
UART
(additional)
RXD_FT
SARA-N3
28 O Data output
Circuit 104 (RXD) in ITU-T V.24, at V_INT voltage level. Supporting FW update via u-blox EasyFlash tool and
Trace log. Provide a test point for FW upgrade and diagnostic. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.
TXD_FT
SARA-N3
29 I Data input
Circuit 103 (TXD) in ITU-T V.24, at V_INT voltage level. Supporting FW update via u-blox EasyFlash tool and
Trace log. Provide a test point for FW upgrade and diagnostic. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.
GPIO1
SARA-N2
16 O Data output
Circuit 104 (RXD) in ITU-T V.24, at V_INT voltage level. Supporting Trace diagnostic logging. Provide a test point on this pin for diagnostic. See sections 1.9.3 and 1.11 for functional description. See sections 2.6.3 and 2.8 for external circuit design-in.
DDC
SCL
All
27 O I2C bus clock line
Open drain, at V_INT voltage level. I2C not supported by SARA-N2 "02" versions. I2C not supported by SARA-N3 "00" versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.
SDA
All
26
I/O
I2C bus data line
Open drain, at V_INT voltage level. I2C not supported by SARA-N2 "02" versions. I2C not supported by SARA-N3 "00" versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.
GPIO
GPIO1
SARA-N3
16
I/O
GPIO
GPIO, at V_INT voltage level. See section 1.11 for functional description. See section 2.8 for external circuit design-in.
GPIO2
SARA-N2
24
I/O
GPIO
GPIO2 not supported by "02" product versions.
SARA-N3
23
I/O
GPIO
GPIO, at V_INT voltage level. See section 1.11 for functional description. See section 2.8 for external circuit design-in.
GPIO3
SARA-N3
24
I/O
GPIO
GPIO, at V_INT voltage level. See section 1.11 for functional description. See section 2.8 for external circuit design-in.
GPIO4
SARA-N3
25
I/O
GPIO
GPIO, at V_INT voltage level. See section 1.11 for functional description. See section 2.8 for external circuit design-in.
GPIO5
SARA-N3
42
I/O
GPIO
GPIO, at V_INT voltage level. See section 1.11 for functional description. See section 2.8 for external circuit design-in.
ADC
ADC1
SARA-N3
33 I ADC input
See section 1.10 for functional description. See section 2.7 for external circuit design-in.
Reserved
RSVD
SARA-N2
33
N/A
RESERVED pin
This pin can be connected to GND. See sections 1.12 and 2.9.
RSVD
SARA-N2
2, 6-9, 15,17,19, 23, 25, 28,29,42
N/A
RESERVED pin
Leave unconnected. See sections 1.12 and 2.9.
RSVD
All
31,34-37, 44-49
N/A
RESERVED pin
Leave unconnected. See sections 1.12 and 2.9.
Table 3: SARA-N2 / N3 series modules pin definition, grouped by function
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1.4 Operating modes

SARA-N2 / N3 series modules have several operating modes as defined in Table 4.
General Status
Operating Mode
Definition
Power-down
Not-Powered mode
VCC supply not present or below the operating range. The module is switched off.
Power-Off mode 8
VCC supply within the operating range, with the module switched off.
Normal operation
Deep-sleep mode
Module processor runs with internal 32 kHz reference. Lowest possible power mode, with current consumption in the ~µA range.
Sleep mode 8
Module processor runs with internal 32 kHz reference. PSRAM does not power down, with current consumption in the ~100 µA range.
Idle mode 8
Module processor runs with internal 32 kHz reference. Low power mode, with current consumption in the ~mA range.
Active mode
Module processor runs with internal 38.4 MHz / 26 MHz reference. Data transmission or reception not in progress.
Connected mode
Module processor runs with internal 38.4 MHz / 26 MHz reference. Data transmission or reception in progress.
Table 4: SARA-N2 / N3 series modules’ operating modes definition
Figure 3 and Figure 4 illustrate the transition between the different operating modes.
The initial operating mode of SARA-N2 / N3 series modules is the one with VCC supply not present or below the operating range: the modules are switched off in non-powered mode.
Once a valid VCC supply is applied to the SARA-N2 modules, this event triggers the switch on routine of the modules that subsequently enter the active mode.
On the other hand, once a valid VCC supply is applied to the SARA-N3 series modules, they remain switched off in power-off mode. Then the proper toggling of the PWR_ON input line is necessary to trigger the switch on routine of the modules that subsequently enter the active mode.
SARA-N2 / N3 series modules are fully ready to operate when in active mode. Then, the SARA-N2 series modules switch from active mode to deep sleep mode whenever possible,
entering the lowest possible power mode, with current consumption in the ~µA range. The UART interface is still completely functional and the module can accept and respond to any AT command, entering back into the active mode as in case of network paging reception and as in case of expiration of the “Periodic Update Timer” according to the Power Saving Mode defined in 3GPP release 13.
Instead, the SARA-N3 series modules switch from active mode to the idle mode whenever possible, entering the low power mode, if enabled by a dedicated AT command, with current consumption in the ~mA range. The UART interface is still completely functional and the module can accept and respond to any AT command, entering back into the active mode as in case of network paging reception.
According to AT+NVSETPM setting, the SARA-N3 series can switch between modes. It can switch from active mode to sleep mode if the eDRX feature is enabled and set to let the module go to sleep for time periods of less than 300 s. It can switch from active mode to deep sleep mode if the Power Saving Mode is enabled or if the eDRX feature is enabled and set to let the module go to sleep for time periods of more than 300 s, thus entering the lowest possible power mode, with current consumption in the ~µA range (Power Saving Mode and eDRX are defined in 3GPP release 13). In both sleep mode and deep sleep mode, the UART interface is not functional: a wake up event, consisting for example in proper toggling of the PWR_ON line or in expiration of the “Periodic Update Timer”, is necessary to trigger the wake up routine of the modules that subsequently enter back into the active mode.
☞ See the SARA-N2 / SARA-N3 series AT commands manual [4] for the +NVSETPM AT command
and for configuration of PSM and eDRX features.
8
Not available in SARA-N2 series modules
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SARA-N2 / N3 series modules switch from active mode to connected mode upon RF transmission or reception operations turning back to active mode once RF operations are terminated or suspended.
The switch off routine of the SARA-N3 series modules can be properly triggered by the dedicated AT command or by proper toggling of the PWR_ON line. The modules subsequently enter the power-off mode and then they enter the non-powered mode by removing the VCC supply.
Switch ON:
• Apply VCC
If there is no activity for
a defined time interval
• Network paging
• Data received over UART
• Expiration of Periodic Update Timer
Incoming/outgoing data or other dedicated device network communication
No RF Tx/Rx in progress
Not
powered
ActiveConnected
Deep
Sleep
Switch OFF:
• Remove VCC
Figure 3: SARA-N2 series modules’ operating modes transitions
• Using PWR_ON
• Expiration of timer
Incoming/outgoing data or other dedicated device network communication
No RF Tx/Rx in progress
Remove VCC
Switch ON:
• PWR_ON
Not
powered
Power off
ActiveConnected
Deep
sleep
Switch OFF:
• AT+CPWROFF
• PWR_ON
Apply VCC
If low power mode is enabled, if AT inactivity timer is expired
Idle
• Network paging
• Data received
over UART
Sleep
Figure 4: SARA-N3 series modules’ operating modes transitions
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1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via all the three VCC pins that represent the module power supply input.
The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators, including V_INT (digital interfaces supply) and VSIM (SIM card supply).
During operation, the current drawn by the SARA-N2 / N3 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during data transmission at maximum power level in connected mode, to the low current consumption during deep-sleep mode (as described in section 1.5.1.2).
1.5.1.1 VCC supply requirements
Table 5 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the
suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 5.
⚠ VCC supply circuit design may affect the RF compliance of the device integrating SARA-N2 / N3
series modules with applicable required certification schemes. Compliance is not guaranteed if the VCC requirements summarized in the Table 5 are not fulfilled.
Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
• SARA-N2: 3.1 V min. / 4.0 V max
• SARA-N3: 3.2 V min. / 4.2 V max
The module cannot be switched on if VCC voltage value is below the normal operating range minimum limit.
Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for at least more than 3 s after the module switch-on.
VCC voltage during normal operation
Within VCC extended operating range:
• SARA-N2: 2.75 V min. / 4.2 V max
• SARA-N3: 2.6 V min. / 4.2 V max
The module may switch off when VCC voltage drops below the extended operating range minimum limit. Operation above extended operating range limit is not recommended and may affect device reliability. When operating below the normal operating range minimum limit, the internal PA may not be able to transmit at the network-required power level.
VCC average current
Support with margin the highest averaged VCC current consumption value in connected mode specified in the SARA-N2 data sheet [1] or in the SARA-N3 data sheet [2].
The maximum average current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage.
VCC voltage ripple
Noise in the supply has to be minimized
High supply voltage ripple values during RF transmissions in connected-mode directly affect the RF compliance with applicable certification schemes.
Table 5: Summary of VCC supply requirements
☞ For the additional specific requirements applicable to the integration of the SARA-N211 and the
SARA-N310 modules in devices intended for use in potentially explosive atmospheres, see the guidelines reported in section 2.12.
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1.5.1.2 VCC current consumption profile
Figure 5 shows an example of the module VCC current consumption profile starting from the switch-
on event, followed by different phases and operating modes:
• Network registration and context activation procedure
• Transmission of an up-link datagram
• RRC connection release and related signaling operations
• Cyclic paging reception
• Deep sleep mode
Timings in the figure are purely indicative since these may significantly change depending on the network signaling activity. The current consumption peaks occur when the module is in the connected (transmitting) mode and the value of these peaks is strictly dependent on the transmitted power, which is regulated by the network. See the electrical specification section in the SARA-N2 series data sheet [1] or SARA-N3 series data sheet [2] for more details about the current consumption values in the different modes and the influence of the transmitting power level.
A proper power supply circuit for SARA-N2 / N3 series modules must be able to withstand the current values present during the data transmission at maximum power, even though NB-IoT systems should be designed to keep the module in deep-sleep mode for most of the time, with an extremely low current consumption in the range of few microamps.
Current [mA]
200
1 50
1 00
50
0
5 10 15 20 25 30 4035
Time [s]
Registration and
context activation
RRC connection release
(signaling operations)
Up-link
data
45 50 6055
Cyclic paging reception Deep Sleep
250
65 70 8075 85 90 1 00950
Figure 5: Example of module current consumption from the switch-on event up to deep-sleep mode

1.5.2 RTC supply (V_BCKP)

☞ The RTC supply (V_BCKP pin) is not available on SARA-N2 series modules.
V_BCKP is the Real Time Clock (RTC) supply of SARA-N3 series modules. When VCC voltage is within
the valid operating range, the internal Power Management Unit (PMU) supplies the RTC and the same supply voltage is available on the V_BCKP pin. If the VCC voltage is under the minimum operating limit (e.g. during non powered mode), the RTC can be externally supplied through the V_BCKP pin.
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1.5.3 Interfaces supply output (V_INT)

The same voltage domain internally used as supply for the generic digital interfaces of SARA-N2 / N3 series modules is also available on the V_INT output pin, as illustrated in Figure 6.
In detail, the V_INT supply rail is used internally to supply the:
• I2C interface, and the GPIO pins of SARA-N2 series modules
• UART interfaces, the I2C interface, and the GPIO pins of SARA-N3 series modules
The internal regulator that generates the V_INT supply output is a low drop out (LDO) converter, which is directly supplied from the VCC main supply input of the module.
The V_INT supply output provides internal short circuit protection to limit start-up current and protect the load to short circuits.
The V_INT voltage regulator output of SARA-N2 series modules is disabled (i.e. 0 V) when the module is switched off, and it can be used to monitor the operating mode when the module is switched on:
• When the radio is off, the voltage level is low (i.e. 0 V)
• When the radio is on, the voltage level is high (i.e. 1.8 V)
The V_INT voltage regulator output of SARA-N3 series modules is disabled (i.e. 0 V) when the module is switched off, and it can be used to monitor the operating mode of the module as follows:
• When the module is off, or in deep sleep mode, the voltage level is low (i.e. 0 V)
• When the module is on, outside deep sleep mode, the voltage level is high (i.e. 1.8 V or 2.8 V)
The V_INT operating voltage of SARA-N3 series modules can be selected using the VSEL input pin:
• If the VSEL input pin is connected to GND, the digital I/O interfaces operate at 1.8 V
• If the VSEL input pin is left unconnected, the digital I/O interfaces operate at 2.8 V
☞ If the VSEL input pin is left unconnected, the VCC voltage shall be inside normal operating range
to let the digital I/O interfaces work correctly (see SARA-N3 series data sheet [2] for more details).
☞ Provide a test point connected to the V_INT pin for diagnostic purpose.
Baseband
processor
51
VCC
52
VCC
53
VCC
4
V_INT
LDO
Digital I/O interfaces
Power
management
SARA-N2/N3 series
Figure 6: SARA-N2 / N3 series interfaces supply output (V_INT) simplified block diagram
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1.6 System function interfaces

1.6.1 Module power-on

1.6.1.1 Switch-on events
When the SARA-N2 series modules are in the non-powered mode (i.e. switched off, with the VCC module supply not applied), the switch on routine of the module can be triggered by:
• Rising edge on the VCC supply input to a valid voltage value for module supply, starting from a
voltage value lower than 1.8 V, so that the module switches on applying a proper VCC supply within the normal operating range (see SARA-N2 series data sheet [1]).
• Alternately, the RESET_N pin can be held low during the VCC rising edge, so that the module
switches on by releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal range.
When the SARA-N3 series modules are in the non-powered mode (i.e. switched off, with the VCC module supply not applied), the switch on routine of the module can be triggered by:
• Applying a VCC supply within the normal operating range of the module, and then forcing a low
level on the PWR_ON input pin (normally high due to internal pull-up) for a valid time period (see SARA-N3 series data sheet [2]).
• Alternately, the RESET_N pin can be held low during the VCC rising edge, so that the module
switches on by releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal range.
When the SARA-N3 series modules are in power off mode (i.e. switched off, with valid VCC supply applied), the switch on routine of the module can be triggered by:
• Forcing a low level on the PWR_ON input pin (normally high due to internal pull-up) for a valid time
period (see SARA-N3 series data sheet [2]).
When the SARA-N3 series modules are in deep sleep mode (i.e. in the Power Saving Mode defined by 3GPP Rel. 13, with valid VCC supply applied), the wake-up routine of the module can be triggered by:
• Forcing a low level on the PWR_ON input pin (normally high due to internal pull-up) for a valid time
period (see SARA-N3 series data sheet [2]).
As illustrated in Figure 7, the PWR_ON line of SARA-N3 series modules is equipped with an internal pull-up.
Baseband processor
15
PWR_ON
SARA-N3 series
Power-on
Power management
Power-on
1.1 V
Figure 7: SARA-N3 series PWR_ON input equivalent circuit description
☞ The PWR_ON input pin is not available on SARA-N2 series modules.
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1.6.1.2 Switch-on sequence from not-powered mode
Figure 8 shows the switch-on sequence of SARA-N2 modules starting from the non-powered mode:
• The external supply is being applied to the VCC inputs, representing the start-up event.
• The RESET_N line rises suddenly to high logic level due to internal pull-up to VCC.
• Then, the V_INT generic digital interfaces supply output is enabled by the integrated PMU.
• The RXD UART data output pin also rises to the high logic level, at VCC voltage value
• A greeting message is sent on the RXD pin (for more details see AT commands manual [4])
• From now on the module is fully operational and the UART interface is functional
VCC
RESET_N
V_INT
HIGH when radio is ON
LOW when radio is OFF
RXD
System state
OFF
ON
0 s
~3.5 s
Module is
operational
Start-up
event
Greeting te xt
Figure 8: SARA-N2 series power-on sequence from not-powered mode
Figure 9 shows the switch on sequence of SARA-N3 modules starting from the non-powered mode:
• The external supply is being applied to the VCC inputs.
• The PWR_ON and RESET_N lines rise suddenly to high logic level due to internal pull-up.
• Then, the PWR_ON line is set low for a proper time period, representing the start-up event.
• Then, the V_INT generic digital interfaces supply output is enabled by the integrated PMU.
• The RXD UART data output pin also rises to the high logic level, at V_INT voltage value.
• A greeting message is sent on the RXD pin (for more details, see AT commands manual [4])
• From now on the module is fully operational and the UART interface is functional
VCC
PWR_ON
RESET_N
V_INT
RXD
System state
OFF
ON
Module is
operational
Start-up
event
Greeting te xt
Figure 9: SARA-N3 series power-on sequence from not-powered mode
☞ No voltage driven by an external application should be applied to the UART interface of the module
before applying the VCC supply, to avoid latch-up of circuits and allow a proper boot of the module.
☞ No voltage driven by an external application should be applied to any generic digital interface of
the module (GPIOs, I2C interface) before the switch-on of the generic digital interface supply source of the module (V_INT), to avoid latch-up of circuits and allow a proper boot of the module.
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1.6.2 Module power-off

The SARA-N2 series modules enter the non-powered mode by removing the VCC supply.
The switch-off routine of the SARA-N3 series modules can be properly triggered, with storage of current parameter settings in the module’s non-volatile memory and clean network detach, by:
• AT+CPWROFF command (see the SARA-N2 / SARA-N3 series AT commands manual [4]).
• Low level on the PWR_ON input pin, i.e. forcing the pin (normally high due to internal pull-up) to a
low level for a valid time period (see SARA-N3 series data sheet [2]).
An abrupt under-voltage shutdown occurs on the SARA-N3 series modules when the VCC supply drops below the extended operating range minimum limit (see the SARA-N3 series data sheet [2]), but in this case it is not possible to perform the storing of the current parameter settings in the module’s non-volatile memory as well as a clean network detach.
Figure 10 shows the switch-off sequence of the SARA-N3 series modules started by means of the
AT+CPWROFF command, allowing storage of current parameter settings in the module’s non-volatile memory and a clean network detach, with the following phases:
• When the +CPWROFF AT command is sent, the module starts the switch-off routine.
• Then, the module replies OK on the AT interface: the switch-off routine is in progress.
• At the end of the switch-off routine, the internal voltage regulator generating the V_INT supply rail
is turned off. Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a low level to PWR_ON), and enters not-powered mode if the VCC supply is removed.
VCC
PWR_ON
RESET_N
V_INT
System state
OFF
ON
AT+CPWROFF
sent to the module
OK
replied by the module
VCC can be
removed
Figure 10: SARA-N3 series modules switch-off sequence by means of AT+CPWROFF command
☞ It is highly recommended to monitor the V_INT pin to sense the end of the switch-off sequence. ☞ It is highly recommended to avoid an abrupt removal of the VCC supply during module normal
operations: the VCC supply can be removed only when the V_INT rail is switched off by the module.
☞ The duration of each phase in the SARA-N3 series modules’ switch-off routines can largely vary
depending on the application / network settings and the concurrent module activities.
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1.6.3 Module reset

SARA-N2 / N3 series modules can be properly reset (rebooted) by:
• AT command (see the SARA-N2 / SARA-N3 AT commands manual [4] for more details).
This command causes an “internal” or “software” reset of the module, which is an asynchronous reset
of the module baseband processor. The current parameter settings are saved in the non-volatile memory of the module and a proper network detach is performed.
An abrupt hardware reset occurs on SARA-N2 / N3 series modules when a low level is applied on the RESET_N input pin for a specific time period. In this case, storage of the current parameter settings in the module’s non-volatile memory and a proper network detach cannot be performed.
As described in Figure 11, the RESET_N input pin is equipped with an internal pull-up on SARA-N2 / N3 series modules, with sligthly different internal circuits.
Baseband processor
18
RESET_N
SARA-N2 series
VCC
Reset
Baseband processor
18
RESET_N
SARA-N3 series
Reset
Power management
Reset
1.1 V
Figure 11: SARA-N2 / N3 series RESET_N input equivalent circuit description
☞ It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on
the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset via AT command fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the SARA-N2 / N3 series AT commands manual [4].
☞ Provide a test point connected to the RESET_N pin for diagnostic purpose.

1.6.4 Voltage selection of interfaces (VSEL)

☞ The digital interfaces’ voltage selection functionality is not available in SARA-N2 series modules.
The digital I/O interfaces of the SARA-N3 series modules (the UARTs, I2C, and GPIOs pins) operate at the V_INT voltage, which can be set to 1.8 V or 2.8 V using the VSEL input:
• If the VSEL input pin is externally connected to GND, the digital I/O interfaces operate at 1.8 V
• If the VSEL input pin is left unconnected, the digital I/O interfaces operate at 2.8 V
The operating voltage cannot be changed dynamically: the VSEL input pin configuration has to be set before the boot of the SARA-N3 series modules and then it cannot be changed after switched on.
☞ If the VSEL input pin is left unconnected, the VCC voltage shall be inside normal operating range
to let the digital I/O interfaces work correctly (see SARA-N3 series data sheet [2] for more details).
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1.7 Antenna interface

1.7.1 Cellular antenna RF interface (ANT)

The ANT pin of SARA-N2 / N3 series modules represents the RF input/output for the cellular RF signals reception and transmission. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the external cellular antenna through a 50 transmission line for proper reception and transmission of cellular RF signals.
1.7.1.1 Cellular antenna RF interface requirements
Table 6 summarizes the requirements for the cellular antenna RF interface (ANT). See section 2.4.1
for suggestions to properly design an antenna circuit compliant to these requirements.
⚠ The cellular antenna circuit affects the RF compliance of the device integrating SARA-N2 / N3
series module with applicable required certification schemes.
Item
Requirements
Remarks
Impedance
50 nominal characteristic impedance
The nominal characteristic impedance of the antenna RF connection must match the ANT pin 50 impedance.
Frequency range
See the SARA-N2 series data sheet [1] and SARA-N3 series data sheet [2]
The required frequency range of the antenna depends on the operating bands supported by the cellular module.
Return loss
S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable
The return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the RF antenna connection matches the 50 impedance.
The impedance of the antenna RF termination must match as much as possible the 50 impedance of the ANT pin over the operating frequency range, reducing as much as possible the amount of reflected power.
Efficiency
> -1.5 dB ( > 70%) recommended > -3.0 dB ( > 50%) acceptable
The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits.
The efficiency needs to be enough high over the operating frequency range to comply with the Over-The-Air radiated performance requirements, as Total Radiated Power and Total Isotropic Sensitivity, specified by certification schemes
Maximum gain
See section 4.2 for maximum gain limits
The power gain of an antenna is the radiation efficiency multiplied by the directivity: the maximum gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source.
The maximum gain of the antenna connected to ANT pin must not exceed the values stated in section 4.2 to comply with regulatory agencies radiation exposure limits.
Input power
> 0.5 W peak
The antenna connected to ANT pin must support the maximum power transmitted by the modules.
Table 6: Summary of antenna RF interface (ANT) requirements
☞ For the additional specific requirements applicable to the integration of the SARA-N211 and the
SARA-N310 modules in devices intended for use in potentially explosive atmospheres, see the guidelines reported in section 2.12.
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1.7.2 Bluetooth antenna RF interface (ANT_BT)

☞ The Bluetooth functionality is not available in SARA-N2 series modules. ☞ The Bluetooth functionality is not supported by “00” product version of SARA-N3 series modules.
The ANT_BT pin can be left unconnected or it can also be connected to GND.
The ANT_BT pin has an impedance of 50 and provides the Bluetooth RF antenna interface of the SARA-N3 series modules.

1.7.3 Antenna detection interface (ANT_DET)

☞ Antenna detection interface is not supported in the “02” version of SARA-N2 series modules.
The ANT_DET pin is an Analog to Digital Converter (ADC) input used to sense the antenna presence evaluating the resistance from the ANT pin to GND by means of an external antenna detection circuit implemented on the application board. This optional functionality can be managed by dedicated AT command (for more details see the SARA-N2 / N3 series AT commands manual [4]).

1.8 SIM interface

SARA-N2 / N3 series modules provide a high-speed SIM/ME interface on the VSIM, SIM_IO, SIM_CLK and SIM_RST pins, which is available to connect an external SIM / UICC.
The SIM interface of the SARA-N2 series modules can operate at 1.8 V (VSIM domain), with activation and deactivation of the SIM interface implemented according to the ISO-IEC 7816-3 specifications.
The SIM interface of the SARA-N3 series modules can operate at 1.8 V and/or 3.0 V voltage (VSIM domain), with activation and deactivation of the SIM interface, and automatic 1.8 V / 3.0 V voltage switch according to the voltage class of the external SIM connected to the module implemented according to the ISO-IEC 7816-3 specifications.
The VSIM supply output of SARA-N2 / N3 series modules provides internal short circuit protection to limit start-up current and protect the external SIM / UICC to short circuits.
☞ If a 3.0 V SIM is used, the VCC voltage shall be inside normal operating range to let the SIM
interface work correctly (see SARA-N3 series data sheet [2] for more details).
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1.9 Serial interfaces

SARA-N2 / N3 series modules provide the following serial communication interfaces:
• Main primary UART interface (see 1.9.1): o In the VCC voltage domain (~3.6 V) on the SARA-N2 series modules, supporting:
▪ AT communication ▪ FW upgrades by means of the FOAT feature ▪ FW upgrades by means of the dedicated tool
o In the V_INT voltage domain (1.8 V or 2.8 V) on the SARA-N3 series modules, supporting:
▪ AT communication ▪ FW upgrades by means of the FOAT feature
• Auxiliary secondary UART interface (see 1.9.2):
o Not available on the SARA-N2 modules o In the V_INT voltage domain (1.8 V or 2.8 V) on the SARA-N3 series modules:
▪ Not supported by the “00” product versions
• Additional UART interface (see 1.9.3):
o In the V_INT voltage domain (1.8 V) on the SARA-N2 series modules, supporting:
▪ Diagnostic trace log
o In the V_INT voltage domain (1.8 V or 2.8 V) on the SARA-N3 series modules, supporting:
▪ FW upgrades by means of the u-blox EasyFlash tool ▪ Diagnostic trace log
• DDC I2C-bus compatible interface (see 1.9.4):
o In the V_INT voltage domain (1.8 V) on the SARA-N2 series modules:
▪ Not supported by the “02” product versions
o In the V_INT voltage domain (1.8 V or 2.8 V) on the SARA-N3 series modules:
▪ Not supported by the “00” product versions

1.9.1 Main primary UART interface

1.9.1.1 UART features
SARA-N2 modules include the RXD, TXD, CTS, RTS pins as main primary UART interface, supporting:
• AT communication
• FW upgrades by means of the FOAT feature
• FW upgrades by means of the dedicated tool
The main characteristics of the SARA-N2 modules primary UART interface are the following:
• Serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [7]
• It operates at VCC voltage level
o 0 V for low data bit or ON state o VCC, i.e. ~3.6 V, for high data bit or OFF state
• Data lines (RXD as module data output, TXD as module data input) are provided
• The CTS hardware flow control output is not supported by “02” product version: the CTS output
line can be configured as RING indicator, to signal an incoming message received by the module or an URC event, or as Network status indicator (for more details see section 1.11 and the SARA-N2 / SARA-N3 series AT commands manual [4], +URING, +UGPIOC AT commands),
• The RTS hardware flow control input is not supported by “02” product version
• Default baud rate: 9600 b/s (4800, 57600 and 115200 b/s baud rates are also supported)
• Default frame format: 8N1 (8 data bits, No parity, 1 stop bit)
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SARA-N3 series modules include the RXD, TXD, CTS, RTS, DTR, DSR, DCD, RI pins as main primary UART interface, supporting:
• AT communication
• FW upgrades by means of the FOAT feature
The main characteristics of the SARA-N3 series modules main primary UART interface are the following:
• Serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [7]
• It operates at V_INT level, with voltage value set as per external VSEL pin configuration
o 0 V for low data bit or ON state o V_INT, i.e. 1.8 V or 2.8 V, for high data bit or OFF state
• Data lines (RXD as module data output, TXD as module data input) are provided
• Hardware flow control lines (CTS as output, RTS as input) and RI output line are provided, and they
can be alternatively configured as described in section 1.11 (for more details see also the SARA-N2 / SARA-N3 series AT commands manual [4])
• The modem status and control lines (DTR as input, DSR as output, DCD as output) are not
supported by “00” product versions
• Hardware flow control disabled by default
• One-shot automatic baud rate detection enabled by default
• UART works in low power idle mode, supporting 4800, 9600, 19200, 38400, 57600 b/s baud rates
• 8N1 default frame format
The UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU recommendation [7]): SARA-N2 / N3 series modules are designed to operate as a cellular modem, which represents the Data Circuit-terminating Equipment (DCE) according to ITU-T V.24 recommendation [7]. The application processor connected to the module through the UART interface represents the Data Terminal Equipment (DTE).
The UART interface settings can be suitably configured by AT commands (for more details, see the SARA-N2 / SARA-N3 series AT commands manual [4]).
☞ The signal names of the SARA-N2 / N3 series modules’ UART interface conform to the ITU-T V.24
recommendation [7]: e.g. the TXD line represents the data transmitted by the DTE (application processor data line output) and received by the DCE (module data line input).
Figure 12 describes the 8N1 frame format.
D0 D1 D2 D3 D4 D5 D6 D7
Start of 1-Byte transfer
Start Bit (Always 0)
Possible Start of
next transfer
Stop Bit (Always 1)
t
bit
= 1/(Baudrate)
Normal Transfer, 8N1
Figure 12: Description of UART default frame format (8N1) with fixed baud rate
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1.9.1.2 UART signal behavior
At the module switch-on, before the UART interface initialization (as described in the power-on sequence reported in Figure 8 and Figure 9), each pin is first tri-stated and then is set to its related internal reset state. At the end of the boot sequence, the UART interface is initialized and the UART interface is enabled as AT commands interface.
The configuration and the behavior of the UART signals after the boot sequence are described below. See section 1.4 for definition and description of module operating modes referred to in this section.
RXD signal behavior
The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The greeting message is sent on the RXD line after the completion of the boot sequence to indicate the completion of the UART interface initialization. For more details regarding how to set greeting text, see the SARA-N2 / SARA-N3 series AT commands manual [4].
The module holds RXD in the OFF state until the module does not transmit some data.
TXD signal behavior
The module data input line (TXD) is assumed to be controlled by the external host once UART is initialized.
There is no internal pull-up / pull-down inside the SARA-N2 modules on the TXD input. Instead, the SARA-N3 series modules have an internal pull-up on the TXD input.
1.9.1.3 UART and deep sleep mode
To limit the current consumption, SARA-N2 series modules automatically enter deep-sleep mode whenever possible, that is if there is no data to transmit or receive. When in deep-sleep mode the UART interface is still completely functional and the SARA-N2 module can accept and respond to any AT command. All the other interfaces are disabled.
The application processor should go in standby (or lowest power consumption mode) as soon as the SARA-N2 module enters the deep-sleep mode and there is no more data to be transmitted.
At any time the DTE can request the SARA-N2 module to send data using the related commands (for more details, see the SARA-N2 / SARA-N3 AT commands manual [4] and the NB-IoT application development guide [5]); these commands automatically force the SARA-N2 module to exit the deep­sleep mode.
To limit the current consumption, SARA-N3 series modules automatically enter the low power idle mode whenever possible, that is, if there is no data to transmit or receive. In low power idle mode, the UART interface is still completely functional and the SARA-N3 module can accept and respond to any AT command.
SARA-N3 series modules automatically enter the deep-sleep mode if the Power Saving Mode defined in 3GPP release 13 is enabled by A dedicated AT command (for more details, see the SARA-N2 / SARA-N3 series AT commands manual [4]), entering the lowest possible power mode. The UART interface is not functional: a wake-up event, consisting in proper toggling of the PWR_ON line, is necessary to trigger the wake up routine of the SARA-N3 series modules that subsequently enter
back into the active mode as in case of expiration of the “Periodic Update Timer” as per the Power
Saving Mode defined in 3GPP release 13.
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1.9.2 Secondary auxiliary UART interface

☞ The secondary auxiliary UART interface is not available on SARA-N2 modules. ☞ The secondary auxiliary UART interface is not supported by SARA-N3 “00” product version.
SARA-N3 series modules include the RXD_AUX and TXD_AUX pins as secondary auxiliary UART interface.
The characteristics of the SARA-N3 modules’ secondary auxiliary UART interface are:
• Serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [7]
• It operates at V_INT level, with voltage value set as per external VSEL pin configuration
o 0 V for low data bit or ON state o V_INT, i.e. 1.8 V or 2.8 V, for high data bit or OFF state
• Data lines (RXD_AUX as module data output, TXD_AUX as module data input) are provided

1.9.3 Additional UART interface

SARA-N2 series modules include the GPIO1 pin as additional UART interface, supporting:
• Diagnostic trace log
The characteristics of the SARA-N2 modules’ additional UART interface are:
• Serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [7]
• It operates at V_INT level, with voltage value set as per external VSEL pin configuration
o 0 V for low data bit or ON state o V_INT, i.e. 1.8 V, for high data bit or OFF state
• Data line (GPIO1 as module data output) is provided
• Fixed baud rate: 921600 b/s
• Fixed frame format: 8N1 (8 data bits, no parity, 1 stop bit)
☞ Provide a test point connected to the GPIO1 pin for diagnostic purpose. ☞ The trace diagnostic log is temporarily stopped when the SARA-N2 module is in deep-sleep mode.
SARA-N3 series modules include the RXD_FT and TXD_FT pins as additional UART interface, supporting:
• Diagnostic trace log
• FW upgrades by means of the u-blox EasyFlash tool
The characteristics of the SARA-N3 modules’ additional UART interface are:
• Serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [7]
• It operates at V_INT level, with voltage value set as per external VSEL pin configuration
o 0 V for low data bit or ON state o V_INT, i.e. 1.8 V or 2.8 V, for high data bit or OFF state
• Data lines (RXD_FT as module data output, TXD_FT as module data input) are provided
☞ Provide test points to the RXD_FT and TXD_FT pins for diagnostic and FW update purposes. ☞ The trace diagnostic log is temporarily stopped when the SARA-N3 module is in deep-sleep mode.
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1.9.4 DDC (I2C) interface

☞ DDC (I2C) interface is not supported by SARA-N2 “02” product version. ☞ DDC (I2C) interface is not supported by SARA-N3 “00” product version.
SARA-N2 / N3 series modules include SDA and SCL pins as I2C bus compatible Display Data Channel (DDC) interface, operating at the V_INT voltage level.

1.10 ADC

☞ ADC interface is not available in the SARA-N2 series modules.
The SARA-N3 series modules include two Analog-to-Digital Converter input pins, ANT_DET and ADC1, configurable via dedicated AT command (for further details, see the SARA-N2 / SARA-N3 series AT commands manual [4]).

1.11 General Purpose Input/Output (GPIO)

SARA-N2 series modules provide the following pins:
• GPIO1 pin, working at the V_INT (1.8 V) voltage domain, supporting the Secondary UART data
output functionality (see section 1.9.3 and Table 7)
• GPIO2 pin, working at the V_INT (1.8 V) voltage domain, not supported by “02” product versions
• CTS pin, working at the VCC (3.6 V typical) voltage domain, supporting the Network status
indication and the RING indicator functionality (see section 1.9.1 and Table 7)
For more details about how the pins can be configured, see the SARA-N2 / SARA-N3 series AT commands manual [4], +UGPIOC, +URING AT commands.
☞ Provide a test point connected to the GPIO1 pin for diagnostic purpose.
Function
Description
Default GPIO
Configurable GPIOs
Network status indication
Network status: registered home network, registered roaming, data transmission, no service
--
CTS Ring indication
Indicates an incoming message received by the module or an URC event
--
CTS
Secondary UART
Secondary UART data output for diagnostic purpose, to capture diagnostic logs delivered by the module
GPIO1
GPIO1 Pin disabled
Tri-state with an internal active pull-down enabled
CTS
CTS
Table 7: GPIO custom functions configuration of SARA-N2 series modules
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SARA-N3 series modules include General Purpose Input/Output pins that can be configured via u-blox AT commands (for further details, see the AT commands manual [4], +UGPIOC, +URING AT commands).
The internal power domain for the GPIO pins is V_INT, with 1.8 V or 2.8 V voltage value set according to external VSEL pin configuration.
Table 8 summarizes the custom functions available on the GPIO pins of SARA-N3 series modules.
Function
Description
Default GPIO
Configurable GPIOs
Network status indication
Output to indicate the network status: registered home network, registered roaming, data transmission, no service
--
GPIO1, GPIO2, CTS
Module status indication
Output indicating module status: power-off, sleep or deep-sleep mode versus idle, active or connected mode
--
GPIO4
Last gasp
Input to trigger last gasp execution
--
GPIO3
SIM card detection
Input to sense external SIM card physical presence
GPIO59
GPIO59 HW flow control (RTS)
UART request to send input
RTS
RTS
HW flow control (CTS)
UART clear to send output
CTS
CTS
Ring indication
UART ring indicator output
RI
RI
General purpose input
Input to sense high or low digital level
--
GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, RI, RTS, CTS
General purpose output
Output to set high or low digital level
--
GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, RI, RTS, CTS
Pin disabled
Output tri-stated, with an internal active pull-down enabled
GPIO1, GPIO2, GPIO3, GPIO4, GPIO510
GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 RI, RTS, CTS
Table 8: GPIO custom functions configuration of SARA-N3 series modules

1.12 Reserved pins (RSVD)

SARA-N2 / N3 series modules have pins reserved for future use, marked as RSVD.
All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be externally connected to ground.
9
Not supported by SARA-N3 “00” product version.
10
On SARA-N3 “00” product version only.
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