u-blox SARA-G450 User Manual

UBX-18046432 - R09 C1-Public www.u-blox.com
SARA-G450
Quad-band GSM/GPRS module
System integration manual
Abstract
This document describes the features and the system integration of the SARA-G450 quad-band GSM/GPRS cellular modules. These modules are a complete and cost efficient solution offering voice and/or data communication in the compact SARA form factor.
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Document information

Title
SARA-G450
Subtitle
Quad-band GSM/GPRS module
Document type
System integration manual
Document number
UBX-18046432
Revision and date
R09
08-Mar-2021
Disclosure restriction
C1-Public
Product status
Corresponding content status
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development / Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production / End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Type number
Modem version
Application version
PCN reference
Product status
SARA-G450
SARA-G450-00C-00
09.02
A02.01
UBX-18067098
Obsolete
SARA-G450-00C-01
09.02
A03.17
UBX-20033037
Mass production
SARA-G450-01C-00
09.02
A04.23
UBX-20033037
End of life
SARA-G450-01C-01
09.02
A05.01
UBX-21006193
Mass production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com.
Copyright © u-blox AG.
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Contents

Document information ................................................................................................................................ 2
Contents .......................................................................................................................................................... 3
1 System description ............................................................................................................................... 6
1.1 Overview ........................................................................................................................................................ 6
1.2 Architecture ................................................................................................................................................. 7
1.3 Pin-out ........................................................................................................................................................... 9
1.4 Operating modes .......................................................................................................................................13
1.5 Supply interfaces ......................................................................................................................................15
1.5.1 Module supply input (VCC) .............................................................................................................15
1.5.2 RTC supply input/output (V_BCKP) ..............................................................................................21
1.5.3 Generic digital interfaces supply output (V_INT) .......................................................................22
1.6 System function interfaces ....................................................................................................................22
1.6.1 Module power-on (PWR_ON) ..........................................................................................................22
1.6.2 Module power-off ..............................................................................................................................24
1.6.3 Module reset ......................................................................................................................................26
1.6.4 Digital I/O interfaces voltage selection (VSEL)...........................................................................26
1.7 Antenna interface .....................................................................................................................................26
1.7.1 Antenna RF interface (ANT) ...........................................................................................................26
1.7.2 Antenna detection interface (ANT_DET).....................................................................................27
1.8 SIM interface ..............................................................................................................................................28
1.8.1 (U)SIM card interface .......................................................................................................................28
1.8.2 SIM card detection interface (SIM_DET) .....................................................................................28
1.9 Serial interfaces ........................................................................................................................................28
1.9.1 Primary main serial interface (UART) ...........................................................................................29
1.9.2 Secondary auxiliary serial interface (AUX UART) .......................................................................40
1.9.3 Additional serial interface for FW upgrade and tracing (FT UART) .......................................42
1.9.4 DDC (I2C) interface ...........................................................................................................................42
1.10 Audio interfaces ........................................................................................................................................44
1.10.1 Analog audio interface .....................................................................................................................44
1.11 General Purpose Input/Output (GPIO) ..................................................................................................45
1.12 Reserved pins (RSVD) ..............................................................................................................................45
1.13 System features ........................................................................................................................................46
1.13.1 Network indication ...........................................................................................................................46
1.13.2 Antenna detection ............................................................................................................................46
1.13.3 Jamming detection ..........................................................................................................................46
1.13.4 TCP/IP and UDP/IP ............................................................................................................................47
1.13.5 FTP .......................................................................................................................................................47
1.13.6 HTTP ....................................................................................................................................................47
1.13.7 SSL/TLS ..............................................................................................................................................47
1.13.8 Dual stack IPv4/IPv6 .........................................................................................................................48
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1.13.9 Smart temperature management ................................................................................................48
1.13.10 AssistNow clients and GNSS integration ..............................................................................51
1.13.11 Hybrid positioning and CellLocate® ........................................................................................51
1.13.12 Firmware upgrade Over AT (FOAT) .........................................................................................54
1.13.13 Last gasp ......................................................................................................................................54
1.13.14 Power saving ................................................................................................................................55
2 Design-in ................................................................................................................................................ 56
2.1 Overview ......................................................................................................................................................56
2.2 Supply interfaces ......................................................................................................................................56
2.2.1 Module supply (VCC) ........................................................................................................................56
2.2.2 RTC supply (V_BCKP) .......................................................................................................................70
2.2.3 Interface supply (V_INT) ..................................................................................................................71
2.3 System functions interfaces ..................................................................................................................72
2.3.1 Module power-on (PWR_ON) ..........................................................................................................72
2.3.2 Module hard power-off (PWR_OFF) ..............................................................................................73
2.3.3 Digital I/O interfaces voltage selection (VSEL)...........................................................................74
2.4 Antenna interface .....................................................................................................................................75
2.4.1 Antenna RF interface (ANT) ...........................................................................................................75
2.4.2 Antenna detection interface (ANT_DET).....................................................................................82
2.5 SIM interface ..............................................................................................................................................85
2.5.1 Guidelines for SIM circuit design ...................................................................................................85
2.5.2 Guidelines for SIM layout design ...................................................................................................90
2.6 Serial interfaces ........................................................................................................................................91
2.6.1 Primary main serial interface (UART) ...........................................................................................91
2.6.2 Secondary auxiliary serial interface (AUX UART) .......................................................................98
2.6.3 Additional serial interface for FW upgrade and Tracing (FT UART) ......................................99
2.6.4 DDC (I2C) interface ........................................................................................................................ 100
2.7 Audio interfaces ..................................................................................................................................... 107
2.7.1 Analog audio interface .................................................................................................................. 107
2.8 General Purpose Input/Output (GPIO) ............................................................................................... 112
2.8.1 Guidelines for GPIO circuit design .............................................................................................. 112
2.8.2 Guidelines for GPIO layout design .............................................................................................. 113
2.9 Reserved pins (RSVD) ........................................................................................................................... 113
2.10 Module placement ................................................................................................................................. 113
2.11 Module footprint and paste mask ...................................................................................................... 114
2.12 Schematic for SARA-G450 modules integration ............................................................................ 115
2.13 Design-in checklist ................................................................................................................................. 117
2.13.1 Schematic checklist ...................................................................................................................... 117
2.13.2 Layout checklist ............................................................................................................................. 118
2.13.3 Antenna checklist .......................................................................................................................... 118
3 Handling and soldering ................................................................................................................... 119
3.1 Packaging, shipping, storage and moisture preconditioning ....................................................... 119
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3.2 Handling ................................................................................................................................................... 119
3.3 Soldering .................................................................................................................................................. 120
3.3.1 Soldering paste .............................................................................................................................. 120
3.3.2 Reflow soldering ............................................................................................................................. 120
3.3.3 Optical inspection .......................................................................................................................... 121
3.3.4 Cleaning ........................................................................................................................................... 121
3.3.5 Repeated reflow soldering ........................................................................................................... 122
3.3.6 Wave soldering ............................................................................................................................... 122
3.3.7 Hand soldering ............................................................................................................................... 122
3.3.8 Rework ............................................................................................................................................. 122
3.3.9 Conformal coating ......................................................................................................................... 122
3.3.10 Casting ............................................................................................................................................. 123
3.3.11 Grounding metal covers ............................................................................................................... 123
3.3.12 Use of ultrasonic processes ........................................................................................................ 123
4 Approvals ............................................................................................................................................. 124
4.1 Product certification approval overview ............................................................................................ 124
4.2 European conformance ......................................................................................................................... 125
4.3 Chinese compulsory certification ....................................................................................................... 125
5 Product testing ................................................................................................................................. 126
5.1 u-blox in-series production test .......................................................................................................... 126
5.2 Test parameters for OEM manufacturer .......................................................................................... 126
5.2.1 “Go/No go” tests for integrated devices ................................................................................... 127
5.2.2 Functional tests providing RF operation .................................................................................. 127
Appendix ..................................................................................................................................................... 128
A Migration between SARA modules ............................................................................................. 128
B Glossary ............................................................................................................................................... 128
Related documentation ......................................................................................................................... 131
Revision history ........................................................................................................................................ 131
Contact ........................................................................................................................................................ 132
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1 System description

1.1 Overview

SARA-G450 modules are versatile 2.5G GSM/GPRS cellular modules in the miniature SARA 96-pin LGA (Land Grid Array) form factor (26.0 x 16.0 mm).
Featuring low power consumption, the SARA-G450 modules combine baseband, RF transceiver, power management unit, and power amplifier in a single solution allowing an easy integration into compact designs and a seamless drop-in migration between other SARA series modules and to and from the other u-blox cellular modules families.
SARA-G450 modules provide a fully qualified and certified solution, reducing cost and enabling short time to market. These modules are ideally suited for M2M applications such as: Automatic Meter Reading (AMR), Remote Monitoring Automation and Control (RMAC), surveillance and security, road pricing, asset tracking, fleet management, anti-theft systems and Point of Sales (PoS) terminals.
SARA-G450 modules are full-feature GSM/GPRS quad-band cellular modules with a comprehensive feature set including an extensive set of internet protocols. The modules are also designed to provide fully integrated access to u-blox GNSS positioning chips and modules, with embedded A-GPS (AssistNow Online and AssistNow Offline) functionality. Any host processor connected to the cellular module through a single serial port can control both the cellular module and the positioning chip / module.
The SARA-G450 modules’ compact form factor and LGA pads allow fully automated assembly with standard pick & place and reflow soldering equipment for cost-efficient, high-volume production.
Table 1 describes a summary of interfaces and features provided by SARA-G450 modules.
Model
Data Rate
Bands
Positioning
Interfaces
Audio
Features
Grade
GPRS
multi-slot class 12
GSM/GPRS 4
-band
Integrated GNSS receiver GNSS via modem AssistNow Software CellLocate® UART
SPI
USB 2.0 GPIO
DDC (I
2C)
Analog audio Digital audio Network indication Antenna supervisor Jamming detection Embedded TCP, UDP
stack
Embedded FTP, HTTP Embedded SSL, TLS Dual stack IPv4 / IPv6 FW update via serial interface Standard Professional Automotive
SARA-G450
● □ □ □
● □ □ ● ● □ ● ● ● ● ● ●
● = supported by all FW versions
= supported by product version “01” onwards
Table 1: SARA-G450 modules characteristics summary
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Table 2 reports a summary of cellular radio access technologies characteristics of SARA-G450
modules.
Item
SARA-G450
Mobile Station Class
B1
GSM/GPRS protocol stack
3GPP Release 99
GSM/GPRS bands
GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz
GSM/GPRS Power Class
Class 4 (33 dBm) for 850/900 bands
Class 1 (30 dBm) for 1800/1900 bands
Packet Switched Data rate
GPRS multi-slot class 122 Coding scheme CS1-CS4 Up to 85.6 kbit/s DL3 Up to 85.6 kbit/s UL3
Table 2: SARA-G450 modules GSM/GPRS characteristics summary

1.2 Architecture

Figure 1 summarizes the architecture of SARA-G450 modules, illustrating the internal blocks of the
modules, consisting of the RF, baseband and power management main sections, and the available interfaces.
V_BCKP (RTC)
V_INT (I/O)
26 MHz
32.768 kHz
RF
transceiver
Power
Management
Unit
Baseband
ANT
Switch
PA
VCC (supply)
Memory
Power-off
Power-on
SIM card
SIM card detection
UART (primary main)
UART (secondary auxiliary)
DDC (I2C)
Analog audio (MIC & SPK)
GPIOs
Antenna detection
VSEL (I/O voltage selection)
UART (flashing & tracing)
32.768 kHz over GPIO
Figure 1: SARA-G450 modules block diagram
1
Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. For example, if an incoming call occurs during data transmission, the data connection is suspended to allow the voice communication. Once the voice call has terminated, the data service is resumed.
2
GPRS multi-slot class 12 implies a maximum of 4 slots in Down-Link (reception) and 4 slots in Up-Link (transmission) with 5 slots in total. The SARA-G450 modules can be configured as GPRS multi-slot class 10 by means of AT command.
3
The maximum bit rate of the module depends on the current network settings.
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The RF section is composed of the following main elements:
2G RF transceiver performing modulation, up-conversion of the baseband I/Q signals,
down-conversion and demodulation of the RF received signals
2G power amplifier, which amplifies the signals modulated by the RF transceiver
RF switch, which connects the antenna input/output pin (ANT) of the module to the suitable
RX/TX path
26 MHz crystal, connected to the digital controlled crystal oscillator to perform the clock reference
in active-mode and connected-mode
The Baseband and Power Management section is composed of the following main elements:
Baseband processor
Memory system
Voltage regulators to derive all the system supply voltages from the module supply VCC
Circuit for the RTC clock reference in low power idle-mode
SARA-G450-00C modules, i.e. the “00” product version of the SARA-G450 modules, do not
support the following interfaces, which should be left unconnected and should not be driven by external devices:
o Secondary auxiliary UART interface o DDC (I2C) interface o Analog audio interface
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1.3 Pin-out

Table 3 lists the pin-out of the SARA-G450 modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply input
All VCC pins must be connected to external supply. VCC supply circuit affects the RF performance and
compliance of the device integrating the module with applicable required certification schemes.
See section 1.5.1 for description and requirements. See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14, 20, 22, 30, 32, 43, 50, 54, 55, 57-61, 63-96
N/A
Ground
GND pins are internally connected to each other. External ground connection affects the RF and thermal
performance of the device.
V_BCKP
2
I/O
Real Time Clock supply input/output
V_BCKP = 3.1 V (typical). V_BCKP is generated by internal low power linear
regulator when a valid VCC supply is present. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.
V_INT
4
O
Generic Digital Interfaces supply output
V_INT supply output, rail of the Digital I/O Interfaces, generated by internal linear regulator when the module is switched on.
V_INT = 1.8 V (typical), if VSEL is connected to GND. V_INT = 3 V (typical), if VSEL is unconnected.
Test-Point recommended for diagnostic purpose. See section 1.5.3 for functional description. See section 2.2.3 for external circuit design-in.
System
PWR_ON
15 I Power-on input
Internal 28 k active pull-up to 2.5 V internal supply. Test-Point recommended for diagnostic purpose. See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
PWR_OFF
18 I Power-off input
Internally connected to 1.5 V internal supply. Test-Point recommended for diagnostic purpose. See sections 1.6.2, 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
VSEL
21 I Voltage selection
Input to select the operating voltage of the digital I/O interfaces of the module (the UART interfaces, I2C interface and GPIO pins). See section 1.6.4 for functional description. See section 2.3.3 for external circuit design-in.
Antenna
ANT
56
I/O
RF input/output for antenna
50  nominal characteristic impedance. Antenna circuit affects the RF performance and compliance of the device integrating the module with
applicable required certification schemes. See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT_DET
62
I
Input for antenna detection
ADC input for antenna detection function. See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
SIM
VSIM
41 O SIM supply output
VSIM = 1.8 V (typical) or 2.8 V (typical) automatically generated according to the connected SIM type.
See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_CLK
38 O SIM clock
3.25 MHz clock output for 1.8 V / 3 V SIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_RST
40 O SIM reset
Reset output for 1.8 V / 3 V SIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.
SIM_DET
42 I SIM detection
SIM presence detection function. See section 1.8.2 for functional description. See section 2.5 for external circuit design-in.
UART
RXD
13 O UART data output
Circuit 104 (RxD) in ITU-T V.24, for AT command, data, Mux, and FOAT.
It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
TXD
12 I UART data input
Circuit 103 (TxD) in ITU-T V.24, for AT command, data, Mux, and FOAT. It operates at V_INT voltage level.
See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send output
Circuit 106 (CTS) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
RTS
10
I
UART request to send input
Circuit 105 (RTS) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
DSR 6 O
UART data set ready output
Circuit 107 (DSR) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
DTR 9 I
UART data terminal ready input
Circuit 108/2 (DTR) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
RI 7 O
UART ring indicator output
Circuit 125 (RI) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.
DCD 8 O
UART data carrier detect output
Circuit 109 (DCD) in ITU-T V.24. It operates at V_INT voltage level. See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
Auxiliary UART
RXD_AUX
19
O
AUX UART data output
Circuit 104 (RxD) in ITU-T V.24, for AT command, data and GNSS tunneling.
It operates at V_INT voltage level. Test-Point recommended for diagnostic purpose. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.
TXD_AUX
17
I
AUX UART data input
Circuit 103 (TxD) in ITU-T V.24, for AT command, data and GNSS tunneling.
It operates at V_INT voltage level. Test-Point recommended for diagnostic purpose. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.
Additional UART for FW upgrade and Trace
RXD_FT
28
O
FT UART data output
Circuit 104 (RxD) in ITU-T V.24, for FW upgrade via dedicated tool, and diagnostics.
It operates at 3 V voltage level during FW upgrade, otherwise at V_INT voltage level.
Test-Point recommended for diagnostic purpose. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.
TXD_FT
29
I
FT UART data input
Circuit 103 (TxD) in ITU-T V.24, for FW upgrade via dedicated tool, and diagnostics. It operates at 3 V voltage level during FW upgrade, otherwise at V_INT voltage level. Test-Point recommended for diagnostic purpose. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.
DDC
SCL
27 O I2C bus clock line
Fixed open drain, for communication with u-blox positioning modules / chips. It operates at V_INT voltage level. External pull-up required. See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA
26
I/O
I2C bus data line
Fixed open drain, for communication with u-blox positioning modules / chips.
It operates at V_INT voltage level. External pull-up required. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.
Analog Audio
MIC_BIAS
46
O
Microphone supply output
Supply output (1.7 typ.) for the external microphone. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.
MIC_GND
47
I
Microphone analog reference
Local ground for the external microphone (reference for the differential analog audio input). See section 1.10.1 for functional description.
See section 2.7.1 for external circuit design-in.
MIC_N
48
I
Differential analog audio input (negative)
Differential analog audio signal input (negative). No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.
MIC_P
49
I
Differential analog audio input (positive)
Differential analog audio signal input (positive). No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.
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Function
Pin Name
Pin No
I/O
Description
Remarks
SPK_P
44
O
Differential analog audio output (positive)
Differential analog audio signal output (positive) shared for all the analog downlink path modes: earpiece, headset, loudspeaker mode.
See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in.
SPK_N
45
O
Differential analog audio output (negative)
Differential analog audio signal output (negative) shared for all the analog downlink path modes: earpiece, headset, loudspeaker mode. See section 1.10.1 for functional description.
See section 2.7.1 for external circuit design-in.
Digital Audio
I2S_CLK
36 O I2S clock
Not supported.
I2S_RXD
37 I I2S receive data
Not supported.
I2S_TXD
35 O I2S transmit data
Not supported.
I2S_WA
34 O I2S word alignment
Not supported.
GPIO
GPIO1
16
I/O
GPIO
It operates at V_INT voltage level. See sections 1.11 for functional description. See sections 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
It operates at V_INT voltage level. See sections 1.11 for functional description. See sections 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
It operates at V_INT voltage level. See sections 1.11 for functional description. See sections 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
It operates at V_INT voltage level. See sections 1.11 for functional description. See sections 2.8 for external circuit design-in.
Reserved
RSVD
33
N/A
RESERVED pin
This pin can be connected to GND or left unconnected. See sections 1.12 and 2.9.
RSVD
31
N/A
RESERVED pin
Internally not connected. Leave unconnected. See sections 1.12 and 2.9.
Table 3: SARA-G450 modules pin definition, grouped by function
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1.4 Operating modes

SARA-G450 modules have several operating modes. The operating modes defined in Table 4 and described in detail in Table 5 provide general guidelines for operation.
Figure 2 describes the transition between the different operating modes.
General Status
Operating Mode
Definition
Power-down
Not-powered mode
VCC supply not present or below operating range: module is switched off.
Power-off mode
VCC supply within operating range and module is switched off.
Normal operation
Idle mode
Module processor core runs with internal 32 kHz reference; lowest current consumption.
Active mode
Module processor core runs with internal 26 MHz reference.
Connected mode
Module processor core runs with internal 26 MHz reference; voice call, data transmission/reception or signaling activity with the network enabled.
Table 4: Module operating modes definition
Mode
Description
Transition between operating modes
Not-Powered
VCC supply not present or below operating
range. Module is switched off. Application interfaces are not accessible. Internal RTC operates if a valid voltage is applied to V_BCKP.
When VCC supply is removed, the module enters not-powered mode.
When in not-powered mode, the module cannot be switched on by PWR_ON or RTC alarm.
When in not-powered mode, the module switches to power-off mode if valid VCC supply is applied (see section 1.5.1).
Power-Off
VCC supply within operating range.
Module is switched off. Application interfaces are not accessible. Internal RTC operates as V_BCKP is internally generated.
When valid VCC supply is applied, the module switches from not-powered mode to power-off mode (see section 1.5.1).
When the module is switched off by an appropriate power-off event or by a PWR_OFF abrupt shutdown, the module enters power-off mode (see section 1.6.2). When in power-off mode, the module can be switched on by PWR_ON or RTC alarm: the module switches from power-off mode to active mode (see section 1.6.1). When valid VCC supply is removed, the module switches from power-off mode to not-powered mode.
Idle
The module is not ready to communicate with an external device by means of the application interfaces as configured to reduce consumption.
The module automatically enters idle mode whenever possible if power saving is enabled by the +UPSV AT command (see the u-blox AT commands manual [2]), reducing power consumption (see section 1.5.1.3). The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active mode according to power saving and HW flow control settings (see 1.9.1.3, 1.9.1.4). Power saving configuration is not enabled by default: it can be enabled by +UPSV (see u-blox AT commands manual [2]).
The module automatically switches from active mode to idle mode whenever possible if power saving is enabled (see sections 1.5.1.3, 1.9.1.4 and the u-blox AT commands manual [2], +UPSV AT command).
The module wakes up from idle to active mode in the following events:
Automatic periodic monitoring of the paging channel for the
paging block reception according to network conditions (see 1.5.1.3, 1.9.1.4)
Data received on the UART interface, according to HW flow
control (AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)
RTS input line set to the ON state by the DTE, if HW flow
control is disabled by AT&K0 and AT+UPSV=2 is set (see 1.9.1.4)
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Mode
Description
Transition between operating modes
Active
The module is ready to communicate with an external device by means of the application interfaces.
When the module is switched on by an appropriate power-on event (see 1.6.1), the module enters active mode from power-off mode.
If power saving configuration is enabled by the +UPSV AT command, the module automatically switches from active to idle mode whenever possible and the module wakes up from idle to active mode in the events listed above (see idle to active transition description). When a voice call or a data transmission is initiated, the module enters connected mode from active mode. When a voice call or a data transmission is terminated, the module returns to active mode.
Connected
A voice call or a data transmission is in progress.
The module is ready to communicate with an external device by means of the application interfaces.
When a voice call or a data transmission is initiated, the module enters connected mode from active mode.
When a voice call or a data transmission is terminated, the module returns to active mode.
Table 5: Module operating modes description
Apply VCC
If power saving is enabled and there is no activity for a defined time interval
Any wake-up event described in the module operating modes summary
Incoming/outgoing call or other dedicated device network communication
No RF Tx/Rx in progress, call terminated, communication dropped
Remove VCC
Switch ON:
PWR_ON
RTC alarm
Not
powered
Power off
ActiveConnected Idle
Switch OFF:
AT+CPWROFF
PWR_OFF
Figure 2: Operating modes transitions
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1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input.
The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators, including the V_BCKP Real Time Clock supply, V_INT digital interfaces supply, and VSIM SIM card supply.
During operation, the current drawn by the SARA-G450 modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in connected mode (as described in section 1.5.1.2) to the low current consumption during low power idle mode with power saving enabled (as described in section 1.5.1.3).
SARA-G450 modules provide separate supply inputs over the three VCC pins:
VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding
most of the total current drawn of the module when RF transmission is enabled during voice call or data transmission
VCC pin #51 represents the supply input for the internal baseband Power Management Unit and
the internal transceiver, demanding a minor part of the total current drawn of the module when RF transmission is enabled during voice call or data transmission
Figure 3 provides a simplified block diagram of SARA-G450 modules internal VCC supply routing.
53
VCC
52
VCC
51
VCC
SARA-G450
Power
Management
Unit
Memory
Baseband
processor
Transceiver
RF PMU
2G PA
Figure 3: SARA-G450 module VCC supply simplified block diagram
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1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the
suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6.
VCC supply circuit design may affect the RF compliance of the device integrating SARA-G450
modules with applicable required certification schemes as well as antenna circuit design. Compliance is not guaranteed if the VCC requirements summarized in the Table 6 are not fulfilled.
Item
Requirement
Remark
VCC nominal
voltage
Within VCC normal operating range:
3.4 V min / 4.2 V max
The VCC voltage value must be within the normal operating range limits to switch on the module. RF performances may be affected when VCC voltage is outside the normal operating range limits.
VCC voltage during normal operation
Within VCC extended operating range:
3.1 V min / 4.5 V max
The module may switch off when VCC voltage drops below the extended operating range minimum limit.
Operation above extended operating range limit is not recommended and may affect device reliability.
VCC average current
Support with adequate margin the highest averaged VCC current consumption value in connected mode conditions specified in the SARA-G450 data sheet [1].
The highest averaged VCC current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and VCC voltage. See section 1.5.1.2 for 2G connected mode current profiles.
VCC peak current
Support with margin the highest peak VCC current consumption value specified in the SARA-G450 data sheet [1].
The specified highest peak of VCC current consumption occurs during GSM single transmit slot in 850/900 MHz connected mode, in the event of a mismatched antenna. See section
1.5.1.2 for 2G connected mode current profiles.
VCC voltage drop during 2G Tx slots
Lower than 400 mV
VCC voltage drop directly affects the RF compliance with applicable certification schemes.
Figure 5 describes VCC voltage drop during Tx
slots.
VCC voltage ripple during 2G Tx
Noise in the supply must be minimized
VCC voltage ripple directly affects the RF compliance with applicable certification schemes.
Figure 5 describes VCC voltage ripple during Tx
slots.
VCC under/over-shoot at start/end of Tx slots
Absent or at least minimized
VCC under/over-shoot directly affects the RF compliance with applicable certification schemes.
Figure 5 describes VCC voltage under/over-shoot.
Table 6: Summary of VCC supply requirements
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1.5.1.2 VCC current consumption in 2G connected mode
When a GSM transmission is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption.
If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands, at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the current consumption can reach a high peak / pulse (see the SARA-G450 data sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).
If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to the 3GPP transmitter output power specifications.
During a GSM transmission, current consumption is not so significantly high in receiving or in monitor bursts and it is low in the bursts unused to transmit / receive.
Figure 4 shows an example of the module current consumption profile versus time in GSM talk mode.
Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-120 mA
1900 mA
Peak current depends
on TX power and
actual antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
2.0
60-120 mA
10 -40 mA
Figure 4: VCC current consumption profile versus time during a GSM transmission (1 TX slot, 1 RX slot)
Figure 5 illustrates the VCC voltage profile versus time during a GSM transmission, according to the
related VCC current consumption profile described in Figure 4.
Time
undershoot
overshoot
ripple
drop
Voltage
3.8 V (typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
Figure 5: Description of the VCC voltage profile versus time during a GSM transmission (1 TX slot, 1 RX slot)
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When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as can be in the case of a GSM transmission.
If the module transmits in GPRS multi-slot class 10 or 12, in 850 or 900 MHz bands, at maximum RF power level, the consumption can reach a quite high peak but lower than the one achievable in 2G single-slot mode. This happens for 1.154 ms (width of the 2 Tx slots/bursts) in the case of multi-slot class 10 or for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/4 or 1/2 duty cycle, according to GSM TDMA.
If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower than in the 850 or 900 MHz band because of the 3GPP Tx power specifications.
Figure 6 illustrates the current consumption profiles in GPRS connected mode, in the 850 or 900 MHz
bands, with 2 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 10.
Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
TX
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
TX
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
60-120mA
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
60-120mA
10 -40mA
200mA
Peak current depends
on TX power and
actual antenna load
160 0 mA
Figure 6: VCC current consumption profile versus time during a GPRS multi-slot class 10 connection (2 TX slots, 1 RX slot)
Figure 7 illustrates the current consumption profiles in GPRS connected mode, in the 850 or 900 MHz
bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.
Time [ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
60-120mA
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
60-120mA
10 -40mA
200mA
Peak current depends
on TX power and
actual antenna load
1600 mA
Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)
For detailed current consumption values, see the SARA-G450 data sheet [1].
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1.5.1.3 VCC current consumption in cyclic idle/active mode (+UPSV enabled)
The power saving configuration is disabled by default, but it can be enabled using the appropriate AT command (see the u-blox AT commands manual [2], +UPSV AT command). When power saving is enabled, the module automatically enters low power idle mode whenever possible, reducing current consumption.
During idle mode, the module processor runs with an internal 32 kHz reference clock.
When the power saving configuration is enabled and the module is registered or attached to a network, the module automatically enters the low power idle mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance with the 2G system requirements, even if connected mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active mode to enable paging block reception. In between, the module switches to low power idle mode. This is known as discontinuous reception (DRX).
The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active mode.
The time period between two paging block receptions is defined by the network. This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell.
For 2G radio access technology, the paging period varies from 470.8 ms (DRX = 2, length of 2 x 51 2G frames = 2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms).
Figure 8 roughly describes the current consumption profile of SARA-G450 modules, when power
saving is enabled. The module is registered with the network, automatically enters the very low power idle mode, and periodically wakes up to active mode to monitor the paging channel for paging block reception.
20-30 ms
IDLE MODE ACTIVE MODE IDLE MODE
Active Mode
Enabled
Idle Mode
Enabled
0.44-2.09 s
IDLE MODE
20-30 ms
ACTIVE MODE
Time [s]
Current [mA]
100
50
0
Time [ms]
Current [mA]
100
50
0
RX
Enabled
DSP
Enabled
Figure 8: VCC current consumption profile versus time of the SARA-G450 modules, when registered with the network, with power saving enabled: the very low power idle mode is reached and periodical wake up to active mode are performed to monitor the paging channel
For the detailed modules VCC current consumption values in low-power idle mode or in cyclic idle/active mode (module registered with 2G network with power saving enabled), see the SARA-G450 data sheet [1].
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1.5.1.4 VCC current consumption in fixed active mode (+UPSV disabled)
Power saving configuration is disabled by default, or it can be disabled using the appropriate AT command (see the u-blox AT commands manual [2], +UPSV AT command). When power saving is disabled, the module does not automatically enter idle mode whenever possible: the module remains in active mode.
The module processor core is activated during active mode, and the 26 MHz reference clock frequency is used.
Figure 9 roughly describes the current consumption profile of the SARA-G450 modules, when power
saving is disabled: the module is registered with the network, active mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception.
ACTIVE MODE
0.47-2.12 s
Paging period
Time [s]
Current [mA]
100
50
0
Time [ms]
Current [mA]
100
50
0
RX
Enabled
DSP
Enabled
Figure 9: VCC current consumption profile versus time of the SARA-G450 modules, when registered with the network, with power saving disabled: the active mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel
For the detailed modules VCC current consumption values in fixed active mode (module registered with 2G network with power saving disabled), see the SARA-G450 data sheet [1].
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1.5.2 RTC supply input/output (V_BCKP)

The V_BCKP pin of SARA-G450 modules connects the supply for the Real Time Clock (RTC) and power-on internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 10. The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range, with the module switched off or switched on.
Baseband
processor
51
VCC
52
VCC
53
VCC
2
V_BCKP
Linear
LDO
RTC
Power
Management
Unit
SARA-G450
32 kHz
Figure 10: RTC supply input/output (V_BCKP) and 32 kHz timing reference clock simplified block diagram
The RTC provides the module time reference (date and time) that is used to set the wake-up interval during the idle mode periods between network paging, and is able to make available the programmable alarm functions.
The RTC functions are available also in not-powered mode when the V_BCKP is within its valid range (specified in the “Input characteristics of Supply/Power pins” table in the SARA-G450 data sheet [1]). See the u-blox AT commands manual [2] for more details.
The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module.
The RTC oscillator does not necessarily stop operation (i.e. the RTC counting does not necessarily stop) when the V_BCKP voltage value drops below the specified operating range minimum limit, but the RTC value read after a system restart may not be reliable.
Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).
If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within a few milliseconds, the voltage on V_BCKP will go below the valid range. This has no impact on cellular connectivity, as none of the module functionalities rely on date and time setting.
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1.5.3 Generic digital interfaces supply output (V_INT)

The same 1.8 V / 3 V voltage domain used internally to supply the generic digital interfaces (GDI) of SARA-G450 modules is also available on the V_INT supply output pin, as described in Figure 11.
Baseband
processor
51
VCC
52
VCC
53
VCC
4
V_INT
LDO
Digital I/O
Interfaces
Power
Management
Unit
SARA-G450
Figure 11: SARA-G450 interfaces supply output (V_INT) simplified block diagram
The internal regulator that generates the V_INT supply is a low drop out (LDO) converter that is directly supplied from the VCC main supply input of the module.
The V_INT voltage regulator output is disabled (i.e. 0 V) when the module is switched off. When the module is switched on, V_INT can be configured in the two following ways:
V_INT = 1.8 V, if VSEL pin is connected to GND
V_INT = 3 V, if VSEL pin is left unconnected

1.6 System function interfaces

1.6.1 Module power-on (PWR_ON)

1.6.1.1 Switch-on events
When the SARA-G450 modules are in the not-powered mode (i.e. switched off with the VCC module supply not applied), valid VCC supply must be applied first, switching to power-off mode.
When the SARA-G450 modules are in power-off mode (i.e. switched off with valid VCC supply applied), then they can be switched on by:
Low level for a valid time period on PWR_ON pin, which is normally set high by an internal pull-up
The PWR_ON input voltage thresholds are different from the other generic digital interfaces of the module: see the SARA-G450 data sheet [1] for detailed electrical characteristics.
The SARA-G450 modules can be also switched on from power-off mode by:
RTC alarm pre-programmed by the +CALA AT command (see u-blox AT commands manual [2]).
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1.6.1.2 Switch-on sequence from power-off mode
Figure 12 shows the power-on sequence from the power-off mode, describing the following phases:
The external supply is still applied to the VCC inputs. The V_BCKP output is internally enabled
since an appropriate VCC is present. The PWR_ON and PWR_OFF pins are set to high logic level due to internal pull-ups.
The PWR_ON input pin is set low for a valid time period, representing the start-up event.
All the generic digital pins of the module are tri-stated until the switch-on of their supply source
(V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a clean boot of the module.
The V_INT generic digital interfaces supply output is enabled by the integrated Power
Management Unit.
The Internal Reset signal is held low by the integrated Power Management Unit: the baseband
processor core and all the digital pins of the modules are held in reset state.
When the Internal Reset signal is released by the integrated Power Management Unit, any digital
pin is set in a correct sequence from the reset state to the default operational state.
The module is fully ready to operate after all the interfaces are configured.
VCC
V_BCKP
PWR_ON
PWR_OFF
V_INT
Internal reset
System state
Digital pins state
Internal reset → Operational
Tristate / Floating
OFF
ON
Internal reset
Operational
Start of interface
configuration
Module interfaces
are configured
Start-up
event
Figure 12: SARA-G450 modules power-on sequence from power-off mode
1.6.1.3 General considerations for the switch-on procedure
A greeting text can be activated by means of the +CSGT AT command (see the u-blox AT commands manual [2]) to notify the external application that the module is ready to operate (i.e. ready to reply to AT commands) and that the first AT command can be sent to the module. In this case, the UART autobauding must be disabled to let the module send the greeting text: the UART must be configured at a fixed baud-rate (the baud-rate of the application processor) instead of the default autobauding, otherwise the module does not know the baud-rate to be used for sending the greeting text (or any other URC) at the end of the internal boot sequence.
As an alternative starting procedure, after the interfaces’ configuration phase, the application can
start sending AT commands and wait for the response with a 30 s timeout; iterate it 4 times without resetting or removing the VCC supply of the module, and then run the application.
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The Internal reset signal is not available on a module pin, but the host application can monitor the
V_INT pin to sense the start of the module power-on sequence.
Before the switch-on of the generic digital interface supply source (V_INT) of the module, no
voltage driven by an external application should be applied to any generic digital interface of the module.
Before the modules are fully ready to operate, the host application processor should not send any
AT command over the AT communication module interfaces. After V_INT rises up, wait at least 5 s before issuing AT commands; during this time, modules might be responsive but the NVM might not be ready yet for set commands.
The duration of SARA-G450 modules switch-on routine can vary depending on the
application / network settings and the concurrent module activities.

1.6.2 Module power-off

1.6.2.1 Switch-off events
The SARA-G450 modules can be properly switched off by:
AT+CPWROFF command (more details in the u-blox AT commands manual [2])
The current parameter settings are saved in the module’s non-volatile memory and a clean network detach is performed: this is the correct way to switch off the modules.
An abrupt hardware shutdown occurs on SARA-G450 modules when a low level is applied to PWR_OFF input. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a clean network detach is not performed.
It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low
level on PWR_OFF input pin during module normal operation: the PWR_OFF line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT commands manual [2].
An abrupt under-voltage shutdown occurs on SARA-G450 modules when the VCC module supply is removed. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a clean network detach cannot be performed.
It is highly recommended to avoid an abrupt removal of VCC supply during module normal
operation: the power-off procedure must be properly started by the application, by using the +CPWROFF AT command, waiting the command response for an appropriate time period (see the u-blox AT commands manual [2]), and then an appropriate VCC supply must be held at least until the end of the module’s internal power-off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module.
An over-temperature or an under-temperature shutdown occurs on SARA-G450 modules when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details, see section 1.13.9 and the u-blox AT commands manual [2], +USTS AT command.
The smart temperature supervisor feature is not supported by the “00” product version.
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1.6.2.2 Switch-off sequence by AT+CPWROFF
Figure 13 describes the SARA-G450 modules power-off sequence, properly started sending the
AT+CPWROFF command, allowing storage of the current parameter settings in the module’s non-volatile memory and a clean network detach, with the following phases:
When the +CPWROFF AT command is sent, the module starts the switch-off routine.
The module replies OK on the AT interface: the switch-off routine is in progress.
At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC supply (V_BCKP).
Then, the module remains in power-off mode as long as a switch-on event does not occur
(e.g. applying an appropriate low level to the PWR_ON input), and enters not-powered mode if the supply is removed from the VCC pins.
VCC
V_BCKP
PWR_ON
PWR_OFF
V_INT
Internal reset
System state
Digital pins state Operational
OFF
Tristate / Floating
ON
Operational →
Tristate
AT+CPWROFF
sent to the module
0 s
~2.5 s
~5 s
OK
replied by the module
VCC
can be removed
Figure 13: SARA-G450 modules power-off sequence description
The Internal reset signal is not available on a module pin, but the application can monitor the V_INT
pin to sense the end of the SARA-G450 modules power-off sequence.
The VCC supply can be removed only after the end of the module internal switch-off routine. After
the V_INT voltage level has gone low, wait at least 3 s before removing VCC.
The duration of each phase in the SARA-G450 modules switch-off routines can largely vary
depending on the application / network settings and the concurrent module activities.
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1.6.3 Module reset

SARA-G450 modules can be properly reset (rebooted) by:
AT+CFUN command (see the u-blox AT commands manual [2] for more details).
This command causes an “internal” or “software” reset of the module, which is an asynchronous reset
of the module baseband processor. The current parameter settings are saved in the module’s non-volatile memory and a clean network detach is performed: this is the correct way to reset the modules.
An abrupt hardware reset occurs on SARA-G450 modules when a low level is applied on the PWR_OFF input pin and then a low level is applied on the PWR_ON input pin for specific time periods; in this way the reset is performed with an abrupt shutdown and then switching on again the module. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a clean network detach is not performed.
It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low
level on PWR_OFF input pin during module normal operation: the PWR_OFF line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT commands manual [2].
The PWR_OFF input pin is internally connected through a series Schottky diode to 1.5 V internal supply, keeping the line to the high logic level when the PWR_OFF pin is not forced low from the external. See the SARA-G450 data sheet [1] for the detailed electrical characteristics of the PWR_OFF input.
Before the switch-on of the generic digital interface supply source (V_INT) of the module, no
voltage driven by an external application should be applied to any generic digital interface of the modules.
The internal reset state of all digital pins is summarized in the pin description table included in the
SARA-G450 data sheet [1].

1.6.4 Digital I/O interfaces voltage selection (VSEL)

The digital I/O interfaces of SARA-G450 modules (the UART interfaces, I2C interface and GPIO pins) can operate at 1.8 V or 3 V voltage rail. The operating voltage can be selected using the VSEL input pin:
If the VSEL input pin is connected to GND, the digital I/O interfaces operate at 1.8 V
If the VSEL input pin is left unconnected, the digital I/O interfaces operate at 3 V
The operating voltage cannot be changed dynamically: the VSEL input pin configuration has to be set before the boot of SARA-G450 modules and then it cannot be changed after switched on.
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1.7 Antenna interface

1.7.1 Antenna RF interface (ANT)

The ANT pin of SARA-G450 modules represents the RF input/output for 2G RF signals reception and transmission. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the antenna through a 50 transmission line for clean RF signals reception and transmission.
1.7.1.1 Antenna RF interface requirements
Table 7 summarizes the requirements for the antenna RF interface (ANT). See section 2.4.1 for
suggestions to correctly design an antenna circuit compliant to these requirements.
The antenna circuit affects the RF compliance of the device integrating SARA-G450 modules with
applicable required certification schemes. Compliance is not guaranteed if the antenna RF interface (ANT) requirements summarized in Table 7 are not fulfilled.
Item
Requirements
Remarks
Impedance
50  nominal characteristic impedance
The nominal characteristic impedance of the antenna RF connection must match the ANT pin 50 impedance.
Frequency range
See the SARA-G450 data sheet [1]
The required frequency range of the antenna depends on the operating bands supported by the cellular module.
Return loss
S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable
The return loss (or the S11), as the VSWR, refers to the amount of reflected power, measuring how well the RF antenna connection matches the 50 impedance.
The impedance of the antenna RF termination must match as much as possible the 50 impedance of the ANT pin over the operating frequency range, reducing as much as possible the amount of reflected power.
Efficiency
> -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable
The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits.
The efficiency needs to be enough high over the operating frequency range to comply with the Over-The-Air radiated performance requirements, as Total Radiated Power and Total Isotropic Sensitivity, specified by certification schemes
Maximum gain
See section 4 for maximum gain limits
The power gain of an antenna is the radiation efficiency multiplied by the directivity: the maximum gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source.
The maximum gain of the antenna connected to ANT pin must not exceed the values stated in section 4 to comply with regulatory agencies radiation exposure limits.
Input power
> 2 W peak
The antenna connected to ANT pin must support the maximum power transmitted by the modules.
Detection
Application board with antenna detection circuit
If antenna detection is required by the custom application, an appropriate antenna detection circuit must be implemented on the application board as described in section 2.4.2
Antenna assembly with built-in diagnostic circuit
If antenna detection is required by the custom application, the external antenna assembly must be provided with an appropriate diagnostic circuit as described in section 2.4.2
Table 7: Summary of antenna RF interface (ANT) requirements
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1.7.2 Antenna detection interface (ANT_DET)

The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence.
The antenna detection function provided by the ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the u-blox AT commands manual [2] for more details on this feature.
The ANT_DET pin generates a DC current and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So the requirements to achieve antenna detection functionality are the following:
an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
an antenna detection circuit must be implemented on the application board
See section 2.4.2 for design-in guidelines for antenna detection circuits on an application board and diagnostic circuits on an antenna assembly.

1.8 SIM interface

1.8.1 (U)SIM card interface

SARA-G450 modules provide a high-speed SIM/ME interface, including automatic detection and configuration of the voltage required by the connected (U)SIM card or chip.
Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switching from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations.
The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud rate selection, according to the values determined by the SIM card.

1.8.2 SIM card detection interface (SIM_DET)

The SIM_DET pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2.5:
Low logic level at SIM_DET input pin is recognized as SIM card not present
High logic level at SIM_DET input pin is recognized as SIM card present
The SIM card detection function provided by SIM_DET pin is an optional feature that can be implemented / used or not according to the application requirements: an Unsolicited Result Code (URC) can be generated each time that there is a change of status (for more details, see the “simind” value of the <descr> parameter of +CIND and +CMER commands in u-blox AT commands manual [2]).
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1.9 Serial interfaces

SARA-G450 modules provide the following serial communication interfaces:
UART interface: 9-wire unbalanced 1.8 V / 3 V asynchronous serial interface supporting (see 1.9.1) o AT command mode
4
o Data mode and online command mode
4
o MUX functionality, including dedicated GNSS tunneling
5
o FW upgrades by means of the FOAT feature
Secondary auxiliary UART interface
6
: 3-wire unbalanced 1.8 V / 3 V asynchronous serial interface
supporting (see 1.9.2): o AT command mode
4
o Data mode and online command mode
4
o GNSS tunneling
Additional UART interface for FW upgrade and tracing: 3-wire unbalanced 1.8 V / 3 V asynchronous serial interface supporting (see 1.9.3):
o FW upgrades by means of the dedicated tool o Trace log capture (diagnostic purpose)
DDC interface
7
: I2C-bus compatible 1.8 V / 3 V interface supporting (see 1.9.4):
o Communication with u-blox GNSS positioning chips / modules
Secondary auxiliary UART interface is not supported by the “00” product version. This interface
should be left unconnected and should not be driven by external devices.
DDC (I2C) interface is not supported by the “00” product version. This interface should be left
unconnected and should not be driven by external devices.

1.9.1 Primary main serial interface (UART)

1.9.1.1 UART features
The UART interface is a 9-wire unbalanced asynchronous serial interface, supporting:
AT command mode
4
Data mode and Online command mode
4
Multiplexer protocol functionality (see 1.9.1.5)
FW upgrades by means of the FOAT feature (see 1.13.12)
The main characteristics of the interface are the following:
Complete serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [5] with CMOS compatible signal levels: 0 V for low data bit or ON state and 1.8 V / 3 V for high data bit or OFF state (for detailed electrical characteristics, see the SARA-G450 data sheet [1])
Data lines (RXD as output, TXD as input)
Hardware flow control lines (CTS as output, RTS as input)
Modem status and control lines (DTR as input, DSR as output, RI as output, DCD as output)
4
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
5
SARA-G450 modules product version “00” do not support GNSS tunneling.
6
SARA-G450 modules product version “00” do not support secondary auxiliary UART.
7
SARA-G450 modules product version “00” do not support DDC I2C-bus compatible interface.
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SARA-G450 modules UART interface is configured by default in AT command mode: the module waits for AT command instructions and interprets all the characters received as commands to execute. All the functionalities supported by SARA-G450 modules can generally be set and configured with AT commands (see the u-blox AT commands manual [2]).
SARA-G450 modules are designed to operate as a cellular modem, representing the Data Circuit-terminating Equipment (DCE) as per ITU-T V.24 recommendation [5]. The application processor connected to the module through the UART interface represents the Data Terminal Equipment (DTE).
The signal names of SARA-G450 modules UART interface conform to the ITU-T V.24
recommendation [5]: e.g. the TXD line represents the data transmitted by the DTE (application processor data line output) and received by the DCE (module data line input).
HW flow control handshakes or none flow control are supported by the UART interface and can be set by AT commands (see u-blox AT commands manual [2], &K, +IFC AT commands).
Hardware flow control is enabled by default.
SARA-G450 modules support one-shot autobauding: the baud-rate automatic detection is performed once at module start-up, at first AT command received. After detection, the module works at the detected baud-rate and the baud-rate can only be changed with an AT command.
The following baud-rates can be set by the AT+IPR command (see u-blox AT commands manual [2]):
2400 bit/s
4800 bit/s
9600 bit/s
19200 bit/s
38400 bit/s
57600 bit/s
115200 bit/s
One-shot autobauding is enabled by default. The one-shot autobauding feature works only with first AT command in capital letters (i.e. “AT”).
The following frame formats can be set by AT+ICF command (see u-blox AT commands manual [2]):
8N1 (8 data bits, no parity, 1 stop bit), default frame configuration
8E1 (8 data bits, even parity, 1 stop bit)
8O1 (8 data bits, odd parity, 1 stop bit)
8N2 (8 data bits, no parity, 2 stop bit)
The automatic frame format recognition is not supported.
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