The OEMs can embed their own application on top of the integrated Bluetooth low energy
R41Z
Stand-alone Bluetooth 4.2 low energy and IEEE 802.15.4
module
Data sheet
This technical data sheet describes the R41Z stand-alone Bluetooth® low energy and IEEE 802.15.4
module.
stack using the NXP MCUXpresso SDK and integrated development environment (IDE).
UBX-19033355 - R08
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R41Z - Data sheet
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Title R41Z
Subtitle Stand-alone Bluetooth 4.2 low energy and IEEE 802.15.4 module
Document type Data sheet
Document number UBX-19033355
Revision and date R08 17-Feb-2021
Disclosure restriction C1-Public
Product status Corresponding content status
Functional sample DraftFor functional testing. Revised and supplementary data will be published later.
In development /
Prototype
Engineering sample Advance information Data based on early testing. Revised and supplementary data will be published later.
Initial production Early production information Data from product verification. Revised and supplementary data may be published later.
Mass production /
End of life
Objective specification Target values. Revised and supplementary data will be published later.
Production information Document contains the final product specification.
This document applies to the following products:
Product nameType numberIN / PCN referenceProduct status
1.1 Features ........................................................................................................................................................ 6
2.1.2 Power ................................................................................................................................................... 10
2.2 GPIO and LLWU signals ........................................................................................................................... 11
2.8 Radio signals .............................................................................................................................................. 14
2.8.1 Wi-Fi/Bluetooth low energy coexistence signals ........................................................................ 14
2.8.2 Direct test mode (DTM) signals ..................................................................................................... 14
2.8.3 IEEE 802.15.4 Bit streaming mode (BSM) signals .................................................................... 14
2.9 Carrier modulator timer (CMT) signal ................................................................................................... 14
2.10 Single wire debug (SWD) and reset signals ......................................................................................... 14
2.11 RTC and clock signals .............................................................................................................................. 15
2.12 Analog signals ............................................................................................................................................ 15
3.4 General purpose I/O and ports ................................................................................................................ 21
3.5 Analog I/O and VREF ................................................................................................................................ 21
3.5.1 Analog signals ................................................................................................................................... 21
3.5.2 VDDA and VREF ................................................................................................................................ 22
7 Evaluation development kit .......................................................................................................... 31
8 Qualification and approvals .......................................................................................................... 32
8.1 United States (FCC): ................................................................................................................................ 32
8.1.1 Labeling and user information requirements ............................................................................. 32
8.3 European Union regulatory compliance ............................................................................................... 34
8.3.1 Radio Equipment Directive (RED) 2014/53/EU .......................................................................... 34
8.4 Australia / New Zealand (RCM) .............................................................................................................. 34
8.5 Japan (MIC) ................................................................................................................................................ 34
8.6 Bluetooth qualification ............................................................................................................................. 35
11 Ordering information ...................................................................................................................... 39
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R41Z - Data sheet
12 Life support and other high-risk use warnings ....................................................................... 40
Related documents ................................................................................................................................ 41
Revision history ....................................................................................................................................... 41
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R41Z - Data sheet
1 Functional description
The R41Z module from u-blox is a highly integrated, ultra-low power module that enables Bluetooth
low energy and IEEE 802.15.4 connectivity based on the Kinetis KW41Z SoC from NXP
Semiconductors. With an ARM® Cortex™ M0+ processor, embedded 2.4 GHz transceiver supporting
FSK/GFSK and O-QPSK modulations, and integrated antenna, the R41Z provides a complete RF
solution with no additional RF design allowing faster time to market. Equipped with the ability to
concurrently communicate over Bluetooth, Thread, and Zigbee connections, the R41Z offers an
unprecedented level of connectivity in a single module. With an internal DC-DC Converter and a wide
supply voltage range of 0.9 V to 4.2 V, the R41Z can be directly powered by sources ranging from a
single alkaline cell to lithium polymer batteries.
1.1 Features
• Based on the NXP Kinetis KW41Z SoC
• Complete RF solution with an integrated DC-DC converter
• Bluetooth 4.2 1M PHY
• IEEE 802.15.4 with Thread and Zigbee support
• ARM® Cortex™-M0+ 32-bit processor
• Serial Wire Debug (SWD)
• Over-the-Air (OTA) firmware updates
• 512 KB embedded flash memory
• 128 KB RAM
• 25 GPIO, 2 dedicated analog pins
• 16-bit / 500KSPS ADC
• 12-bit DAC
• – 40 °C to +85 °C temperature range
• 16 capacitive touch sensing Inputs
• Two SPI master/slave (12 Mbps)
• Two I2C master/slave
• UART (w/ CTS/RTS and DMA)
• Low power comparator
• Temperature sensor
• Infrared communication interface
• Nine low power modes
• True random number generator
• 128-bit AES HW encryption
• 32-bit Real-Time Clock (RTC)
• Wi-Fi coexistence support
• Dimensions: 10.6 x 16.2 x 2.0 mm
1.2 Applications
• Beacons – iBeacon™, Eddystone, AltBeacon, and so on.
• Low-power sensors
• Fitness devices
• Wearables
• Climate control
• Lighting
• Safety and security
• Home appliances
• Access control
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R41Z - Data sheet
Detail Description
Current consumption
TX only @ 0 dBm, bypass mode 14.7 mA
TX only @ 0 dBm, DCDC enabled,
3.6 V Vin
RX only bypass mode 16.2 mA
RX only, DCDC enabled, 3.6 Vin 6.7 mA
Normal Run CPU @ 48 MHz @ 3.0 V,
DCDC enabled
Very-Low-Power Run CPU @ 4 MHz
@ 3.0 V, DCDC enabled
Very-Low-Leakage Stop 3 (RAM
retained) @ 3.0 V @ 25 °C, DCDC
enabled
Very-Low-Leakage Stop 0 @ 3.0 V
@25 °C, bypass mode
Dimensions
R41Z Length: 16.2 mm ± 0.3 mm
Width: 10.6 mm ± 0.3 mm
Height: 2.0 mm ± 0.1 mm
Hardware
Interfaces SPI Master/Slave x 2
Power supply Boost mode: 0.9 V to 1.8 V, 1.1 V required to startup
Temperature range -40 °C to +85 °C
Certifications
USA (FCC) FCC part 15 modular certification
Canada (ISED) Industry Canada RSS-210 modular certification
Europe (CE) EN 62368-1:2014+A11:2017: Health and Safety of the User
Japan (MIC) Ministry of Internal Affairs and Communications (MIC) of Japan pursuant to the Radio
Australia / New Zealand (RCM)
Bluetooth
Radio chip
NXP KW41Z Additional details: MKW41Z Data Sheet Software & Tools
6.1 mA
4.8 mA
137 µA
1.8 µA
182 nA
UART x 1
Touch Sense Interface x 16
Two-Wire Master/Slave (I2C) x2
GPIO x 25
Analog input x 6
Bypass mode: 1.71 V to 3.6 V
Buck mode: 1.8 V to 4.2 V, 2.1 V required to startup
FCC ID: 2AA9B07
IC: 12208A-07
EN 301 489-1 V2.1.1 & 3.1 (b): Electromagnetic Compatibility
EN 301 489-17 V3.1.1
EN 300 328 V2.1.1 3.2: Effective use of spectrum allocated
Act of Japan
MIC: 210-109448
AS/NZS 4268:2017, Radio equipment and systems – Short range devices
RF-PHY Component (Tested) – DID: D035037; QDID: 95459
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R41Z - Data sheet
2 Pin definition
2.1 Pin assignment
Figure 2: R41Z pin assignment
Pin Name Direction Description Default State at POR KW41Z pin Remarks
2 PTC1 I/O GPIO Disabled PTC1
3 PTC2 I/O GPIO Disabled PTC2
4 PTC3 I/O GPIO Disabled PTC3
5 PTC4 I/O GPIO Disabled PTC4
6 PTC5 I/O GPIO Disabled PTC5
7 PTC6 I/O GPIO Disabled PTC6
8 PTC7 I/O GPIO Disabled PTC7
10 PTC16 I/O GPIO Disabled PTC16
11 PTC17 I/O GPIO Disabled PTC17
12 PTC18 I/O GPIO Disabled PTC18
13 PTC19 I/O GPIO Disabled PTC19
14 PTA0 I/O GPIO SWDIO, Pullup EN PTA0
15 PTA1 I/O GPIO SWCLK, Pulldown EN PTA1
17 PTA2 I/O GPIO Reset, Pullup EN PTA2
18 PTA16 I/O GPIO Disabled PTA16
19 PTA17 I/O GPIO Disabled PTA17
20 PTA18 I/O GPIO Disabled PTA18
21 PTA19 I/O GPIO Disabled PTA19
30 PTB0 I/O GPIO XTAL_OUT_EN
31 PTB1 I/O GPIO Disabled PTB1
32 PTB2 I/O GPIO Disabled PTB2
33 PTB3 I/O GPIO Disabled PTB3
34 PTB16 I/O GPIO EXTAL32K PTB16
36 PTB17 I/O GPIO XTAL32K PTB17
PTB0 See e10224 in NXP
KW41Z errata
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R41Z - Data sheet
ADC/Comparator
ADC/Comparator
Pin Name Direction Description Default State at POR KW41Z pin Remarks
37 PTB18 I/O GPIO Non-maskable
Interrupt req
38 ADC0_P In
input
39 ADC0_N In
input
Table 1: R41Z GPIO / Analog pin-out
N/A ADC0_P
N/A ADC0_N
PTB18
2.1.1 Reference
Pin Name Direction Description Remarks
40 XTAL_OUT Out 32 MHz Clock output
41 VREF I/O Analog reference voltage. Internally or
externally sourced
42 VDDA Power Analog supply. Internally sourced VDDA is connected to V1P8 through a
Table 2: Pin descriptions – Reference
power filtering circuit on the module
2.1.2 Power
Pin Name Direction Description Remarks
1 GND Power Electrical Ground
9 GND Power Electrical Ground
16 GND Power Electrical Ground
22 PSWITCH Input DCDC start signal
23 DCDC_CFG Input DCDC mode
24 GND Power Electrical Ground
25 VCC Power DCDC input
26 DCDC_LP Power DCDC signal
27 V1P8 Power DCDC IO and peripheral voltage
28 GND Power Electrical Ground
29 V1P5 Power DCDC RF supply See the DCDC converter operation
35 GND Power Electrical Ground
43 GND Power Electrical Ground
44 GND Power Electrical Ground
45 GND Power Electrical Ground
Table 3: Power
See the DCDC converter operation
section for details on signal usage
and DCDC modes
section for details on signal usage
and DCDC modes
☞ Internal peripherals on the R41Z (such as UART and I2C) can be routed to multiple pin options
using multiplexing. However, each pin can only be used with certain peripherals. See the following
sections for details on which pins can be used for a given function.
☞ Signal options for a pin are selected using a pin mux value. On many pins, there are multiple signals
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that are accessed with the same pin mux value. See the
details on configuring these functions.
NXP KW41Z Reference Manual for
R41Z - Data sheet
2.2 GPIO and LLWU signals
To use a Pin as GPIO or as a Low Leakage Wake-Up source, use pin mux ALT1. The LLWU pins can be
used to trigger interrupts that can bring the module out of Low Leakage sleep modes.
Signal Direction Description Pin Port Mux Alt Remarks
PTC1 I/O GPIO 2 PTC1 ALT1
PTC2 / LLWU_P10 I/O GPIO, LLWU 3 PTC2 ALT1
PTC3 / LLWU_P11 I/O GPIO, LLWU 4 PTC3 ALT1
PTC4 / LLWU_P12 I/O GPIO, LLWU 5 PTC4 ALT1
PTC5 / LLWU_P13 I/O GPIO, LLWU 6 PTC5 ALT1
PTC6 / LLWU_P14 I/O GPIO, LLWU 7 PTC6 ALT1
PTC7 / LLWU_P15 I/O GPIO, LLWU 8 PTC7 ALT1
PTC16 / LLWU_P0 I/O GPIO, LLWU 10 PTC16 ALT1
PTC17 / LLWU_P1 I/O GPIO, LLWU 11 PTC17 ALT1
PTC18 / LLWU_P2 I/O GPIO, LLWU 12 PTC18 ALT1
PTC19 / LLWU_P3 I/O GPIO, LLWU 13 PTC19 ALT1
PTA0 I/O GPIO 14 PTA0 ALT1
PTA1 I/O GPIO 15 PTA1 ALT1
PTA2 I/O GPIO 17 PTA2 ALT1
PTA16 / LLWU_P4 I/O GPIO, LLWU 18 PTA16 ALT1
PTA17 / LLWU_P5 I/O GPIO, LLWU 19 PTA17 ALT1
PTA18 / LLWU_P6 I/O GPIO, LLWU 20 PTA18 ALT1
PTA19 / LLWU_P7 I/O GPIO, LLWU 21 PTA19 ALT1
PTB0 / LLWU_P8 I/O GPIO, LLWU
PTB1 I/O GPIO 31 PTB1 ALT1
PTB2 I/O GPIO 32 PTB2 ALT1
PTB3 I/O GPIO 33 PTB3 ALT1
PTB16 I/O GPIO 34 PTB16 ALT1
PTB17 I/O GPIO 36 PTB17 ALT1
PTB18 I/O GPIO 37 PTB18 ALT1
Table 4: GPIO and LLWU signal map
30 PTB0 ALT1 See e10224 in
NXP KW41Z errata
2.3 UART signals
Signal Direction Description Pin Port Mux Alt
LPUART0_RX In UART Data Receiver 3
LPUART0_TX Out UART Data Transmit 4
LPUART0_CTS_b In UART Clear to Send 5
LPUART0_RTS_b Out UART Request to Send 2
Table 5: UART signal map
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