This technical data sheet describes the NINA-W10 series stand-alone
multiradio MCU module that integrates a powerful microcontroller
(MCU) and a radio for wireless communication. The module has a
number of important security features embedded, including secure
boot, which ensures the module boots up only in the presence of
authenticated software.
www.u-blox.com
UBX-17065507 - R01
NINA-W10 series
Stand-alone Multiradio modules
Data Sheet
NINA-W10 series - Data Sheet
Document Information
Title
NINA-W10 series
Subtitle
Stand-alone Multiradio modules
Document type
Data Sheet
Document number
UBX-17065507
Revision and date
R01
16-Feb-2018
Disclosure restriction
Product Status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Prod. Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Final product specification.
Product name
Type number
u-blox connectivity software version
PCN reference
Product status
NINA-W101
NINA-W101-00B-00
-
N/A
Initial Production
NINA-W102
NINA-W102-00B-00
-
N/A
Initial Production
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u-blox is a registered trademark of u-blox Holding AG in the EU and other countries. Arm is the registered trademark of Arm Limited in the
EU and other countries.
1.3 Product features ................................................................................................................................... 6
1.6 Radio performance ............................................................................................................................... 7
1.7 CPU ...................................................................................................................................................... 8
1.8 MAC addresses ..................................................................................................................................... 8
1.9 Power modes ........................................................................................................................................ 9
2.1 Power supply ...................................................................................................................................... 10
Data interfaces ....................................................................................................................................... 12
2.7.7 CAN ............................................................................................................................................ 13
2.9 Analog interfaces ................................................................................................................................ 13
2.9.1 Analog to digital converters ......................................................................................................... 13
2.9.2 Digital to analog converters ......................................................................................................... 13
4.2.5 Digital pins .................................................................................................................................. 19
4.2.6 Current consumption .................................................................................................................. 19
4.2.7 Wi-Fi radio characteristics ............................................................................................................ 20
4.2.8 Bluetooth radio characteristics ..................................................................................................... 20
4.2.9 Bluetooth low energy characteristics ........................................................................................... 20
6 Qualification and approvals ...................................................................................... 23
6.1 Country approvals .............................................................................................................................. 23
6.2 European Union regulatory compliance .............................................................................................. 23
6.2.1 Radio Equipment Directive (RED) 2014/53/EU .............................................................................. 23
6.2.2 Compliance with the RoHS directive ............................................................................................ 23
The NINA-W10 series are stand-alone multiradio MCU modules that integrate a powerful microcontroller (MCU)
and a radio for wireless communication. With the open CPU architecture, customers can develop advanced
applications running on the dual core 32-bit MCU. The radio provides support for Wi-Fi 802.11b/g/n in the 2.4
GHz ISM band, Bluetooth BR/EDR, and Bluetooth low energy communications.
The NINA-W10 includes the wireless MCU, flash memory, crystal, and components for matching, filtering,
antenna and decoupling, making it a very compact stand-alone multiradio module. The module can be used to
design solutions with top grade security, thanks to integrated cryptographic hardware accelerators.
Intended applications include telematics, low power sensors, connected factories, connected buildings
(appliances and surveillance), point-of-sales, and health devices.
The modules will initially be certified for the US, Europe, and Canada. Certifications for other countries are
planned. The modules will be qualified according to ISO 16750 for professional grade operation, supporting an
extended temperature range of –40 °C to +85 °C.
1.2 Applications
Internet of Things (IoT)
Wi-Fi networks
Bluetooth and Bluetooth low energy applications
Telematics
Point-of-sales
Medical and industrial networking
Access to laptops, mobile phones, and similar consumer devices
Home/building automation
Ethernet/Wireless Gateway
1.3 Product features
Table 1: NINA-W10 series main features summary
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1.4 Block diagram
Flash (16Mbit)
Linear voltage regulators
Wi-Fi baseband
Baseband
IO Buffers
SRAM (4Mbit)
Cryptographics
accelerations
Quad SPI
VCC_IO
VCC (3.0- 3.6V)
40 MHz
Reset
ANT (NINA-W101)
UART
RMII
*
I2C
*
SPI
*
SDIO
*
Quad SPI
*
JTAG
*
GPIO
ADC/DAC
*
LPO (32.768 kHz, 0.7V)
*
Only on NINA-W101/NINA-W102
EFUSE
CAN
Antenna
(NINA-W102)
NINA-W10 series - Data Sheet
BPF
RF
PLL
Bluetooth
hardware
ROM
*
2xXtensa 32-bit LX6 MCU
Figure 1: Block diagram of NINA-W10 series
1.5 Product variants
The NINA-W10 modules have open CPU architecture tailored for OEMs who wish to embed their own
application on top of the available Wi-Fi functionality including support for Bluetooth and Bluetooth low energy.
1.5.1 NINA-W101
The NINA-W101 modules do not use the internal antenna and thus the PCB outline has been trimmed to
10.0 x 10.6 mm. Instead of an internal antenna, the RF signal is available at a module pin for routing to an
external antenna or antenna connector.
1.5.2 NINA-W102
The NINA-W102 modules use an integrated antenna mounted on the PCB. The PCB outline is 10.0 x 14.0 mm.
The RF signal pin is not connected to any signal path.
1.6 Radio performance
The NINA-W10 series (NINA-W101 and NINA-W102) modules support Wi-Fi and conform to IEEE 802.11b/g/n
single-band 2.4 GHz operation, Bluetooth BR/EDR, and Bluetooth low energy as explained in Table 2.
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NINA-W10 series - Data Sheet
Wi-Fi
Bluetooth BR/EDR
Bluetooth Low Energy
IEEE 802.11b/g/n
Bluetooth v4.2 BR/EDR
Maximum number of slaves: 7
Bluetooth 4.2 BLE dual-mode
Band support
2.4 GHz, channel 1-13*
Band support
2.4 GHz, 79 channels
Band support
2.4 GHz, 40 channels
Maximum conducted output power
16 dBm
Maximum conducted output power
5 dBm
Maximum conducted output power
5 dBm
Maximum radiated output power
19 dBm EIRP**
Maximum radiated output power
8 dBm EIRP**
Maximum radiated output power
8 dBm EIRP**
Conducted sensitivity
-96 dBm
Conducted sensitivity
-90 dBm
Conducted sensitivity
-90 dBm
Data rates:
IEEE 802.11b:
1 / 2 / 5.5 / 11 Mbit/s
IEEE 802.11g:
6 / 9 / 12 / 18 / 24 / 36 / 48 / 54 Mbit/s
IEEE 802.11n:
MCS 0-7, HT20 (6.5-72 Mbit/s)
Data rates:
1 / 2 / 3 Mbit/s
Data rates:
1 Mbit/s
*
Depending on the location (country or region), channels 12-13 must be limited or disabled; the software implementation must support
country determination algoritms for using channel 12-13, for example, with 802.11d. See section 6.1 for more info.
**
RF power including maximum antenna gain (3 dBi).
Table 2: NINA-W10 series - Wi-Fi and Bluetooth characteristics
1.7 CPU
The NINA-W10 series has a dual-core system with two Harvard Architecture Xtensa LX6 CPUs with max 240
MHz internal clock frequency. The internal memory of NINA-W1 includes the following:
448 Kbyte ROM for booting and core functions
520 Kbyte SRAM for data and instruction
16 Mbit FLASH for code storage including hardware encryption to protect programs and data
1 kbit EFUSE (non- erasable memory) for MAC addresses, module configuration, Flash-Encryption, and
Chip-ID
The open CPU variants (NINA-W101/NINA-W102) also support external FLASH and SRAM memory via a Quad SPI
interface (see section 0). Software options
NINA-W10 has no software and provides an open CPU architecture. With the open CPU architecture, customers
can develop advanced applications running on the dual core 32-bit MCU. The radio provides support for Wi-Fi
802.11b/g/n in the 2.4 GHz ISM band, Bluetooth BR/EDR, and Bluetooth low energy communication. It is the
responsibility of the customer to comply with the NINA-W10 certification and configuration as mentioned in
section 6.1.
The module can be used to design solutions with top grade security, thanks to integrated cryptographic
hardware accelerators. This enables secure boot, which ensures the module boots up only in the presence of
authenticated software.
1.7.1 Software upgrade
Information on how to upgrade the software for NINA-W10 series is provided in the NINA-W10 series System
Integration Manual [1].
1.8 MAC addresses
The NINA-W10 module series has four unique consecutive MAC addresses reserved for each module and the
addresses are stored in the configuration memory during production. The first Wi-Fi MAC address is available in
the Data Matrix on the label (see section 9.1).
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NINA-W10 series - Data Sheet
MAC address
Assignment
Last bits of MAC address
Example
Module 1, address 1
Wi-Fi
00
D4:CA:6E:90:04:90
Module 1, address 2
RMII/Ethernet
01
D4:CA:6E:90:04:91
Module 1, address 3
Bluetooth
10
D4:CA:6E:90:04:92
Module 1, address 4
Reserved
11
D4:CA:6E:90:04:93
Module 2, address 1
Wi-Fi
00
D4:CA:6E:90:04:94
Module 2, address 2
RMII/Ethernet
01
D4:CA:6E:90:04:95
Module 2, address 3
Bluetooth
10
D4:CA:6E:90:04:96
Module 2, address 4
Reserved
11
D4:CA:6E:90:04:97
Table 3: Example MAC addresses assignment for two modules
1.9 Power modes
The NINA-W10 series modules are power efficient devices capable of operating in different power saving modes
and configurations. Different sections of the module can be powered off when not needed and complex wake
up events can be generated from different external and internal inputs. For the lowest current consumption
modes, an external LPO clock is required (see section 2.2).
See the Espressif ESP32 Datasheet [3] for more information about power modes.
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NINA-W10 series - Data Sheet
Pin
State during boot
Default
Behavior
Description
36
0
VDD_SDIO=3.3V
Voltage of Internal Flash
1
10 kΩ pull-up
VDD_SDIO=1.8V
(VDD_SDIO should always be 1.8 V)
27, 25
00 Download Boot
Booting Mode, see section
0 for information about
software upgrade.
01 Reserved, do not use
10
Pull-up*, Pull-down
*
Normal Boot from internal Flash
11
Normal Boot from internal Flash
2 Interfaces
2.1 Power supply
The power for NINA-W10 series modules is supplied through VCC and VCC_IO pins by DC voltage.
The system power supply circuit must be able to support peak power (add 20% as margin over the
listed type current consumption), as during operation, the current drawn from VCC and VCC_IO can vary
significantly based on the power consumption profile of the Wi-Fi technology.
2.1.1 Module supply input (VCC)
The NINA-W10 series modules use an integrated Linear Voltage converter to transform the supply voltage
presented at the VCC pin into a stable system voltage.
2.1.2 Digital I/O interfaces reference voltage (VCC_IO)
All modules in the NINA-W10 series provide an additional voltage supply input for setting the I/O voltage level.
The separate VCC_IO pin enables integration of the module in many applications with different voltage levels
(for example, 1.8 V or 3.3 V) without any level converters. The NINA-W1 modules support only 3.3 V as IO
voltage level currently.
2.2 Low Power Clock
The NINA-W10 series module does not have an internal low power oscillator (LPO), which is required for low
power modes. An external 32.768 KHz LPO signal can be supplied externally via the LPO_CLK pin if low power
modes are required.
The low power clock voltage level is lower (0/0.7 V) compared to the digital signal levels and a
voltage divider can be required (see section 4.2.4).
2.3 Module reset
The NINA-W10 series modules can be reset (rebooted) in with a low level on the RESET_N pin, which is normally
set high by an internal pull-up. This causes “hardware” reset of the module. The RESET_N signal should be
driven by an open drain, open collector or contact switch. When RESET_N is low (off), the chip works at the
minimum power.
2.4 Boot strapping pins
There are several boot configuration pins available on the module that must have the correct settings during
boot. It is important that they are in the default state (marked with bold in Table 4) during startup for normal
operation. The default state is automatically selected (with internal pull-ups or pull-downs) if the pins are left
unconnected.
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NINA-W10 series - Data Sheet
Pin
State during boot
Default
Behavior
Description
32
0
Silent
Debugging Log on U0TXD
during booting
1
Pull-up*
U0TXD Toggling
32, 28
00
Falling-edge input, falling-edge output
Timing of SDIO Slave
01
Falling-edge input, rising-edge output
10
Rising-edge input, falling-edge output
11
Pull-up*, Pull-up
*
Rising-edge input, rising-edge output
*
About 30 kΩ
Table 4: NINA-W10 series boot strapping pins
2.5 RF antenna interface
The RF antenna interface of the NINA-W10 series supports Bluetooth BR/EDR and Bluetooth low energy on the
same RF antenna signal (the signal is switched between Bluetooth and Wi-Fi as the different RF technologies are
never active simultaneously). The module is equipped with a 2.4 GHz bandpass filter between the radio chip and
RF antenna interface (see section 1.4).
The NINA-W10 series supports either an internal antenna (NINA-W102) or external antennas connected through
an antenna pin (NINA-W101).
2.5.1 Internal antenna
The NINA-W102 module has an internal (embedded) 2.4 GHz PIFA antenna. The internal antenna is a PIFA
antenna specifically designed and optimized for the NINA form factor.
Keep a minimum clearance of 5 mm between the antenna and the casing. Keep a minimum of 10 mm free
space from the metal around the antenna including the area below. If a metal enclosure is required, use
NINA-W101/ and an external antenna.
It is recommended to place the NINA-W102/ modules in such a way that the internal antenna is in the corner of
the host PCB (the corner closest to Pin 16 should be in the corner). The antenna side (short side closest to the
antenna), positioned along one side of the host PCB ground plane is the second best option. It is beneficial to
have a large solid ground plane on the host PCB and have a good grounding on the NINA-W102/ module.
Minimum ground plane size is 24x30 mm but recommended is more than 50x50 mm.
See the NINA-W1 series System Integration Manual [1] for more information about antenna related design.
The ANT signal is not available on the solder pins of the NINA-W102 module.
2.5.2 External RF antenna interface
The NINA-W101 module has an antenna signal (ANT) pin with a characteristic impedance of 50 Ω for using an
external antenna. The antenna signal supports both Tx and Rx.
The external antenna, for example, can be an SMD antenna (or PCB integrated antenna) on the host board. An
antenna connector for using an external antenna via a coaxial cable could also be implemented. A cable antenna
might be necessary if the module is mounted in a shielded enclosure such as a metal box or cabinet.
An external antenna connector (U.FL. connector) reference design (see the NINA-W1 series System Integration Manual[1]) is available and must be followed to comply with the NINA-W1 FCC/IC modular approvals.
Also see the list of approved antennas (section 7.2).
2.6 IO signals
The NINA-W1 module has 36 pins in total, out of which 20 can be used as input and output and 4 signals are
only inputs. The pins can be used as GPI(O) but are also multiplexed with the digital and analog interfaces. There
are four input only signals (GPI) that can only be input regardless of the selected function/interface.
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NINA-W10 series - Data Sheet
SPI signal
Dual SPI signal
Quad SPI signal
DI
IO0
IO0
DO
IO1
IO1
WP - IO2
HD - IO3
CS
CS
CS
CLK
CLK
CLK
It is also possible to multiplex all interfaces via an IO MUX to any pin but the speed is limited (see section 4.2.5).
2.6.1 Pulse Width Modulation (PWM)
The Pulse Width Modulation (PWM) functionality, for example, can be used to control the intensity of LEDs and
driving digital motors. The controller consists of PWM timers, the PWM operator, and a dedicated capture submodule. Each timer provides timing in synchronous or independent form, and each PWM operator generates the
waveform for one PWM channel. The PWM controller has 16 channels, which can generate independent
waveforms that can be used to drive RGB LED devices. For maximum flexibility, the high-speed as well as the
low-speed channels can be driven from one of four high-speed/low-speed timers. The PWM controller also has
the ability to automatically increase or decrease the duty cycle gradually, allowing for fades without any
processor interference. The PWM signals can be configured to be available on any of the GPIO pins via the IO
MUX.
2.7 Data interfaces
2.7.1 UARTs
NINA-W101/NINA-W102 modules have two UART interfaces - UART0 and UART1, which provide asynchronous
communication; for example, supporting RS232, RS485 and IrDA (external drivers are required). UART0 is the
main port and is named UART in this document. The maximum speed is 5 Mbps. The UART0 and UART1 can be
routed to any GPIO pins via the IO MUX but it is recommended to keep UART0 on the default pins (see section
3.1) as the firmware upgrade is done on the UART0 default pins (see section 1.7.1).
The UART provides hardware management of the CTS and RTS signals and software flow control (XON and
XOFF).
2.7.2 RMII
The RMII (Reduced Media-Independent Interface) Ethernet interface is intended for connecting to an external
PHY. The flow control of the UART0 interface is multiplexed with the RMII interface and cannot be used
simultaneously. An MDIO (Management Data Input/Output) interface used for controlling the external PHY is
also available. The pins for the MDIO interface are configurable by software but the proposed pins as specified in
chapter 3 are recommended for use.
2.7.3 SPI
Two SPI interfaces are available for the application. One SPI interface with the name SPI_V and another interface
by name SPI_H (the SPI_H interface is multiplexed with the JTAG and SDIO interfaces). It is possible to connect
the SPI interfaces to other pins via the IO MUX but the maximum speed will be reduced. It is also possible to
configure the SPI interface as a dual or quad SPI (2 or 4 bit -bidirectional data signals), see section 0.
2.7.4 Dual/Quad SPI
The dual/quad SPI (2 or 4 bi-bidirectional data signals) can be used for connecting an additional external flash or
SRAM. The SPI to dual/quad SPI signal mapping are shown in Table 5.
Table 5: SPI to dual/quad SPI signal mapping
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NINA-W10 series - Data Sheet
2.7.5 I
Three I2C interfaces can be configured on any GPIO pins.
The NINA-W101/NINA-W102 modules can operate as both master and slave on the I2C bus using both standard
(100 kbps) and fast (400 kbps) transmission speeds. The interface uses the SCL signal to clock instructions and
data on the SDL signal.
2
C
2.7.6 SDIO
SDIO is multiplexed with the JTAG interface and the second SPI interface (SPI_H). It is possible to connect the
SDIO interfaces to other pin via the IO MUX but the speed is limited (see section 4.2.5). Only SDIO host is
supported (not SDIO slave).
2.7.7 CAN
The NINA-W101/NINA-W102 modules support CAN2.0.
2.8 Debug interfaces
2.8.1 JTAG debug interfaces
The NINA-W101 and NINA-W102 modules support the JTAG debug interface (JTAG_TMS, JTAG_CLK,
JTAG_TDI and JTAG_TDO). The JTAG interface is multiplexed with the SDIO and the second SPI interface
(SPI_H).
2.9 Analog interfaces
2.9.1 Analog to digital converters
The NINA-W101 and NINA-W102 modules have four pins marked as Analog to Digital Converter (ADC) input
signals (ADC_2, ADC_3, ADC_4 and ADC_34), see chapter 3. These pins are primarily recommended for the
ADC application (to be compatible with future NINA modules). There are also 13 additional GPIO pins that can
be used for ADC application (see pins marked with an ADC-CH in the “ESP-32” column of Table 6. The analog
converters are 12-bit SAR ADCs. The NINA-W101 and NINAW102 modules can measure the voltages while
operating in the sleep mode, to enable low power consumption; the CPU can be woken up by a threshold
setting.
Analog pins cannot be re-routed to other pins via the IO MUX.
2.9.2 Digital to analog converters
Two 8-bit DAC channels ADC_16 and ADC_17 can be used to convert the two digital signals into two analog
voltage signal outputs. The design structure is composed of integrated resistor strings and a buffer. This dual
DAC has VCC as input voltage reference and can drive other circuits. The dual channels support independent
conversions.
Analog pins cannot be rerouted to other pins via the IO MUX.
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NINA-W10 series - Data Sheet
3 Pin definition
3.1 Pin assignment
The NINA-W10 module has 36 pins in total, out of which 20 can be used as input and output and 4 signals are
only inputs signals.
Figure 2 shows the multiplexed pinout for NINA-W101 and NINA-W102 Open CPU modules. Some additional
interfaces that are available are not shown in Figure 2 (see Table 6 for additional interfaces). The part below the
dotted line in Figure 2 is the antenna area of NINA-W102 and the outline of the NINA-W101 module ends at the
dotted line. It is also possible to multiplex all interfaces via an IO MUX to any pin but the maximum speed is
limited (see section 4.2.5).
Figure 2: NINA-W10 pin assignment (top view)
The grey pins in the center of the modules are GND pins. The lower part below the dotted line is the
antenna part of NINA-W102 and the outline of the NINA-W101 module ends at this line.
Pins 2, 3, 4, and 34 can only be used as input signals (GPI) regardless of the selected function/interface. Some of the signals are boot strap signals (see Table 6). It is important that these signals are in the correct
state during startup (see section 2.4).
UBX-17065507 - R01Pin definition
Page 14 of 44
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