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NEO-D9S
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U-blox NEO-D9S Integration manual

NEO-D9S
u-blox D9 correction data receiver
Integration manual
Abstract
This document describes the features and specifications of the u-blox D9 correction data receiver.
www.u-blox.com
NEO-D9S-Integration manual
Document information
Title NEO-D9S
Subtitle u-blox D9 correction data receiver
Document type Integration manual
Document number UBX-19026111
Revision and date R05 17-Nov-2020
Document status Early production information
Disclosure restriction C1-Public
This document applies to the following products:
Product name Type number Firmware version PCN reference
NEO-D9S NEO-D9S-00B-00 PMP 1.04 N/A
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided "as is" and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given with respect to, including but not limited to, the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u blox.com.
Copyright © 2020, u-blox AG.
u-blox is a registered trademark of u-blox Holding AG in the EU and other countries.
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Contents

1 Integration manual structure............................................................................................ 5
2 System description...............................................................................................................6
2.1 Overview.................................................................................................................................................... 6
2.1.1 Satellite L band DGNSS................................................................................................................6
2.2 Architecture..............................................................................................................................................6
2.2.1 Block diagram..................................................................................................................................6
3 Receiver functionality..........................................................................................................7
3.1 Receiver configuration........................................................................................................................... 7
3.1.1 Changing the receiver configuration..........................................................................................7
3.1.2 Default L band configuration.......................................................................................................7
3.1.3 Default interface settings............................................................................................................ 7
3.1.4 Basic receiver configuration.........................................................................................................8
3.1.5 L band service selection............................................................................................................... 8
3.1.6 Power management....................................................................................................................... 9
3.2 Communication interfaces................................................................................................................. 10
3.2.1 UART...............................................................................................................................................11
3.2.2 I2C interface..................................................................................................................................12
3.2.3 SPI interface..................................................................................................................................15
3.2.4 USB interface................................................................................................................................16
3.3 Predefined PIOs..................................................................................................................................... 17
3.3.1 D_SEL..............................................................................................................................................17
3.3.2 RESET_N........................................................................................................................................17
3.3.3 SAFEBOOT_N................................................................................................................................17
3.3.4 TX_READY..................................................................................................................................... 18
3.3.5 EXTINT............................................................................................................................................18
3.4 Antenna supervisor..............................................................................................................................18
3.4.1 Antenna voltage control - ANT_OFF........................................................................................20
3.4.2 Antenna short detection - ANT_SHORT_N............................................................................ 20
3.4.3 Antenna short detection auto recovery.................................................................................. 21
3.4.4 Antenna open circuit detection - ANT_DETECT................................................................... 21
3.5 Security................................................................................................................................................... 22
3.5.1 Receiver status monitoring....................................................................................................... 22
3.6 Forcing a receiver reset....................................................................................................................... 22
3.7 Firmware upload....................................................................................................................................22
4 Design..................................................................................................................................... 23
4.1 Pin assigment........................................................................................................................................ 23
4.2 Antenna...................................................................................................................................................24
4.2.1 Antenna bias.................................................................................................................................27
4.3 Power supply.......................................................................................................................................... 29
4.3.1 VCC: Main supply voltage.......................................................................................................... 29
4.3.2 NEO-D9S power supply.............................................................................................................. 29
4.4 NEO-D9S minimal design................................................................................................................... 30
4.5 EOS/ESD precautions.......................................................................................................................... 30
4.5.1 ESD protection measures.......................................................................................................... 31
Contents Page 3 of 51
4.5.2 EOS precautions...........................................................................................................................31
4.5.3 Safety precautions...................................................................................................................... 32
4.6 Electromagnetic interference on I/O lines.......................................................................................32
4.6.1 General notes on interference issues...................................................................................... 32
4.6.2 In-band interference mitigation................................................................................................ 33
4.6.3 Out-of-band interference........................................................................................................... 33
4.7 Layout...................................................................................................................................................... 34
4.7.1 Placement......................................................................................................................................34
4.7.2 Thermal management................................................................................................................ 34
4.7.3 Package footprint, copper and paste mask........................................................................... 34
4.7.4 Layout guidance........................................................................................................................... 36
4.8 Design guidance....................................................................................................................................38
4.8.1 General considerations............................................................................................................... 38
4.8.2 RF front-end circuit options...................................................................................................... 38
4.8.3 Antenna/RF input........................................................................................................................ 39
4.8.4 Schematic design........................................................................................................................ 39
4.8.5 Layout design-in guideline......................................................................................................... 40
5 Product handling................................................................................................................. 41
5.1 ESD handling precautions.................................................................................................................. 41
5.2 Soldering.................................................................................................................................................41
5.3 Tapes....................................................................................................................................................... 44
5.4 Reels........................................................................................................................................................ 45
5.5 Moisture sensitivity levels.................................................................................................................. 45
Appendix.................................................................................................................................... 46
A Stacked patch antenna.......................................................................................................................... 46
B Glossary......................................................................................................................................................47
Related documents................................................................................................................ 49
Revision history.......................................................................................................................50
NEO-D9S-Integration manual

1 Integration manual structure

This manual provides a wealth of information to enable a successful design with the u-blox D9 correction data receiver. The manual is structured according to system, software and hardware aspects.
The first section, "System description" gives an overview of the u-blox D9 correction data receiver with a block diagram of NEO-D9S.
The following section "Receiver functionality" provides an exhaustive description of the receiver's functionality. Beginning with the new configuration messages, both existing and new users should read this section to understand the new message types employed. Most of the following sub­sections should be familiar to existing users of u-blox positioning products, however some changes are introduced owing to the new configuration messages.
The sections from "Design" onwards address hardware options when designing NEO-D9S into a new product. This part gives power supply recommendations and provides guidance for circuit design and PCB layout assistance. The antenna and RF front-end sections provide design information and recommendations for these essential components. The final "Design guidance" section helps the designer to check that crucial aspects of the design-in process have been carried out.
The final section addresses the general product handling concerns giving guidance on ESD precautions, production soldering considerations and tape and reel packaging information.
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2 System description

2.1 Overview

NEO-D9S can receive the data stream of a GNSS correction service, broadcast via satellite L band and compliant to the specification the product is designed for. Integrated with a high precision GNSS receiver, such as from the u-blox F9 platform, it enables the positioning system to reach down to centimeter-level accuracy.

2.1.1 Satellite L band DGNSS

Wide area correction services from several service providers are available via the L band communication satellites. These satellites cover the bulk of the globe's populated surface. However each DGNSS service provider using the L band channel will possibly have spot beams only covering the relevant area their corrections are valid for. This ensures their correction coverage area is accessible via a satellite and not simply broadcast over large areas of the earth with no feasible use.
Each service provider will be allocated a correction service ID and a frequency for a particular part of the globe. In addition the service provider will have a data bit rate for their data stream.
This means that the frequency allocation for a particular service provider could change. It is important that any deployed system can be re-configured if necessary. Service providers do provide information on any frequency changes when required.

2.2 Architecture

The NEO-D9S receiver provides all the necessary RF and baseband processing to enable multi-band, multi-constellation operation. The block diagram below shows the key functionality.

2.2.1 Block diagram

Figure 1: NEO-D9S block diagram
An active antenna is mandatory with the NEO-D9S.
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3 Receiver functionality

This section describes the NEO-D9S operational features and their configuration.
3.1 Receiver configuration
u-blox positioning receivers are fully configurable with UBX protocol messages. The configuration used by the receiver during normal operation is called the "current configuration". The current configuration can be changed during normal operation by sending UBX configuration messages. On start-up the current configuration held in RAM is built from the default firmware settings plus any settings held in flash memory.
Configuration interface settings are held in a database consisting of separate configuration items. An item is made up of a pair consisting of a key ID and a value. Related items are grouped together and identified under a common group name: CFG-GROUP-*; a convention used in u-center and within this document. Within u-center, a configuration group is identified as "Group name" and the configuration item is identified as the "item name" under the "Generation 9 Configuration View" ­"Advanced Configuration" view.
The UBX messages available to change or poll the configurations are the UBX-CFG-VALSET, UBX­CFG-VALGET, and UBX-CFG-VALDEL messages. For more information about these messages and the configuration keys see the configuration interface section in the NEO-D9S Interface description [3].
3.1.1 Changing the receiver configuration
The configuration messages UBX-CFG-VALSET, UBX-CFG-VALGET and UBX-CFG-VALDEL, will result in a UBX-ACK-ACK or a UBX-ACK-NAK response.
3.1.2 Default L band configuration
The default L band configuration is:
• CFG-PMP-CENTER_FREQUENCY = 1539812500 Hz
• CFG-PMP-SEARCH_WINDOW = 2200 Hz
• CFG-PMP-USE_SERVICE_ID = 1 (true)
• CFG-PMP-SERVICE_ID = 50821
• CFG-PMP-DATA_RATE = 2400 (B2400) bps
• CFG-PMP-USE_DESCRAMBLER = 1 (true)
• CFG-PMP-DESCRAMBLER_INIT = 23560
• CFG-PMP-UWERRT = 4
• CFG-PMP-USE_PRESCRAMBLING = 0 (false)
• CFG-PMP-UNIQUE_WORD = 0xe15ae893e15ae893
The required satellite center frequency and service data rate might need changing based on the receiver global location to aid acquisition of the required satellite/service (service ID).
The configuration settings can be modified using UBX protocol configuration messages. For more information, see the NEO-D9S Interface description [3].

3.1.3 Default interface settings

Interface Settings
UART 9600 baud, 8 bits, no parity bit, 1 stop bit.
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Interface Settings
Output protocol: UBX.
Input protocols without need of additional configuration: UBX.
USB Output messages activated as in UART. Input protocols available as in UART.
I2C Output messages activated as in UART. Input protocols available as in UART.
SPI Output messages activated as in UART. Input protocols available as in UART.
Table 1: Default interface settings
The boot message is still output using $GNTXT messages, this is output when the NEO­D9S is powered up.
Refer to the u-blox NEO-D9S Interface description [3] for information about further settings.
3.1.4 Basic receiver configuration
This section summarizes the basic receiver configuration most commonly used.
3.1.4.1 Communication interface configuration
Several configuration groups allow operation mode configuration of the various communication interfaces. These include parameters for the data framing, transfer rate and enabled input/output protocols. See Communication interfaces section for details. The configuration groups available for each interface are:
Interface Configuration groups
UART1 CFG-UART1-*, CFG-UART1INPROT-*, CFG-UART1OUTPROT-*
USB CFG-USB-*, CFG-USBINPROT-*, CFG-USBOUTPROT-*
Table 2: Interface configurations
3.1.4.2 Message output configuration
The rate of the supported output messages is configurable.
If the rate configuration value is zero, then the corresponding message will not be output. Values greater than zero indicate how often the message is output.
For periodic output messages the rate relates to the event the message is related to. The rates of the output messages are individually configurable per communication interface. See the CFG­MSGOUT-* configuration group.
Some messages, such as UBX-MON-VER, are non-periodic and will only be output as an answer to a poll request.
The UBX-INF-* information messages are non-periodic output messages that do not have a message rate configuration. Instead they can be enabled for each communication interface via the CFG-INFMSG-* configuration group.
All message output is additionally subject to the protocol configuration of the communication interfaces. Messages of a given protocol will not be output until the protocol is enabled for output on the interface (see the Communication interface configuration).

3.1.5 L band service selection

Any particular service provider will have several requirements that need to be configured before the receiver will provide the relevant service provider data:
• Service provider service ID
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• Service provider frequency based on geographical location
• Service provider data rate
The service provider will provide the information on the frequency required per geographical location.
All relevant configurations are done via the CFG-PMP message.
The main settings are shown below:
• CFG-PMP-SERVICE_ID - Example, 50821
• CFG-PMP-CENTER_FREQUENCY - Can be set from 1525000000 to 1559000000 Hz
• CFG-PMP-DATA_RATE - Can be set from 600 bps to 4800 bps
There may be additional settings required that can be configured from the information supplied by the service provider.
The receiver will output raw L band correction data when a service provider satellite data frame is received. This will be output in the UBX-RXM-PMP message. This message is not output at a fixed rate.
If no selected service provider data frame is detected, no UBX-RXM-PMP message is sent. The output rate of the UBX-RXM-PMP message depends on the data rate of the satellite data stream (600 bps - 4800 bps). The validity of the data frame must be verified by the host software. For frame verification, quality indicators included in this message can be used.
For more information see the Configuration Interface section in the NEO-D9S Interface description [3].
Figure 2: L band SESTB-28A data frame

3.1.6 Power management

u-blox D9 correction data receiver supports two different externally controlled power modes.
• External cycling of the receiver main power supply with the receiver in continuous mode when powered (no battery backup software/hardware feature is supported, however V_BCKP must be connected to VCC for correct core operation.)
• Instruct the receiver to turn on/off into software back-up mode (with main power still applied) via the UBX-RXM-PMREQ message
3.1.6.1 Continuous mode
u-blox receivers use dedicated signal processing engines optimized for signal acquisition and tracking. The acquisition engine delivers rapid signal searches during cold starts or when insufficient signals are available for data download. The tracking engine delivers signal measurements for message decoding.
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3.1.6.2 Power on/off command - software back-up
With message UBX-RXM-PMREQ the receiver can be forced to enter Inactive state (software back­up mode) with main power still applied. It will stay in Inactive state for the time specified in the message or until it is woken up by activity on the RXD1, NRESET pin or EXTINT pin.
3.1.6.2.1 Wake up
The receiver can be woken up by generating an edge on one of the following pins:
• Rising or falling edge on one of the EXTINT pins
• Rising or falling edge on the RXD1 pin
• Rising edge on NRESET pin
All wake-up signals are interpreted as an acquisition request, where the receiver wakes up and tries to obtain the satellite. Wake-up signals have no effect if the receiver is already in Acquisition, Tracking state.
3.1.6.2.2 Behavior while USB host connected
As long as the receiver is connected to a USB host, it will not enter the lowest possible power state. This is because it must retain a small level of CPU activity to avoid breaching requirements of the USB specification. The drawback, however, is that power consumption is higher.
Wake up by N_RESET, EXTINT pin or UART RX is possible even if the receiver is connected to a USB host. In this case the state of the pin must be changed for a duration longer than one millisecond.

3.2 Communication interfaces

u-blox receivers are equipped with a communication interface which is multi-protocol capable. The interface ports can be used to transmit GNSS measurements, monitor status information and configure the receiver.
A protocol (e.g. UBX, NMEA) can be assigned to several ports simultaneously, each configured with individual settings (e.g. baud rate, message rates, etc.). More than one protocol (e.g. UBX protocol and NMEA) can be assigned to a single port (multi-protocol capability), which is particularly useful for debugging purposes.
The NEO-D9S provides UART1, UART2, SPI, I2C and USB interfaces for communication with a host CPU. The interfaces are configured via the configuration methods described in the NEO-D9S interface description [3].
The following table shows the port numbers reported in the UBX-MON-COMMS messages.
Port no. UBX-MON-COMMS portId Electrical interface
0 0x0000 I2C
1 0x0100 UART1
3 0x0300 USB
4 0x0400 SPI
Table 3: Port number assignment
It is important to isolate interface pins when VCC is removed. They can be allowed to float or be connected to a high impedance (Float or tri-state: Hi-Z state). Open collector circuits powered by module VCC are also suitable. They must be powered by module VCC to ensure correct pin state when module VCC is removed.
Example isolation circuit is shown below.
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Figure 3: NEO-D9S output isolation
NEO-D9S-Integration manual
Figure 4: NEO-D9S input isolation

3.2.1 UART

A Universal Asynchronous Receiver/Transmitter (UART) port consists of an RX and a TX line. Neither handshaking signals nor hardware flow control signals are available. The UART interface protocol and baud rate can be configured but there is no support for setting different baud rates for reception and transmission.
The NEO-D9S includes two UART serial ports. UART1 can be used as a host interface for configuration, monitoring and control.
The UART RX interface will be disabled when more than 100 frame errors are detected during a one-second period. This can happen if the wrong baud rate is used or the UART RX pin is grounded. An error message appears when the UART RX interface is re-enabled at the end of the one-second period.
Baud rate Data bits Parity Stop bits
9600 8 none 1
19200 8 none 1
38400 8 none 1
57600 8 none 1
115200 8 none 1
230400 8 none 1
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Baud rate Data bits Parity Stop bits
460800 8 none 1
921600 8 none 1
Table 4: Possible UART interface configurations
Note that for protocols such as UBX, it does not make sense to change the default word length values (data bits) since these properties are defined by the protocol and not by the electrical interface.
If the amount of data configured is too much for a certain port's bandwidth (e.g. all UBX messages output on a UART port with a baud rate of 9600), the buffer will fill up. Once the buffer space is exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate and communication speed or the number of enabled messages should be carefully selected so that the expected number of bytes can be transmitted in less than one second.

3.2.2 I2C interface

An I2C interface is available for communication with an external host CPU or u-blox cellular modules. The interface can be operated in slave mode only. The I2C protocol and electrical interface are fully compatible with the I2C industry standard fast mode. Since the maximum SCL clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s. The SCL and SDA pins have internal pull-up resistors which should be sufficient for most applications. However, depending on the speed of the host and the load on the I2C lines additional external pull-up resistors may be necessary.
To use the I2C interface D_SEL pin must be left open.
In designs where the host uses the same I2C bus to communicate with more than one u­blox receiver, the I2C slave address for each receiver must be configured to a different value. Typically most u-blox receivers are configured to the same default I2C slave address value. To poll or set the I2C slave address, use the CFG-I2C-ADDRESS configuration item (see NEO­D9S Interface description [3]).
The CFG-I2C-ADDRESS configuration item is an 8-bit value containing the I2C slave address in 7 most significant bits, and the read/write flag in the least significant bit.The default value for the CFG-I2C-ADDRESS configuration item is 0x86 (10000110). This indicates a standard 7-bit I2C slave address of 0x43 (1000011).
3.2.2.1 I2C register layout
The I2C interface allows 256 registers to be addressed. As shown in Figure 5, only three of these are currently implemented.
The data registers 0 to 252 at addresses 0x00 to 0xFC contain reserved information, the result from their reading is currently undefined. The data registers 0 to 252 are 1 byte wide.
At addresses 0xFD and 0xFE it is possible to read the currently available number of bytes.
The register at address 0xFF allows the data stream to be read. If there is no data awaiting transmission from the receiver, then this register delivers value 0xFF, which cannot be the first byte of a valid message. If the message data is ready for transmission, the successive reads of register 0xFF will deliver the waiting message data.
Do not use registers 0x00 to 0xFC. They are reserved for future use and they do not currently provide any meaningful data.
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Figure 5: I2C register layout
3.2.2.2 Read access types
There are two I2C read transfer forms:
• The "random access" form: includes a slave register address and allows any register to be read.
• The "current address" form: omits the register address.
Figure 6 shows the format of the first one, the "random access" form of the request. Following the
start condition from the master, the 7-bit device address and the RW bit (which is a logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers with an acknowledge (logic low) to indicate that it recognizes the address.
Next, the 8-bit address of the register to be read must be written to the bus. Following the receiver's acknowledgment, the master again triggers a start condition and writes the device address, but this time the RW bit is a logic high to initiate the read access. Now, the master can read 1 to N bytes from the receiver, generating a not-acknowledge and a stop condition after the last byte being read.
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Figure 6: I2C random read access
If the second form, "current address" is used, an address pointer in the receiver is used to determine which register to read. This address pointer will increment after each read unless it is already pointing at register 0xFF, the highest addressable register, in which case it remains unaltered.
The initial value of this address pointer at start-up is 0xFF, so by default all current address reads will repeatedly read register 0xFF and receive the next byte of message data (or 0xFF if no message data is waiting).
Figure 7: I2C current address read access
3.2.2.3 Write access
The receiver does not provide any write access except for writing UBX and NMEA messages to the receiver, such as configuration or aiding data. Therefore, the register set mentioned in the section
Read access is not writeable.
Following the start condition from the master, the 7-bit device address and the RW bit (which is a logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers with an acknowledge (logic low) to indicate that it is responsible for the given address.
The master can write 2 to N bytes to the receiver, generating a stop condition after the last byte being written. The number of data bytes must be at least 2 to properly distinguish from the write access to set the address counter in random read accesses.
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Figure 8: I2C write access

3.2.3 SPI interface

The u-blox D9 correction data receiver has an SPI slave interface that can be selected by setting D_SEL = 0. The SPI slave interface is shared with UART1 and I2C port, the physical pins are same. The SPI pins available are:
• SPI_MISO (TXD)
• SPI_MOSI (RXD)
• SPI_CS_N
• SPI_CLK
See more information about communication interface selection from D_SEL section.
The SPI interface is designed to allow communication to a host CPU. The interface can be operated in slave mode only.
3.2.3.1 Read access
As the register mode is not implemented for the SPI port, only the UBX/NMEA message stream is provided. This stream is accessed using the back-to-back read and write access (see section Back-
to-back read and write access below). When no data is available to be written to the receiver, MOSI
should be held logic high, i.e. all bytes written to the receiver are set to 0xFF.
To prevent the receiver from being busy parsing incoming data, the parsing process is stopped after 50 subsequent bytes containing 0xFF. The parsing process is re-enabled with the first byte not equal to 0xFF.
If the receiver has no more data to send, it sets MISO to logic high, i.e. all bytes transmitted decode to 0xFF. An efficient parser in the host will ignore all 0xFF bytes which are not part of a message and will resume data processing as soon as the first byte not equal to 0xFF is received.
3.2.3.2 Back-to-back read and write access
The receiver does not provide any write access except for writing UBX and NMEA messages to the receiver, such as configuration or aiding data. For every byte written to the receiver, a byte will
simultaneously be read from the receiver. While the master writes to MOSI, at the same time it needs to read from MISO, as any pending data will be output by the receiver with this access. The data on MISO represents the results from a current address read, returning 0xFF when no more data is
available.
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Figure 9: SPI back-to-back read/write access

3.2.4 USB interface

A single USB port is provided for host communication purposes.
The USB 2.0 FS (Full speed, 12 Mbit/s) interface can be used for host communication. Due to the hardware implementation, it may not be possible to certify the USB interface.
If the receiver executes code from internal ROM (i.e. when a valid flash firmware image is not detected), the USB behavior can differ compared to executing a firmware image from flash memory. USB host compatibility testing is thus recommended in this scenario.
USB suspend mode is not supported.
USB bus-powered mode is not supported.
It is important to connect V_USB to ground and leave data lines open when the USB interface is not used in an application.
The voltage range for V_USB is specified from 3.0 V to 3.6 V, which differs slightly from the specification for VCC.
The boot screen is retransmitted on the USB port after enumeration. However, messages generated between boot-up of the receiver and USB enumeration are not visible on the USB port.
There are additional hardware requirements if USB is to be used:
• V_USB (pin 7) requires 1 uF capacitor mounted adjacent to the pin to ensure correct V_USB voltage detection
• The V_USB (Pin 7) voltage should be sourced from an LDO enabled by the module VCC and supplied from the USB host.
• A pull down resistor is required on the output of this V_USB LDO
• Pin 5 is USB_DM. Pin 6 is USB_DP.
• Apply USB_DM and USB_DP series resistors; typically 27 Ω
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