Abstract
This document describes the features and the system integration of TOBY-L2 and MPCI-L2 series
multi-mode cellular modules. These modules are a complete and cost efficient LTE/3G/2G solution
offering up to 150 Mb/s download and 50 Mb/s upload data rates, covering up to six LTE bands, up
to five WCDMA/DC-HSPA+ bands and up to four GSM/EGPRS bands in the compact TOBY LGA form
factor of TOBY-L2 modules or in the industry standard PCI Express Mini Card form factor of MPCI-L2
modules.
www.u-blox.com
UBX-13004618 - R28
TOBY-L2 and MPCI-L2 series
LTE/DC-HSPA+/EGPRS modules
System Integration Manual
TOBY-L2 and MPCI-L2 series - System Integration Manual
Title
TOBY-L2 and MPCI-L2 series
Subtitle
LTE/DC-HSPA+/EGPRS modules
Document type
System Integration Manual
Document number
UBX-13004618
Revision and date
R28
12-Apr-2019
Disclosure Restriction
Product status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Production Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Document contains the final product specification.
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document.
Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the
express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents,
visit www.u-blox.com.
Copyright © u-blox AG.
Document Information
UBX-13004618 - R28 Page 2 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Product name
Type number
Modem version
Application version
PCN reference
Product status
TOBY-L200
TOBY-L200-00S-00
09.71
A01.15
UBX-14044437
Obsolete
TOBY-L200-00S-01
09.71
A01.30
UBX-16026448
Obsolete
TOBY-L200-02S-00
15.90
A01.00
UBX-15029946
Obsolete
TOBY-L200-02S-01
15.90
A01.10
UBX-16031212
End of Life
TOBY-L200-03A-01
16.19
A01.02
UBX-19004188
Initial Production
TOBY-L200-03S-00
15.90
A01.50
UBX-17022983
End of Life
TOBY-L200-03S-01
16.19
A01.02
UBX-19000820
Initial Production
TOBY-L201
TOBY-L201-01S-00
09.93
A01.07
UBX-18012849
End of Life
TOBY-L201-02S-00
(for AT&T): 09.93
(for AT&T): A02.50
UBX-17013932
End of Life
(for VZW): 09.94
(for VZW): A01.02
UBX-17013932
End of Life
TOBY-L201-02S-01
(for AT&T): 20.03
(for AT&T): A01.02
UBX-19000820
Initial Production
(for VZW): 20.03
(for VZW): A01.02
UBX-19000820
Initial Production
TOBY-L210
TOBY-L210-00S-00
09.71
A01.15
UBX-14044437
Obsolete
TOBY-L210-02S-00
15.63
A01.03
UBX-15029946
Obsolete
TOBY-L210-02S-01
15.63
A01.10
UBX-16031212
End of Life
TOBY-L210-03A-00
15.63
A01.60
UBX-18010749
End of Life
TOBY-L210-03A-01
16.19
A01.02
UBX-19012118
Initial Production
TOBY-L210-03S-00
15.63
A01.50
UBX-17022983
End of Life
TOBY-L210-03S-01
16.19
A01.02
UBX-19000820
Initial Production
TOBY-L210-60S-00
09.94
A01.00
UBX-15021694
Obsolete
TOBY-L210-60S-01
09.94
A01.01
UBX-16005471
Obsolete
TOBY-L210-62S-00
16.05
A01.02
UBX-17003573
Initial Production
TOBY-L220
TOBY-L220-02S-00
15.93
A01.00
UBX-16025501
Mass Production
TOBY-L220-62S-00
16.04
A01.00
UBX-17013073
Mass Production
TOBY-L280
TOBY-L280-02S-00
15.63
A01.03
UBX-15029946
Obsolete
TOBY-L280-02S-01
15.63
A01.10
UBX-16031212
End of Life
TOBY-L280-03A-01
16.19
A01.02
UBX-19004188
Initial Production
TOBY-L280-03S-00
15.63
A01.50
UBX-17022983
End of Life
TOBY-L280-03S-01
16.19
A01.02
UBX-19000820
Initial Production
MPCI-L200
MPCI-L200-00S-00
09.71
A01.15
UBX-14044437
Obsolete
MPCI-L200-00S-01
09.71
A01.30
UBX-16026448
Obsolete
MPCI-L200-02S-00
15.90
A01.00
UBX-15029946
Obsolete
MPCI-L200-02S-01
15.90
A01.10
UBX-16031212
End of Life
MPCI-L200-03S-00
15.90
A01.50
UBX-17022983
Mass Production
MPCI-L201
MPCI-L201-01S-00
09.93
A01.07
UBX-18012849
End of Life
MPCI-L201-02S-00
(for AT&T): 09.93
(for AT&T): A02.50
UBX-17013932
End of Life
(for VZW): 09.94
(for VZW): A01.02
UBX-17013932
End of Life
MPCI-L201-02S-01
(for AT&T): 20.03
(for AT&T): A01.02
UBX-19000820
Initial Production
(for VZW): 20.03
(for VZW): A01.02
UBX-19000820
Initial Production
MPCI-L210
MPCI-L210-00S-00
09.71
A01.15
UBX-14044437
Obsolete
MPCI-L210-02S-00
15.63
A01.03
UBX-15029946
Obsolete
MPCI-L210-02S-01
15.63
A01.10
UBX-16031212
End of Life
MPCI-L210-03S-00
15.63
A01.50
UBX-17022983
Mass Production
MPCI-L210-60S-00
09.94
A01.00
UBX-15021694
Obsolete
MPCI-L210-60S-01
09.94
A01.01
UBX-16005471
Mass Production
MPCI-L220
MPCI-L220-02S-00
15.93
A01.00
UBX-16025501
Initial Production
MPCI-L220-62S-00
16.04
A01.00
UBX-17013073
Initial Production
MPCI-L280
MPCI-L280-02S-00
15.63
A01.03
UBX-15029946
Obsolete
MPCI-L280-02S-01
15.63
A01.10
UBX-16031212
End of Life
MPCI-L280-03S-00
15.63
A01.50
UBX-17022983
Mass Production
This document applies to the following products:
UBX-13004618 - R28 Page 3 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Contents
Document Information ................................................................................................................................ 2
Contents .......................................................................................................................................................... 4
1 System description ............................................................................................................................... 8
1.1 Overview ........................................................................................................................................................ 8
1.2 Architecture ................................................................................................................................................ 11
1.2.1 Internal blocks .................................................................................................................................... 12
1.3 Pin-out ......................................................................................................................................................... 13
1.3.1 TOBY-L2 series pin assignment .................................................................................................... 13
1.3.2 MPCI-L2 series pin assignment ...................................................................................................... 17
1.4 Operating modes ....................................................................................................................................... 19
1.5 Supply interfaces ....................................................................................................................................... 21
1.5.1 Module supply input (VCC or 3.3Vaux) .......................................................................................... 21
1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 28
1.5.3 Generic digital interfaces supply output (V_INT) ....................................................................... 29
1.6 System function interfaces ....................................................................................................................30
1.6.1 Module power-on ..............................................................................................................................30
1.6.2 Module power-off .............................................................................................................................. 32
1.6.3 Module reset ...................................................................................................................................... 34
1.6.4 Module configuration selection by host processor .................................................................... 34
1.7 Antenna interface ..................................................................................................................................... 35
1.7.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 35
1.7.2 Antenna detection interface (ANT_DET) ..................................................................................... 38
1.8 SIM interface .............................................................................................................................................. 38
1.8.1 SIM interface ..................................................................................................................................... 38
1.8.2 SIM detection interface ................................................................................................................... 38
1.9 Data communication interfaces ............................................................................................................ 39
1.9.1 Universal Serial Bus (USB) .............................................................................................................. 39
1.9.2 Asynchronous serial interface (UART) ......................................................................................... 43
1.9.3 DDC (I2C) interface ............................................................................................................................ 54
1.9.4 Secure Digital Input Output interface (SDIO) ............................................................................. 55
1.10 Audio ............................................................................................................................................................ 55
1.10.1 Digital audio over I2S interface ....................................................................................................... 55
1.11 General Purpose Input/Output ............................................................................................................... 57
1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#) ................................................................ 58
1.13 Reserved pins (RSVD) .............................................................................................................................. 58
1.14 Not connected pins (NC) .......................................................................................................................... 58
1.15 System features ........................................................................................................................................ 59
1.15.1 Network indication ........................................................................................................................... 59
1.15.2 Antenna supervisor .......................................................................................................................... 59
1.15.3 Jamming detection .......................................................................................................................... 59
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1.15.4 IP modes of operation ...................................................................................................................... 60
1.15.5 Dual stack Ipv4/Ipv6 ......................................................................................................................... 60
1.15.6 TCP/IP and UDP/IP ............................................................................................................................ 60
1.15.7 FTP ....................................................................................................................................................... 60
1.15.8 HTTP .................................................................................................................................................... 61
1.15.9 SSL / TLS ............................................................................................................................................ 61
1.15.10 Bearer Independent Protocol .......................................................................................................... 61
1.15.11 Wi-Fi integration ............................................................................................................................... 61
1.15.12 Firmware update Over AT (FOAT) ................................................................................................. 62
1.15.13 Firmware update Over The Air (FOTA) ......................................................................................... 62
1.15.14 Smart temperature management ................................................................................................ 62
1.15.15 SIM Access Profile (SAP) ................................................................................................................. 65
1.15.16 Power saving ...................................................................................................................................... 67
2 Design-in ................................................................................................................................................ 68
2.1 Overview ...................................................................................................................................................... 68
2.2 Supply interfaces ...................................................................................................................................... 69
2.2.1 Module supply (VCC or 3.3Vaux) ................................................................................................... 69
2.2.2 RTC supply output (V_BCKP) ......................................................................................................... 81
2.2.3 Generic digital interfaces supply output (V_INT) ....................................................................... 82
2.3 System functions interfaces .................................................................................................................. 83
2.3.1 Module power-on (PWR_ON) .......................................................................................................... 83
2.3.2 Module reset (RESET_N or PERST#) ............................................................................................ 84
2.3.3 Module configuration selection by host processor .................................................................... 85
2.4 Antenna interface ..................................................................................................................................... 86
2.4.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 86
2.4.2 Antenna detection interface (ANT_DET) ..................................................................................... 94
2.5 SIM interface .............................................................................................................................................. 96
2.6 Data communication interfaces .......................................................................................................... 103
2.6.1 Universal Serial Bus (USB) ............................................................................................................ 103
2.6.2 Asynchronous serial interface (UART) ....................................................................................... 105
2.6.3 DDC (I2C) interface .......................................................................................................................... 109
2.6.4 Secure Digital Input Output interface (SDIO) ............................................................................ 110
2.7 Audio interface ......................................................................................................................................... 112
2.7.1 Digital audio interface ..................................................................................................................... 112
2.8 General Purpose Input/Output .............................................................................................................. 116
2.9 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#) ............................................................... 117
2.10 Reserved pins (RSVD) ............................................................................................................................. 118
2.11 Module placement ................................................................................................................................... 119
2.12 TOBY-L2 series module footprint and paste mask ......................................................................... 120
2.13 MPCI-L2 series module installation ..................................................................................................... 121
2.14 Thermal guidelines ................................................................................................................................. 122
2.15 ESD guidelines ......................................................................................................................................... 124
2.15.1 ESD immunity test overview ........................................................................................................ 124
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TOBY-L2 and MPCI-L2 series - System Integration Manual
2.15.2 ESD immunity test of TOBY-L2 and MPCI-L2 reference design .......................................... 125
2.15.3 ESD application circuits ................................................................................................................ 125
2.16 Schematic for TOBY-L2 and MPCI-L2 module integration ............................................................ 128
2.16.1 Schematic for TOBY-L2 module “00” product version ........................................................... 128
2.16.2 Schematic for TOBY-L2 module “01” or “60” product versions ............................................. 129
2.16.3 Schematic for TOBY-L2 module “02”, “03” or “62” product versions .................................. 130
2.16.4 Schematic for MPCI-L2 series ...................................................................................................... 131
2.17 Design-in checklist .................................................................................................................................. 132
2.17.1 Schematic checklist ....................................................................................................................... 132
2.17.2 Layout checklist .............................................................................................................................. 133
2.17.3 Antenna checklist ........................................................................................................................... 134
3 Handling and soldering .................................................................................................................... 135
3.1 Packaging, shipping, storage and moisture preconditioning ........................................................ 135
3.2 Handling .................................................................................................................................................... 135
3.3 Soldering ................................................................................................................................................... 136
3.3.1 Soldering paste ............................................................................................................................... 136
3.3.2 Reflow soldering .............................................................................................................................. 136
3.3.3 Optical inspection ........................................................................................................................... 137
3.3.4 Cleaning ............................................................................................................................................ 137
3.3.5 Repeated reflow soldering ............................................................................................................ 138
3.3.6 Wave soldering ................................................................................................................................ 138
3.3.7 Hand soldering ................................................................................................................................ 138
3.3.8 Rework .............................................................................................................................................. 138
3.3.9 Conformal coating .......................................................................................................................... 138
3.3.10 Casting .............................................................................................................................................. 138
3.3.11 Grounding metal covers ................................................................................................................ 139
3.3.12 Use of ultrasonic processes ......................................................................................................... 139
4 Approvals ............................................................................................................................................. 140
4.1 Product certification approval overview ............................................................................................. 140
4.2 US Federal Communications Commission notice ............................................................................. 141
4.2.1 Safety warnings review the structure ......................................................................................... 141
4.2.2 Declaration of Conformity .............................................................................................................. 141
4.2.3 Modifications ................................................................................................................................... 142
4.3 Innovation, Science, Economic Development Canada notice ........................................................ 143
4.3.1 Declaration of Conformity ............................................................................................................. 143
4.3.2 Modifications ................................................................................................................................... 143
4.4 Brazilian Anatel certification ................................................................................................................ 145
4.5 European Conformance CE mark ........................................................................................................ 146
4.6 Australian Regulatory Compliance Mark ........................................................................................... 147
4.7 Taiwanese NCC certification ................................................................................................................ 147
4.8 Japanese Giteki certification ............................................................................................................... 148
5 Product testing .................................................................................................................................. 149
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5.1 u-blox in-series production test ........................................................................................................... 149
5.2 Test parameters for OEM manufacturer ........................................................................................... 150
5.2.1 “Go/No go” tests for integrated devices .................................................................................... 150
5.2.2 RF functional tests ......................................................................................................................... 150
Appendix ...................................................................................................................................................... 152
A Migration between TOBY-L1 and TOBY-L2 ............................................................................... 152
A.1 Overview .................................................................................................................................................... 152
A.2 Pin-out comparison between TOBY-L1 and TOBY-L2 ..................................................................... 154
A.3 Schematic for TOBY-L1 and TOBY-L2 integration ........................................................................... 157
B Glossary ................................................................................................................................................ 158
Related documents .................................................................................................................................. 161
Revision history ......................................................................................................................................... 162
Contact ......................................................................................................................................................... 164
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TOBY-L2 and MPCI-L2 series - System Integration Manual
1 System description
1.1 Overview
TOBY-L2 and MPCI-L2 series comprises LTE/3G/2G multi-mode modules supporting up to six LTE
bands, up to five UMTS/DC-HSPA+ bands and up to four GSM/(E)GPRS bands for voice and/or data
transmission as following:
TOBY-L200, TOBY-L201, MPCI-L200 and MPCI-L201 are designed primarily for operation in
America
TOBY-L210 and MPCI-L210 are designed primarily for operation in Europe, Asia and other
countries
TOBY-L220 and MPCI-L220 are designed primarily for operation in Japan
TOBY-L280 and MPCI-L280 are designed primarily for operation in Asia and Oceania
TOBY-L2 and MPCI-L2 series are designed in two different form-factors suitable for applications as
following:
TOBY-L2 modules are designed in the small TOBY 152-pin Land Grid Array form-factor (35.6 x 24.8
mm), easy to integrate in compact designs and form-factor compatible with the u-blox cellular
module families: this allows customers to take the maximum advantage of their hardware and
software investments, and provides very short time-to-market.
The modules are the perfect choice for consumer fixed-wireless terminals, mobile routers and
gateways, and applications requiring video streaming. They are also optimally suited for industrial
(M2M) applications, such as remote access to video cameras, digital signage, telehealth, and
security and surveillance systems
MPCI-L2 modules are designed in the industry standard PCI Express Full-Mini Card form-factor
(51 x 30 mm) easy to integrate into industrial and consumer applications and also ideal for
manufacturing of small series.
Typical applications are industrial computing, ruggedized terminals, video communications,
wireless routers, alarm panels and surveillance, digital signage and payment systems.
With LTE Category 4 data rates at up to 150 Mb/s (down-link) and 50 Mb/s (up-link), the TOBY-L2 and
MPCI-L2 series modules are ideal for applications requiring the highest data-rates and high-speed
internet access.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Module
LTE
UMTS
GSM
Interfaces
Audio
Features
Grade
LTE FDD category Bands
HSDPA category HSUPA category Bands
GPRS/EDGE multi
-slot class
Bands
UART USB 2.0 SDIO (Master) DDC (I
2
C)
GPIOs Analog audio Digital audio Network indication Antenna supervisor MIMO 2x2 / Rx Diversity
Embedded TCP/UDP stack Embedded HTTP,FTP FOTA Dual stack IPv4/IPv6 Standard Professional Automotive
TOBY-L200
4
2,4,5
7,17
24
6
1,2,4
5,8
12
Quad
♦ ● ♦ ♦ ♦ ♦ ● ♦ ● ♦ ♦ ♦
● ●
●
TOBY-L201
4
2,4,5
13,17
24 6 2,5
● ● ♦ ♦
● ♦ ● ● ● ● ● ●
TOBY-L210
4
1,3,5
7,8,20
24
6
1,2
5,8
12
Quad
♦
●
■ ■ ■ ■ ● ■ ● ■ ■ ■
● ● ● TOBY-L220 1
4
1,3,5
6,8,19
24
6
1,6
8,19
● ● ● ● ●
▲
● ● ● ● ● ● ● ●
TOBY-L280
4
1,3,5
7,8,28
24
6
1,2
5,8
12
Quad
● ● ● ● ● ● ● ● ● ● ● ●
● ●
●
MPCI-L200
4
2,4,5
7,17
24
6
1,2,4
5,8
12
Quad
● ● ● ♦ ♦ ♦
● ● MPCI-L201
4
2,4,5
13,17
24 6 2,5
● ● ● ● ● ●
● ●
MPCI-L210
4
1,3,5
7,8,20
24
6
1,2
5,8
12
Quad
● ●
●
■ ■ ■
● ●
MPCI-L2201
4
1,3,5
6,8,19
24
6
1,6
8,19
● ● ● ● ● ●
● ● MPCI-L280
4
1,3,5
7,8,28
24
6
1,2
5,8
12
Quad
● ● ● ● ● ●
● ●
● = supported by all product versions
♦ = supported by all product versions except versions “00”,”01”
■ = supported by all product versions except versions “00”,”60”
▲= supported by all product versions except versions “62”
1
2
Table 1 summarizes the TOBY-L2 and MPCI-L2 series main features and interfaces.
Table 1: TOBY-L2 and MPCI-L2 series main features summary
TOBY-L2 modules provide Circuit-Switched-Fall-Back (CSFB)2 audio capability.
Table 2 reports a summary of cellular radio access technologies characteristics and features of the
modules.
TOBY-L220-62S and MPCI-L220-62S product versions do not support UMTS Radio Access Technology
Not supported by “00”, “01”, “60”, TOBY-L201-02S and TOBY-L220-62S product versions.
UBX-13004618 - R28 System description Page 9 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
4G LTE
3G UMTS/HSDPA/HSUPA
2G GSM/GPRS/EDGE
3GPP Release 9
Long Term Evolution (LTE)
Evolved UTRA (E-UTRA)
Frequency Division Duplex (FDD)
DL Multi-Input Multi-Output (MIMO) 2x2
3GPP Release 8
Dual-Cell HS Packet Access (DC-HSPA+)
UMTS Terrestrial Radio Access (UTRA)
Frequency Division Duplex (FDD)
DL Rx diversity
3GPP Release 8
Enhanced Data rate GSM Evolution (EDGE)
GSM EGPRS Radio Access (GERA)
Time Division Multiple Access (TDMA)
DL Advanced Rx Performance Phase 1
Band support3:
TOBY-L200 / MPCI-L200:
o Band 17 (700 MHz)
o Band 5 (850 MHz)
o Band 4 (AWS, i.e. 1700 MHz)
o Band 2 (1900 MHz)
o Band 7 (2600 MHz)
TOBY-L201 / MPCI-L201:
o Band 17 (700 MHz)
o Band 13 (750 MHz)
o Band 5 (850 MHz)
o Band 4 (AWS, i.e. 1700 MHz)
o Band 2 (1900 MHz)
TOBY-L210 / MPCI-L210:
o Band 20 (800 MHz)
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 3 (1800 MHz)
o Band 1 (2100 MHz)
o Band 7 (2600 MHz)
TOBY-L220 / MPCI-L220:
o Band 19 (850 MHz)
o Band 6 (850 MHz)
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 3 (1800 MHz)
o Band 1 (2100 MHz)
TOBY-L280 / MPCI-L280:
o Band 28 (750 MHz)
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 3 (1800 MHz)
o Band 1 (2100 MHz)
o Band 7 (2600 MHz)
Band support:
TOBY-L200 / MPCI-L200:
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 4 (AWS, i.e. 1700 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)
TOBY-L201 / MPCI-L201:
o Band 5 (850 MHz)
o Band 2 (1900 MHz)
TOBY-L210 / MPCI-L210:
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)
TOBY-L2204 / MPCI-L2204:
o Band 19 (850 MHz)
o Band 6 (850 MHz)
o Band 8 (900 MHz)
o Band 1 (2100 MHz)
TOBY-L280 / MPCI-L280:
o Band 5 (850 MHz)
o Band 8 (900 MHz)
o Band 2 (1900 MHz)
o Band 1 (2100 MHz)
Band support
TOBY-L200 / MPCI-L200:
o GSM 850 MHz
o E-GSM 900 MHz
o DCS 1800 MHz
o PCS 1900 MHz
TOBY-L210 / MPCI-L210:
o GSM 850 MHz
o E-GSM 900 MHz
o DCS 1800 MHz
o PCS 1900 MHz
TOBY-L280 / MPCI-L280:
o GSM 850 MHz
o E-GSM 900 MHz
o DCS 1800 MHz
o PCS 1900 MHz
LTE Power Class
Class 3 (23 dBm)
for LTE mode
WCDMA/HSDPA/HSUPA Power Class
Class 3 (24 dBm)
for UMTS/HSDPA/HSUPA mode
GSM/GPRS (GMSK) Power Class
Class 4 (33 dBm) in GSM/E-GSM bands
Class 1 (30 dBm) in DCS/PCS bands
EDGE (8-PSK) Power Class
Class E2 (27 dBm) in GSM/E-GSM bands
Class E2 (26 dBm) in DCS/PCS bands
Data rate
LTE category 4:
up to 150 Mb/s DL, 50 Mb/s UL
Data rate
xxxx-L200 / xxxx-L201:
o HSDPA cat.14, up to 21 Mb/s DL5
o HSUPA cat.6, up to 5.6 Mb/s UL
xxxx-L210 / xxxx-L220 / xxxx-L280:
o HSDPA cat.24, up to 42 Mb/s DL
o HSUPA cat.6, up to 5.6 Mb/s UL
Data rate6
GPRS multi-slot class 127, CS1-CS4,
up to 85.6 kb/s DL/UL
EDGE multi-slot class 127, MCS1-MCS9
up to 236.8 kb/s DL/UL
3
4
5
6
7
Table 2: TOBY-L2 and MPCI-L2 series LTE, 3G and 2G characteristics summary
The modules support all E-UTRA channel bandwidths for each operating band according to 3GPP TS 36.521-1 [23]
TOBY-L220-62S and MPCI-L220-62S product versions do not support 3G Radio Access Technology
HSDPA category 24 capable
GPRS/EDGE multi-slot class determines the number of timeslots available for upload and download and thus the speed at
which data can be transmitted and received, with higher classes typically allowing faster data transfer rates.
GPRS/EDGE multi-slot class 12 implies a maximum of 4 slots in Down-Link and 4 slots in Up-Link with 5 slots in total.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Cellular
Base-band
Processor
Memory
Power Management Unit
26 MHz
32.768 kHz
ANT1
RF
Transceiver
ANT2
V_INT (I/O)
V_BCKP (RTC)
VCC (Supply)
SIM
USB
GPIO
Power On
External Reset
PAs
LNAsFilters
Filter
s
Duplexer
Filters
PAs
LNAsFilter
s
Filter
s
Duplexer
Filters
LNAsFilter
s
Filters
LNAsFiltersFilter
s
Switch
Switch
DDC(I2C)
SDIO
UART
Digital audio (I2S)
ANT_DET
Host Select
ANT1
SIM
USB
W_DISABLE#
TOBY-L2
series
Signal
Conditioning
ANT2
PERST#
LED_WWAN#
U.FL
U.FL
3.3Vaux (Supply)
Boost
Converter
VCC
1.2 Architecture
Figure 1 summarizes the internal architecture of TOBY-L2 series modules.
Figure 1: TOBY-L2 series block diagram
As described in the Figure 2, each MPCI-L2 series module integrates one TOBY-L2 series module:
The MPCI-L200 integrates a TOBY-L200 module
The MPCI-L201 integrates a TOBY-L201 module
The MPCI-L210 integrates a TOBY-L210 module
The MPCI-L220 integrates a TOBY-L220 module
The MPCI-L280 integrates a TOBY-L280 module
The TOBY-L2 module represents the core of the device, providing the related LTE/3G/2G modem and
processing functionalities. Additional signal conditioning circuitry is implemented for PCI Express
Mini Card compliance, and two UF.L connectors are available for easy antenna integration.
Figure 2: MPCI-L2 series block diagram
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TOBY-L2 and MPCI-L2 series - System Integration Manual
1.2.1 Internal blocks
As described in Figure 2, each MPCI-L2 series module integrates one TOBY-L2 series module, which
consists of the following internal sections: RF, baseband and power management.
RF section
The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF
switches.
Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port
(ANT1) of the module via power amplifier (PA), SAW band pass filters band, specific duplexer and
antenna switch.
Dual receiving paths are implemented according to LTE Down-Link MIMO 2 x 2 and 3G Receiver
Diversity radio technologies supported by the modules as LTE category 4 and HSDPA category 24
User Equipments: incoming signals are received through the primary (ANT1) and the secondary
(ANT2) antenna input ports which are connected to the RF transceiver via specific antenna switch,
diplexer, duplexer, LNA, SAW band pass filters.
RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx,
down-conversion and demodulation of the dual RF signals for Rx. The RF transceiver contains:
o Automatically gain controlled direct conversion Zero-IF receiver,
o Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM, 64-QAM,
o Fractional-N Sigma-Delta RF synthesizer,
o VCO.
Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx
path
Low Noise Amplifiers (LNA) enhance the received sensitivity
SAW duplexers separate the Tx and Rx signal paths and provide RF filtering
SAW band pass filters enhance the rejection of out-of-band signals
26 MHz crystal oscillator generates the clock reference in active-mode or connected-mode.
Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
A mixed signal ASIC, which integrates
o Microprocessor for control functions
o DSP core for LTE/3G/2G Layer 1 and digital processing of Rx and Tx signal paths
o Memory interface controller
o Dedicated peripheral blocks for control of the USB, SIM and GPIO digital interfaces
o Analog front end interfaces to RF transceiver ASIC
Memory system, which includes NAND flash and LPDDR
Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
Voltage sources for external use: V_BCKP and V_INT (not available on MPCI-L2 series modules)
Hardware power on
Hardware reset
Low power idle-mode support
32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can
be set by enable power saving configuration using the AT+UPSV command.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Function
Pin name
Pin No
I/O
Description
Remarks
Power
VCC
70,71,72
I
Module supply input
VCC pins are internally connected each other.
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for functional description/ requirements
See section 2.2.1 for external circuit design-in.
GND
2, 30, 32,
44, 46, 69,
73, 74, 76,
78, 79, 80,
82, 83, 85,
86, 88-90,
92-152
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_BCKP
3
I/O
RTC supply
input/output
V_BCKP = 3.0 V (typical) generated by internal regulator
when valid VCC supply is present.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
V_INT
5 O Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator
when the module is switched on.
Test-Point for diagnostic access is recommended.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.
System
PWR_ON
20 I Power-on input
Internal active pull-up to the VCC enabled.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
23 I External reset input
Internal active pull-up to the VCC enabled.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
HOST_SELECT0
26 I Selection of module
configuration by the
host processor
Not supported by all the product versions.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
HOST_SELECT1
62 I Selection of module
configuration by the
host processor
Not supported by all the product versions.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
Antennas
ANT1
81
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects RF performance and application
device compliance with required certification schemes.
See section 1.7 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT2
87 I Secondary antenna
Rx only for MIMO 2x2 and Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects RF performance and application
device compliance with required certification schemes.
See section 1.7 for functional description / requirements
See section 2.4 for external circuit design-in.
ANT_DET
75 I Antenna detection
Not supported by “00”, “01”, “60” product versions.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
1.3 Pin-out
1.3.1 TOBY-L2 series pin assignment
Table 3 lists the pin-out of the TOBY-L2 series modules, with pins grouped by function.
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Function
Pin name
Pin No
I/O
Description
Remarks
SIM
VSIM
59 O SIM supply output
VSIM = 1.8 V / 3 V output as per connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
57
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
56 O SIM clock
3.43 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
58 O SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
USB
VUSB_DET
4 I USB detect input
Leave unconnected: VUSB_DET functionality is not
supported.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_D-
27
I/O
USB Data Line D-
USB interface for AT and data communication, FOAT,
FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and series resistors as
required by USB 2.0 specifications [7] are part of the
USB pad driver and need not be provided externally.
If the USB interface is not used by the Application
Processor, Test-Point for diagnostic / FW update
access is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_D+
28
I/O
USB Data Line D+
USB interface for AT and data communication, FOAT,
FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and series resistors as
required by the USB 2.0 specifications [7] are part of the
USB pad driver and need not be provided externally.
If the USB interface is not used by the Application
Processor, Test-Point for diagnostic / FW update access
is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Function
Pin name
Pin No
I/O
Description
Remarks
UART
RXD
17 O UART data output
Not supported by “00” product versions.
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT and data communication, FOAT, diagnostic.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD
16 I UART data input
Not supported by “00” product versions.
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT and data communication, FOAT, diagnostic.
Internal active pull-up to V_INT.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
CTS
15 O UART clear to send
output
Not supported by “00” product versions.
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
RTS
14 I UART ready to send
input
Not supported by “00” product versions.
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
DSR
10
O /
I/O
UART data set
ready output / GPIO
UART DSR not supported by “00” product versions;
GPIO not supported by “00”, “01”, “60” versions.
1.8 V, Circuit 107 in ITU-T V.24, configurable as GPIO.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 and 1.11 for functional description.
See section 2.6.2 and 2.8 for external circuit design-in.
RI
11
O /
I/O
UART ring indicator
output / GPIO
RI not supported by “00” product versions;
GPIO not supported by “00”, “01”, “60” versions.
1.8 V, Circuit 125 in ITU-T V.24, configurable as GPIO.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 and 1.11 for functional description.
See section 2.6.2 and 2.8 for external circuit design-in.
DTR
13
I /
I/O
UART data terminal
ready input / GPIO
UART DTR not supported by “00” product versions;
GPIO not supported by “00”, “01”, “60” versions.
1.8 V, Circuit 108/2 in ITU-T V.24, configurable as GPIO.
Internal active pull-up to V_INT when configured as DTR
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 and 1.11 for functional description.
See section 2.6.2 and 2.8 for external circuit design-in.
DCD
12
O /
I/O
UART data carrier
detect output / GPIO
UART DCD not supported by “00” product versions;
GPIO not supported by “00”, “01”, “60” versions.
1.8 V, Circuit 109 in ITU-T V.24, configurable as GPIO.
Test-Point and series 0 recommended for diagnostic.
See section 1.9.2 and 1.11 for functional description.
See section 2.6.2 and 2.8 for external circuit design-in.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Function
Pin name
Pin No
I/O
Description
Remarks
DDC
SCL
54 O I2C bus clock line
Not supported by versions ‘00’, ‘01’, ‘60’, TOBY-L201-02S.
1.8 V open drain, to communicate with I2C-slave devices.
External pull-up required.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SDA
55
I/O
I2C bus data line
Not supported by versions ‘00’, ‘01’, ‘60’, TOBY-L201-02S.
1.8 V open drain, to communicate with I2C-slave devices.
External pull-up required.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SDIO
SDIO_D0
66
I/O
SDIO serial data [0]
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D1
68
I/O
SDIO serial data [1]
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D2
63
I/O
SDIO serial data [2]
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D3
67
I/O
SDIO serial data [3]
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CLK
64 O SDIO serial clock
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CMD
65
I/O
SDIO command
Not supported by “00”, “01”, “60” product versions.
Interface for communication with u-blox Wi-Fi module.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
Audio
I2S_TXD
51
O /
I/O
I2S transmit data /
GPIO
I2S not supported by vers.‘00’,‘01’,‘60’,‘L201-02’,‘L220-62’
GPIO not supported by versions ‘00’, ‘01’, ‘60’.
I2S data output, alternatively configurable as GPIO.
See sections 1.10 and 1.11 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_RXD
53
I /
I/O
I2S receive data /
GPIO
I2S not supported by vers.‘00’,‘01’,‘60’,‘L201-02’,‘L220-62’
GPIO not supported by versions ‘00’, ‘01’, ‘60’.
I2S data input, alternatively configurable as GPIO.
See sections 1.10 and 1.11 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_CLK
52
I/O /
I/O
I2S clock /
GPIO
I2S not supported by vers.‘00’,‘01’,‘60’,‘L201-02’,‘L220-62’
GPIO not supported by versions ‘00’, ‘01’, ‘60’.
I2S serial clock, alternatively configurable as GPIO.
See sections 1.10 and 1.11 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_WA
50
I/O /
I/O
I2S word alignment /
GPIO
I2S not supported by vers.‘00’,‘01’,‘60’,‘L201-02’,‘L220-62’
GPIO not supported by versions ‘00’, ‘01’, ‘60’.
I2S word alignment, alternatively configurable as GPIO.
See sections 1.10 and 1.11 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
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Function
Pin name
Pin No
I/O
Description
Remarks
GPIO
GPIO1
21
I/O
GPIO
Not supported by “00”, “01”, “60” product versions,
providing WWAN status indication on GPIO1 pin.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
22
I/O
GPIO
Not supported by “00”, “01”, “60” product versions.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
Not supported by “00”, “01”, “60” product versions.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
Not supported by “00”, “01”, “60” product versions.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
60
I/O
GPIO
Not supported by “00”, “01”, “60” product versions.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO6
61
I/O
GPIO
Not supported by “00”, “01”, “60” product versions.
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
6
N/A
Reserved pin
This pin must be connected to ground.
See section 2.10
RSVD
1, 7-9, 18,
19, 29, 31,
33-43, 45,
47-49, 77,
84, 91
N/A
Reserved pin
Leave unconnected.
See section 2.10
Function
Pin name
Pin No
I/O
Description
Remarks
Power
3.3Vaux
2, 24, 39,
41, 52
I
Module supply input
3.3Vaux pins are internally connected each other.
3.3Vaux supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
4, 9, 15, 18,
21, 26, 27,
29, 34, 35,
37, 40, 43,
50
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
Auxiliary
Signals
PERST#
22 I External reset input
Internal 45 k pull-up to 3.3 V supply.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Table 3: TOBY-L2 series module pin definition, grouped by function
1.3.2 MPCI-L2 series pin assignment
Table 4 lists the pin-out of the MPCI-L2 series modules, with pins grouped by function.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Function
Pin name
Pin No
I/O
Description
Remarks
Antennas
ANT1
U.FL
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects RF performance and integrating
device compliance with applicable certification schemes.
See section 1.7 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT2
U.FL
I
Secondary antenna
Rx only for MIMO 2x2 and Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects RF performance and integrating
device compliance with applicable certification schemes.
See section 1.7 for functional description / requirements
See section 2.4 for external circuit design-in.
SIM
UIM_PWR
8 O SIM supply output
UIM_PWR = 1.8 V / 3 V automatically generated
according to the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UIM_DATA
10
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to UIM_PWR.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UIM_CLK
12 O SIM clock
3.43 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UIM_RESET
14 O SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
USB
USB_D-
36
I/O
USB Data Line D-
USB interface for AT and data communication, FOAT,
FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and series resistors as
required by the USB 2.0 specifications [7] are part of the
USB pad driver and need not be provided externally.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_D+
38
I/O
USB Data Line D+
USB interface for AT and data communication, FOAT,
FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and series resistors as
required by the USB 2.0 specifications [7] are part of the
USB pad driver and need not be provided externally.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
Specific
Signals
LED_WWAN#
42 O LED indicator
output
Open drain active low output.
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
W_DISABLE#
20 I Wireless radio
disable input
Internal 22 k pull-up to 3.3Vaux.
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
Not
Connected
NC
1, 3, 5-7, 11,
13,16,17,19,
23, 25, 28,
30-33, 4446,47-49,51
N/A
Not connected
Internally not connected.
See section 1.14 for the description.
Table 4: MPCI-L2 series module pin definition, grouped by function
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TOBY-L2 and MPCI-L2 series - System Integration Manual
General Status
Operating Mode
Definition
Power-down
Not-Powered Mode
VCC or 3.3Vaux supply not present or below operating range: module is switched off.
Power-Off Mode
VCC or 3.3Vaux supply within operating range and module is switched off.
Normal Operation
Idle-Mode
Module processor core runs with 32 kHz reference generated by the internal oscillator.
Active-Mode
Module processor core runs with 26 MHz reference generated by the internal oscillator.
Connected-Mode
RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.
Operating Mode
Description
Transition between operating modes
Not-Powered Mode
Module is switched off.
Application interfaces are not accessible.
When VCC or 3.3Vaux supply is removed, the module
enters not-powered mode.
When in not-powered mode, TOBY-L2 modules cannot be
switched on by PWR_ON, RESET_N or RTC alarm and enter
active-mode after applying VCC supply (see 1.6.1).
When in not-powered mode, MPCI-L2 modules cannot be
switched on by RTC alarm and enter active-mode after
applying 3.3Vaux supply (see 1.6.1).
Power-Off Mode
Module is switched off: normal shutdown by
an appropriate power-off event (see 1.6.2).
Application interfaces are not accessible.
MPCI-L2 modules do not support Power-Off
Mode but halt mode (see 1.6.2 and u-blox AT
Commands Manual [3], AT+CFUN=127
command).
When the module is switched off by an appropriate poweroff event (see 1.6.2), the module enters power-off mode
from active-mode.
When in power-off mode, TOBY-L2 modules can be
switched on by PWR_ON, RESET_N or an RTC alarm.
When in power-off mode, TOBY-L2 modules enter the
not-powered mode after removing VCC supply.
Idle-Mode
Module is switched on with application
interfaces temporarily disabled or
suspended: the module is temporarily not
ready to communicate with an external
device by means of the application
interfaces as configured to reduce the
current consumption.
The module enters the low power idle-mode
whenever possible if power saving is enabled
by AT+UPSV (see u-blox AT Commands
Manual [3]) reducing current consumption
(see 1.5.1.5).
With HW flow control enabled and
AT+UPSV=1 or AT+UPSV=3, the UART CTS
line indicates when the UART is enabled
(see 1.9.2.3, 1.9.2.4).
With HW flow control disabled, the UART
CTS line is fixed to ON state (see 1.9.2.3).
Power saving configuration is not enabled by
default: it can be enabled by the AT+UPSV
command (see the u-blox AT Commands
Manual [3]).
The modules automatically switch from active-mode to low
power idle-mode whenever possible if power saving is
enabled (see sections 1.5.1.5, 1.9.1.4, 1.9.2.4 and u-blox AT
Commands Manual [3], AT+UPSV).
The modules wake up from low power idle-mode to activemode in the following events:
Automatic periodic monitoring of the paging channel for
the paging block reception according to network conditions
(see 1.5.1.5)
The connected USB host forces a remote wakeup of the
module as USB device (see 1.9.1.4)
Automatic periodic enable of the UART interface to
receive / send data, with AT+UPSV=1 (see 1.9.2.4)
Data received over UART, with HW flow control disabled
and power saving enabled (see 1.9.2.4)
RTS input set ON by the host DTE, with HW flow control
disabled and AT+UPSV=2 (see 1.9.2.4)
DTR input set ON by the host DTE, with AT+UPSV=3
(see 1.9.2.4)
The connected SDIO device forces a wakeup of the
module as SDIO host (see 1.9.4)
A preset RTC alarm occurs (see u-blox AT Commands
Manual [3], AT+CALA)
1.4 Operating modes
TOBY-L2 and MPCI-L2 series modules have several operating modes. The operating modes are
defined in Table 5 and described in detail in Table 6, providing general guidelines for operation.
Table 5: TOBY-L2 and MPCI-L2 series modules operating modes definition
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Operating Mode
Description
Transition between operating modes
Active-Mode
Module is switched on with application
interfaces enabled or not suspended: the
module is ready to communicate with an
external device by means of the application
interfaces unless power saving
configuration is enabled by AT+UPSV (see
1.9.1.4, 1.9.2.4 and u-blox AT Commands
Manual [3]).
When the module is switched on by an appropriate
power-on event (see 1.6.1), the module enters active-mode
from power-off mode.
If power saving configuration is enabled by the AT+UPSV
command, the module automatically switches from active
to idle-mode whenever possible and the module wakes up
from idle to active-mode in the events listed above (see
idle-mode to active-mode transition description above).
When a RF Tx/Rx data connection is initiated or when RF
Tx/Rx is required due to a connection previously initiated,
the module switches from active to connected-mode.
Connected-Mode
RF Tx/Rx data connection is in progress.
The module is prepared to accept data
signals from an external device unless
power saving configuration is enabled by
AT+UPSV (see sections 1.9.1.4, 1.9.2.4 and
u-blox AT Commands Manual [3]).
When a data connection is initiated, the module enters
connected-mode from active-mode.
Connected-mode is suspended if Tx/Rx data is not in
progress, due to connected discontinuous reception and
fast dormancy capabilities of the module and according to
network environment settings and scenario. In such case,
the module automatically switches from connected to
active mode and then, if power saving configuration is
enabled by the AT+UPSV command, the module
automatically switches to idle-mode whenever possible.
Vice-versa, the module wakes up from idle to active mode
and then connected mode if RF Tx/Rx is necessary.
When a data connection is terminated, the module returns
to the active-mode.
TOBY-L2 Switch ON:
• Apply VCC
MPCI-L2 Switch ON:
• Apply 3.3Vaux
If power saving is enabled
and there is no activity for
a defined time interval
Any wake up event described
in the module operating
modes summary table above
Incoming/outgoing call or
other dedicated device
network communication
No RF Tx/Rx in progress,
Call terminated,
Communication dropped
TOBY-L2
Switch ON:
• PWR_ON
• RESET_N
• RTC alarm
Not
powered
Power off
ActiveConnected Idle
TOBY-L2
Switch OFF:
• AT+CPWROFF
• RESET_N
MPCI-L2:
• AT+CFUN=127 and
then remove 3.3Vaux
TOBY-L2:
• Remove VCC
Table 6: TOBY-L2 and MPCI-L2 series modules operating modes description
Figure 3 describes the transition between the different operating modes.
Figure 3: TOBY-L2 and MPCI-L2 series modules operating modes transition
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Item
Requirement
Remark
VCC or 3.3Vaux
nominal voltage
Within VCC or 3.3Vaux normal operating range:
See “Supply/Power pins” section in the TOBY-L2
Data Sheet [1] or in the MPCI-L2 Data Sheet [2].
The modules cannot be switched on if the supply
voltage is below the normal operating range minimum
limit.
VCC or 3.3Vaux
voltage during
normal operation
Within VCC or 3.3Vaux extended operating range:
See “Supply/Power pins” section in the TOBY-L2
Data Sheet [1] or in the MPCI-L2 Data Sheet [2].
The modules may switch off if the supply voltage
drops below the extended operating range minimum
limit.
VCC or 3.3Vaux
average current
Support with adequate margin the highest
averaged current consumption value in
connected-mode conditions specified for VCC in
TOBY-L2 Data Sheet [1] or specified for 3.3Vaux in
MPCI-L2 Data Sheet [2].
The maximum average current consumption can be
greater than the specified value according to actual
antenna mismatching, temperature, supply voltage.
Sections 1.5.1.2, 1.5.1.3 and 1.5.1.4 describe current
consumption profiles in 2G, 3G, LTE connected-mode.
VCC or 3.3Vaux
peak current
Support with margin the highest peak current
consumption value in 2G connected-mode
conditions specified for VCC in TOBY-L2 Data
Sheet [1] or specified for 3.3Vaux in MPCI-L2 Data
Sheet [2].
The specified maximum peak of current consumption
occurs during GSM single transmit slot in
850/900 MHz connected-mode, in case of
mismatched antenna.
Section 1.5.1.2 describes 2G Tx peak/pulse current.
VCC or 3.3Vaux
voltage drop during
2G Tx slots
Lower than 400 mV
Supply voltage drops greater than recommended
during 2G TDMA transmission slots directly affect RF
compliance with applicable certification schemes.
Figure 5 shows supply voltage drop during 2G Tx slots
VCC or 3.3Vaux
voltage ripple
during RF Tx
Noise in the supply has to be minimized
High supply voltage ripple values during LTE/3G/2G
RF transmissions in connected-mode directly affect
RF compliance with applicable certification schemes.
Figure 5 describes supply voltage ripple during RF Tx.
VCC or 3.3Vaux
under/over-shoot
at start/end of Tx
slots
Absent or at least minimized
Supply voltage under-shoot or over-shoot at the start
or the end of 2G transmission slots directly affect RF
compliance with applicable certification schemes.
Figure 5 describes supply voltage under/over-shoot
1.5 Supply interfaces
1.5.1 Module supply input (VCC or 3.3Vaux)
TOBY-L2 modules are supplied via the three VCC pins, and MPCI-L2 modules are supplied via the five
3.3Vaux pins. All supply voltages used inside the modules are generated from the VCC or the 3.3Vaux
supply input by integrated voltage regulators, including the V_BCKP RTC supply, the V_INT generic
digital interface supply, and the VSIM or UIM_PWR SIM interface supply.
The current drawn by the TOBY-L2 and MPCI-L2 series modules through the VCC or 3.3Vaux pins can
vary by several orders of magnitude depending on radio access technology, operation mode and state.
It is important that the supply source is able to support both the high peak of current consumption
during 2G transmission at maximum RF power level (as described in the section 1.5.1.2) and the high
average current consumption during 3G and LTE transmission at maximum RF power level (as
described in the sections 1.5.1.3 and 1.5.1.4).
1.5.1.1 VCC or 3.3Vaux supply requirements
Table 7 summarizes the requirements for the VCC or 3.3Vaux modules supply. See section 2.2.1 for
suggestions to properly design a VCC or 3.3Vaux supply circuit compliant with the requirements
listed in Table 7.
⚠ The supply circuit affects the RF compliance of the device integrating TOBY-L2 and MPCI-L2
series modules with applicable required certification schemes as well as antenna circuit design.
Compliance is guaranteed if the requirements summarized in the Table 7 are fulfilled.
Table 7: Summary of VCC or 3.3Vaux modules supply requirements
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Time
[ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-120 mA
1900 mA
Peak current depends
on TX power and
actual antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
60-120 mA
10-40 mA
0.0
1.5
1.0
0.5
2.0
2.5
Time [ms]
undershoot
overshoot
ripple
drop
Voltage [mV]
3.8 V
(typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5.1.2 Current consumption in 2G connected-mode
When a GSM call is established, the VCC or 3.3Vaux module current consumption is determined by
the current consumption profile typical of the GSM transmitting and receiving bursts.
The peak of current consumption during a transmission slot is strictly dependent on the RF
transmitted power, which is regulated by the network (the current base station). The transmitted
power in the transmit slot is also the more relevant factor for determining the average current
consumption.
If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands, at the maximum
RF power level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current
consumption can reach an high peak (see the “Current consumption” section in the TOBY-L2 Data
Sheet [1] or the MPCI-L2 Data Sheet [2]) for 576.9 µs (width of the transmit slot/burst) with a
periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM
TDMA (Time Division Multiple Access).
If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current
consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output
power specifications.
During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts
and is low in the inactive unused bursts.
Figure 4 shows an example of the current consumption profile versus time in 2G single-slot mode.
Figure 4: VCC or 3.3Vaux current consumption profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)
Figure 5 illustrates VCC or 3.3Vaux voltage profile versus time during a 2G single-slot call, according
to the relative VCC or 3.3Vaux current consumption profile described in Figure 4.
Figure 5: VCC or 3.3Vaux voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Time [ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200mA
60-130mA
Peak current depends
on TX power and
actual antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
1600 mA
0.0
1.5
1.0
0.5
2.0
2.5
When a GPRS connection is established, more than one slot can be used to transmit and/or more than
one slot can be used to receive. The transmitted power depends on network conditions, which set the
peak current consumption, but following the 3GPP specifications the maximum Tx RF power is
reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as
can be in case of a 2G single-slot call.
The multi-slot transmission power can be further reduced by configuring the actual Multi-Slot Power
Reduction profile with the dedicated AT command, AT+UDCONF=40 (see the u-blox AT Commands
Manual [3]). This command is not supported by “00” and “60” product versions.
If the module transmits in GPRS class 12 in the 850 or 900 MHz bands, at the maximum RF power
control level, the current consumption can reach a quite high peak but lower than the one achievable
in 2G single-slot mode. This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a
periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to 2G
TDMA.
If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, the current consumption
figures are quite less high than the one in the low bands, due to 3GPP transmitter output power
specifications.
Figure 6 reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or
900 MHz bands, with 4 slots used to transmit and 1 slot used to receive.
Figure 6: VCC or 3.3Vaux current consumption profile during a 2G GPRS/EDGE multi-slot connection (4 TX slots, 1 RX slot)
In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current
profile, so the image shown in Figure 6, representing the current consumption profile in GPRS class
12 connected mode, is valid for the EDGE class 12 connected mode as well.
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Time
[ms]
3G frame
10 ms
(1 frame = 15 slots)
Current [mA]
Current consumption
value depends on TX power
and actual antenna load
170
mA
1 slot
666
µs
850
mA
0
300
200
100
500
400
600
700
1.5.1.3 Current consumption in 3G connected mode
During a 3G connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA).
The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a
maximum rate of 1.5 kHz.
There are no high current peaks as in the 2G connection, since transmission and reception are
continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA
implemented in the 2G case.
In the worst scenario, corresponding to a continuous transmission and reception at maximum output
power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins
is considerable (see the “Current consumption” section in TOBY-L2 Data Sheet [1] or in MPCI-L2 Data
Sheet [2]). At the lowest output RF power (approximately 0.01 µW or –50 dBm), the current drawn by
the internal power amplifier is strongly reduced. The total current drawn by the module at the VCC
pins is due to baseband processing and transceiver activity.
Figure 7 shows an example of current consumption profile of the module in 3G WCDMA/DC-HSPA+
continuous transmission mode.
Figure 7: VCC or 3.3Vaux current consumption profile versus time during a 3G connection (TX and RX continuously enabled)
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Time
[ms]
Current [mA]
Current consumption
value depends on TX power
and actual antenna load
1 Slot
1 Resource Block
(0.5 ms)
1 LTE Radio Frame
(10 ms)
0
300
200
100
500
400
600
700
1.5.1.4 Current consumption in LTE connected-mode
During an LTE connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation used in LTE radio access technology.
The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate
of power change can reach a maximum rate of 2 kHz.
The current consumption profile is similar to that in 3G radio access technology. Unlike the 2G
connection mode, which uses the TDMA mode of operation, there are no high current peaks since
transmission and reception are continuously enabled in FDD.
In the worst scenario, corresponding to a continuous transmission and reception at maximum output
power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins
is considerable (see the “Current consumption” section in TOBY-L2 Data Sheet [1] or in MPCI-L2 Data
Sheet [2]). At the lowest output RF power (approximately 0.01 µW or –50 dBm), the current drawn by
the internal power amplifier is strongly reduced and the total current drawn by the module at the VCC
pins is due to baseband processing and transceiver activity.
Figure 8 shows an example of the module current consumption profile versus time in LTE connected-
mode. Detailed current consumption values can be found in TOBY-L2 Data Sheet [1] and in MPCI-L2
Data Sheet [2].
Figure 8: VCC or 3.3Vaux current consumption profile versus time during LTE connection (TX and RX continuously enabled)
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TOBY-L2 and MPCI-L2 series - System Integration Manual
~50 ms
IDLE MODE ACTIVE MODE IDLE MODE
Active Mode
Enabled
Idle Mode
Enabled
2G case: 0.44-2.09 s
3G case: 0.61-5.09 s
LTE case: 0.27-2.51 s
IDLE MODE
~50 ms
ACTIVE MODE
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
1.5.1.5 Current consumption in cyclic idle/active mode (power saving enabled)
The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV
command (see the u-blox AT Commands Manual [3]). When power saving is enabled, the module
automatically enters the low power idle-mode whenever possible, reducing current consumption.
During low power idle-mode, the module processor runs with 32 kHz reference clock frequency.
When the power saving configuration is enabled and the module is registered or attached to a
network, the module automatically enters the low power idle-mode whenever possible, but it must
periodically monitor the paging channel of the current base station (paging block reception), in
accordance to the 2G/3G/LTE system requirements, even if connected-mode is not enabled by the
application. When the module monitors the paging channel, it wakes up to the active-mode, to enable
the reception of paging block. In between, the module switches to low power idle-mode. This is known
as discontinuous reception (DRX).
The module processor core is activated during the paging block reception, and automatically switches
its reference clock frequency from 32 kHz to the 26 MHz used in active-mode.
The time period between two paging block receptions is defined by the network. This is the paging
period parameter, fixed by the base station through broadcast channel sent to all users on the same
serving cell:
In case of 2G RAT, the paging period can vary from 470.8 ms (DRX = 2, length of 2 x 51 2G frames
= 2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms)
In case of 3G RAT, the paging period can vary from 640 ms (DRX = 6, i.e. length of 2
6
3G frames =
64 x 10 ms) up to 5120 ms (DRX = 9, length of 29 3G frames = 512 x 10 ms).
In case of LTE RAT, the paging period can vary from 320 ms (DRX = 5, i.e. length of 2
5
LTE frames
= 32 x 10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms).
Figure 9 illustrates a typical example of the module current consumption profile when power saving is
enabled. The module is registered with network, automatically enters the low power idle-mode and
periodically wakes up to active-mode to monitor the paging channel for the paging block reception.
Detailed current consumption values can be found in TOBY-L2 Data Sheet [1] and in MPCI-L2 Data
Sheet [2].
Figure 9: VCC or 3.3Vaux current consumption profile with power saving enabled and module registered with the network:
the module is in idle-mode and periodically wakes up to active-mode to monitor the paging channel for paging reception
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TOBY-L2 and MPCI-L2 series - System Integration Manual
ACTIVE MODE
2G case: 0.44-2.09 s
3G case: 0.61-5.09 s
LTE case: 0.32-2.56 s
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
1.5.1.6 Current consumption in fixed active-mode (power saving disabled)
When power saving is disabled, the module does not automatically enter the low power idle-mode
whenever possible: the module remains in active-mode. Power saving configuration is by default
disabled. It can also be disabled using the AT+UPSV command (see u-blox AT Commands Manual [3]
for detail usage).
The module processor core is activated during idle-mode, and the 26 MHz reference clock frequency
is used. It would draw more current during the paging period than that in the power saving mode.
Figure 10 illustrates a typical example of the module current consumption profile when power saving
is disabled. In such case, the module is registered with the network and while active-mode is
maintained, the receiver is periodically activated to monitor the paging channel for paging block
reception. Detailed current consumption values can be found in TOBY-L2 Data Sheet [1] and in
MPCI-L2 Data Sheet [2].
Figure 10: VCC or 3.3Vaux current consumption profile with power saving disabled and module registered with the network:
active-mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Baseband
Processor
70
VCC
71
VCC
72
VCC
3
V_BCKP
Linear
LDO
Power
Management
TOBY-L2 series
32 kHz
RTC
1.5.2 RTC supply input/output (V_BCKP)
☞ The RTC supply V_BCKP pin is not available on MPCI-L2 series modules.
The V_BCKP pin of TOBY-L2 series modules connects the supply for the Real Time Clock (RTC). A
linear LDO regulator integrated in the Power Management Unit internally generates this supply, as
shown in Figure 11, with low current capability (see the TOBY-L2 series Data Sheet [1]). The output of
this regulator is always enabled when the main module voltage supply applied to the VCC pins is within
the valid operating range.
Figure 11: TOBY-L2 series RTC supply (V_BCKP) simplified block diagram
The RTC provides the module time reference (date and time) that is used to set the wake-up interval
during the low power idle-mode periods, and is able to make available the programmable alarm
functions.
The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid
range (specified in the “Input characteristics of Supply/Power pins” table in TOBY-L2 series Data
Sheet [1]). The RTC can be supplied from an external back-up battery through the V_BCKP, when the
main module voltage supply is not applied to the VCC pins. This lets the time reference (date and time)
run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to
the module.
Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC
is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).
The RTC has very low current consumption, but is highly temperature dependent. For example,
V_BCKP current consumption at the maximum operating temperature can be higher than the typical
value at 25 °C specified in the “Input characteristics of Supply/Power pins” table in the TOBY-L2 series
Data Sheet [1].
If V_BCKP is left unconnected and the module main supply is not applied to the VCC pins, the RTC is
supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to
provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid
range (1.4 V min). This has no impact on cellular connectivity, as all the module functionalities do not
rely on date and time setting.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Baseband
Processor
70
VCC
71
VCC
72
VCC
5
V_INT
Switching
Step-Down
Power
Management
TOBY-L2 series
Digital I/O
1.5.3 Generic digital interfaces supply output (V_INT)
☞ The generic digital interfaces supply V_INT pin is not available on MPCI-L2 series modules.
The V_INT output pin of the TOBY-L2 series modules is connected to an internal 1.8 V supply with
current capability specified in the TOBY-L2 series Data Sheet [1]. This supply is internally generated
by a switching step-down regulator integrated in the Power Management Unit and it is internally used
to source the generic digital I/O interfaces of the TOBY-L2 module, as described in Figure 12. The
output of this regulator is enabled when the module is switched on and it is disabled when the module
is switched off.
Figure 12: TOBY-L2 series generic digital interfaces supply output (V_INT) simplified block diagram
The switching regulator operates in Pulse Width Modulation (PWM) mode for greater efficiency at
high output loads and it automatically switches to Pulse Frequency Modulation (PFM) power save
mode for greater efficiency at low output loads. The V_INT output voltage ripple is specified in the
TOBY-L2 series Data Sheet [1].
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Baseband
Processor
20
PWR_ON
TOBY-L2 series
VCC
Power-on
Power
Management
Power-on
50k
1.6 System function interfaces
1.6.1 Module power-on
☞ The PWR_ON input pin is not available on MPCI-L2 series modules.
When the TOBY-L2 and MPCI-L2 series modules are in the not-powered mode (switched off, i.e. the
VCC or 3.3Vaux module supply is not applied), they can be switched on as following:
Rising edge on the VCC or 3.3Vaux supply input to a valid voltage for module supply, starting from
a voltage value lower than 0.5 V, so that the module switches on applying a proper VCC or 3.3Vaux
supply within the normal operating range.
Alternately, the RESET_N or PERST# pin can be held to the low level during the VCC or 3.3Vaux
rising edge, so that the module switches on releasing the RESET_N or PERST# pin when the VCC
or 3.3Vaux module supply voltage stabilizes at its proper nominal value within the normal
operating range.
The status of the PWR_ON input pin of TOBY-L2 modules while applying the VCC module supply is
not relevant: during this phase the PWR_ON pin can be set high or low by the external circuit.
When the TOBY-L2 modules are in the power-off mode (i.e. switched off with valid VCC module supply
applied), they can be switched on as following:
Low level on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time
period.
Low level on the RESET_N pin, which is normally set high by an internal pull-up, for a valid time
period.
RTC alarm, i.e. pre-programmed alarm by AT+CALA command (see u-blox AT Commands
Manual [3]).
As described in Figure 13, the TOBY-L2 series PWR_ON input is equipped with an internal active
pull-up resistor to the VCC module supply: the PWR_ON input voltage thresholds are different from
the other generic digital interfaces. Detailed electrical characteristics are described in TOBY-L2 series
Data Sheet [1].
Figure 13: TOBY-L2 series PWR_ON input description
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VCC or 3.3Vaux
V_BCKP
PWR_ON
RESET_N or PERST#
V_INT
Internal Reset
System State
BB Pads State
Internal Reset → Operational
Operational
Tristate / Floating
Internal Reset
OFF
ON
0 ms
~10 ms
~20 s
Start of interface
configuration
Module interfaces
are configured
Start-up
event
~5 ms
Figure 14 shows the module power-on sequence from the not-powered mode, with following phases:
The external supply is applied to VCC or 3.3Vaux supply inputs, representing the start-up event.
PWR_ON and RESET_N or PERST# pins suddenly rise to high logic level due to internal pull-ups.
V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid value.
All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).
The internal reset signal is held low: the baseband core and all the digital pins are held in the reset
state. The reset state of all the digital pins is reported in the pin description table of TOBY-L2
Series Data Sheet [1].
When the internal reset signal is released, any digital pin is set in a proper sequence from the reset
state to the default operational configured state. The duration of this pins’ configuration phase
differs within generic digital interfaces and the USB interface due to host / device enumeration
timings (see section 1.9.1).
The module is fully ready to operate after all interfaces are configured.
Figure 14: TOBY-L2 and MPCI-L2 series power-on sequence description
The greeting text can be activated by means of +CSGT AT command (see u-blox AT Commands
Manual [3]) to notify the external application that the module is ready to operate (i.e. ready to reply to
AT commands) and the first AT command can be sent to the module, given that autobauding has to
be disabled on the UART to let the module sending the greeting text: the UART has to be configured
at fixed baud rate (the baud rate of the application processor) instead of the default autobauding,
otherwise the module does not know the baud rate to be used for sending the greeting text (or any
other URC) at the end of the internal boot sequence.
☞ The Internal Reset signal is not available on a module pin, but the host application can monitor:
☞ Before the switch-on of the generic digital interface supply source (V_INT) of the module, no
☞ Before the TOBY-L2 / MPCI-L2 module is fully ready to operate, the host application processor
☞ The duration of the TOBY-L2 and MPCI-L2 series modules’ switch-on routine can vary depending
o The V_INT pin to sense the start of the TOBY-L2 module power-on sequence.
o The USB interface to sense the start of the MPCI-L2 module power-on sequence: the module,
as USB device, informs the host of the attach event via a reply on its status change pipe for
proper bus enumeration process according to USB Revision 2.0 specification [7].
voltage driven by an external application should be applied to any generic digital interface of
TOBY-L2 module.
should not send any AT command over AT communication interfaces (USB, UART) of the module.
on the application / network settings and the concurrent module activities.
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1.6.2 Module power-off
TOBY-L2 series can be properly switched off by:
AT+CPWROFF command (see u-blox AT Commands Manual [3]). The current parameter settings
are saved in the module’s non-volatile memory and a proper network detach is performed.
☞ The MPCI-L2 series modules do not switch off by the AT+CPWROFF command as the TOBY-L2
modules, but the AT+CPWROFF command causes a reset (reboot) of the module due to the MPCIL2 module’s internal configuration: the command stores the actual parameter settings in the nonvolatile memory of MPCI-L2 modules and performs a network detach, with a subsequent reset
(reboot) of the module.
An abrupt under-voltage shutdown occurs on TOBY-L2 and MPCI-L2 series modules when the VCC or
3.3Vaux module supply is removed. If this occurs, it is not possible to perform the storing of the
current parameter settings in the module’s non-volatile memory or to perform the proper network
detach.
☞ It is highly recommended to avoid an abrupt removal of the VCC supply during TOBY-L2 modules
normal operations: the power off procedure must be started by the AT+CPWROFF command,
waiting the command response for a proper time period (see u-blox AT Commands Manual [3]),
and then a proper VCC supply has to be held at least until the end of the modules’ internal power
off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched
off by the module.
☞ It is highly recommended to avoid an abrupt removal of the 3.3Vaux supply during MPCI-L2
modules normal operations: the power off procedure must be started by setting the MPCI-L2
module in the halt mode by the AT+CFUN=127 command (which stores the actual parameter
settings in the non-volatile memory of the module and performs a network detach), waiting the
command response for a proper time period (see the u-blox AT Commands Manual [3]), and then
the 3.3Vaux supply can be removed.
An abrupt hardware shutdown occurs on TOBY-L2 series modules when a low level is applied on the
RESET_N pin for a specific time period. In this case, the current parameter settings are not saved in
the module’s non-volatile memory and a proper network detach is not performed.
☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low
level on the RESET_N input pin during module normal operation: the RESET_N line should be set
low only if reset or shutdown via AT commands fails or if the module does not reply to a specific
AT command after a time period longer than the one defined in the u-blox AT Commands
Manual [3].
An over-temperature or an under-temperature shutdown occurs on TOBY-L2 and MPCI-L2 series
modules when the temperature measured within the cellular module reaches the dangerous area, if
the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT
command. For more details see u-blox AT Commands Manual [3], +USTS AT command.
☞ The Smart Temperature Supervisor feature is not supported by the “00”, “01”, “60” product
versions.
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VCC
V_BCKP
PWR_ON
RESET_N
V_INT
Internal Reset
System State
BB Pads State Operational
OFF
Tristate / Floating
ON
Operational →
Tristate
AT+CPWROFF
sent to the module
OK
replied by the module
VCC
can be removed
3.3Vaux
PERST#
Internal Reset
System State
BB Pads State
OFF
ON
Tristate / Floating
Operational
AT+CFUN=127
sent to the module
OK
replied by the module
3.3Vaux
can be removed
Figure 15 describes TOBY-L2 power-off sequence by means of AT+CPWROFF with following phases:
When the +CPWROFF AT command is sent, the module starts the switch-off routine.
The module replies OK on the AT interface: the switch-off routine is in progress.
At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).
Then, the module remains in power-off mode as long as a switch on event does not occur (e.g.
applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N
input), and enters not-powered mode if the supply is removed from the VCC pins.
Figure 15: TOBY-L2 series power-off sequence description
☞ The Internal Reset signal is not available on a module pin, but it is recommended monitoring the
V_INT pin to sense the end of the internal switch-off sequence: the VCC supply of the module can
be removed only after V_INT goes low.
Figure 16 describes the MPCI-L2 power-off procedure with the following phases:
When the AT+CFUN=127 command is issued, the module starts the halt mode setting routine.
The module replies OK on the AT interface: after this, the module is set in the halt mode.
Then, the module remains in the Halt mode and enters not-powered mode if the supply is removed
from the 3.3Vaux pins.
Figure 16: MPCI-L2 series power-off procedure description
☞ The duration of each phase in the TOBY-L2 and MPCI-L2 series modules’ switch-off routines can
largely vary depending on the application / network settings and the concurrent module activities.
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Baseband
Processor
23
RESET_N
TOBY-L2 series
VCC
Reset
Power
Management
Reset
50k
Baseband
Processor
22
PERST#
MPCI-L2 series
Reset
Power
Management
Reset
45k
3.3 V
1.6.3 Module reset
TOBY-L2 and MPCI-L2 series modules can be properly reset (rebooted) by:
AT+CFUN command (see u-blox AT Commands Manual [3]).
MPCI-L2 series modules can be additionally properly reset (rebooted) by:
AT+CPWROFF command (see u-blox AT Commands Manual [3]): the behavior differs than
TOBY-L2 series, as MPCI-L2 modules will reboot rather than remain switched off due to modules’
internal configuration.
In the cases listed above an “internal” or “software” reset of the module is executed: the current
parameter settings are saved in the non-volatile memory and proper network detach is performed
An abrupt hardware reset occurs on TOBY-L2 and MPCI-L2 series modules when a low level is applied
on the RESET_N or PERST# input pin for a specific time period. In this case, the current parameter
settings are not saved in module’s non-volatile memory and a proper network detach is not performed.
☞ It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on
the RESET_N or PERST# input during modules normal operation: the RESET_N or PERST# line
should be set low only if reset or shutdown via AT commands fails or if the module does not provide
a reply to a specific AT command after a time period longer than the one defined in the u-blox AT
Commands Manual [3].
As described in Figure 17, the RESET_N and PERST# input pins are equipped with an internal pull-up
to the VCC supply in the TOBY-L2 series and to the 3.3 V in the MPCI-L2 series.
Figure 17: TOBY-L2 and MPCI-L2 series RESET_N and PERST# input equivalent circuit description
☞ For more electrical characteristics details see TOBY-L2 / MPCI-L2 Data Sheet [1][2].
1.6.4 Module configuration selection by host processor
☞ HOST_SELECT0 and HOST_SELECT1 pins are not available on MPCI-L2 series.
☞ Functionality of HOST_SELECT0 and HOST_SELECT1 pins is not supported by TOBY-L2 series.
TOBY-L2 series modules include two input pins (HOST_SELECT0 and HOST_SELECT1) for the
selection of the module configuration by the host application processor.
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Base Station
Tx-1
Antenna
Tx-2
Antenna
TOBY-L2 series
MPCI-L2 series
ANT1
Rx-1
Antenna
ANT2
Rx-2
Antenna
Data Stream 1
Data Stream 2
1.7 Antenna interface
1.7.1 Antenna RF interfaces (ANT1 / ANT2)
TOBY-L2 and MPCI-L2 series modules provide two RF interfaces for connecting external antennas:
The ANT1 represents the primary RF input/output for transmission and reception of LTE/3G/2G
RF signals.
The ANT1 pin of TOBY-L2 modules has a nominal characteristic impedance of 50 and must be
connected to the primary Tx / Rx antenna through a 50 transmission line to allow proper RF
transmission and reception.
The ANT1 Hirose U.FL-R-SMT coaxial connector receptacle of MPCI-L2 modules has a nominal
characteristic impedance of 50 and must be connected to the primary Tx / Rx antenna through
a mated RF plug with a 50 coaxial cable assembly to allow proper RF transmission and reception.
The ANT2 represents the secondary RF input for the reception of the LTE RF signals for the
Down-Link MIMO 2 x 2 radio technology supported by TOBY-L2 and MPCI-L2 series modules as
required feature for LTE category 4 UEs, and for the reception of the 3G RF signals for the
Down-Link Rx diversity radio technology supported by TOBY-L2 and MPCI-L2 series modules as
additional feature for 3G DC-HSDPA category 24 .
The ANT2 pin of TOBY-L2 modules has a nominal characteristic impedance of 50 and must be
connected to the secondary Rx antenna through a 50 transmission line to allow proper RF
reception.
The ANT2 Hirose U.FL-R-SMT coaxial connector receptacle of MPCI-L2 modules has a nominal
characteristic impedance of 50 and must be connected to the secondary Rx antenna through a
mated RF plug with a 50 coaxial cable assembly to allow proper RF reception.
The Multiple Input Multiple Output (MIMO) radio technology is an essential component of LTE radio
systems based on the use of multiple antennas at both the transmitter and receiver sides to improve
communication performance and achieve highest possible bit rate. A MIMO m x n system consists of
m transmit and n receive antennas, where the data to be transmitted is divided into m independent
data streams. Note that the terms Input and Output refer to the radio channel carrying the signal, not
to the devices having antennas, so that in the Down-Link MIMO 2 x 2 system supported by TOBY-L2
and MPCI-L2 series modules:
The LTE data stream is divided into 2 independent streams by the Tx-antennas of the base station
The cellular modules, at the receiver side, receives both LTE data streams by 2 Rx-antennas
Figure 18: Description of the LTE Down-Link MIMO 2 x 2 radio technology supported by TOBY-L2 and MPCI-L2 series modules
TOBY-L2 and MPCI-L2 series modules support the LTE MIMO 2 x 2 radio technology in the Down-Link
path only (from the base station to the module): the ANT1 port is the only one RF interface that is used
by the module to transmit the RF signal in the Up-Link path (from the module to the base station).
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(ANT1 / ANT2)
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Item
Requirement
Remark
Impedance
50 nominal characteristic impedance
The impedance of the antenna RF connection must
match the 50 impedance of the ANT1 port.
Frequency Range
See the TOBY-L2 series Data Sheet [1] and the
MPCI-L2 series Data Sheet [2]
The required frequency range of the antenna
connected to ANT1 port depends on the operating
bands of the used cellular module and the used
mobile network.
Return Loss
S11 < -10 dB (VSWR < 2:1) recommended
S11 < -6 dB (VSWR < 3:1) acceptable
The Return loss or the S11, as the VSWR, refers to the
amount of reflected power, measuring how well the
primary antenna RF connection matches the 50
characteristic impedance of the ANT1 port.
The impedance of the antenna termination must
match as much as possible the 50 nominal
impedance of the ANT1 port over the operating
frequency range, reducing as much as possible the
amount of reflected power.
Efficiency
> -1.5 dB ( > 70% ) recommended
> -3.0 dB ( > 50% ) acceptable
The radiation efficiency is the ratio of the radiated
power to the power delivered to antenna input: the
efficiency is a measure of how well an antenna
receives or transmits.
The radiation efficiency of the antenna connected to
the ANT1 port needs to be enough high over the
operating frequency range to comply with the
Over-The-Air (OTA) radiated performance
requirements, as Total Radiated Power (TRP) and the
Total Isotropic Sensitivity (TIS), specified by
applicable related certification schemes.
Maximum Gain
According to radiation exposure limits
The power gain of an antenna is the radiation
efficiency multiplied by the directivity: the gain
describes how much power is transmitted in the
direction of peak radiation to that of an isotropic
source.
The maximum gain of the antenna connected to
ANT1 port must not exceed the herein stated value to
comply with regulatory agencies radiation exposure
limits.
For additional info see sections 4.2.2 and/or 4.3.1
Input Power
> 33 dBm ( > 2 W )
The antenna connected to the ANT1 port must
support with adequate margin the maximum power
transmitted by the modules.
1.7.1.1 Antenna RF interfaces requirements
Table 8, Table 9 and Table 10 summarize the requirements for the antennas RF interfaces
(ANT1 / ANT2). See section 2.4.1 for suggestions to properly design antennas circuits compliant with
these requirements.
⚠ The antenna circuits affect the RF compliance of the device integrating TOBY-L2 and MPCI-L2
series modules with applicable required certification schemes (for more details see section 4).
Compliance is guaranteed if the antenna RF interfaces (ANT1 / ANT2) requirements summarized
in Table 8, Table 9 and Table 10 are fulfilled.
Table 8: Summary of primary Tx/Rx antenna RF interface (ANT1) requirements
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Item
Requirement
Remark
Impedance
50 nominal characteristic impedance
The impedance of the antenna RF connection must
match the 50 impedance of the ANT2 port.
Frequency Range
See the TOBY-L2 series Data Sheet [1] and the
MPCI-L2 series Data Sheet [2]
The required frequency range of the antennas
connected to ANT2 port depends on the operating
bands of the used cellular module and the used
Mobile Network.
Return Loss
S11 < -10 dB (VSWR < 2:1) recommended
S11 < -6 dB (VSWR < 3:1) acceptable
The Return loss or the S11, as the VSWR, refers to the
amount of reflected power, measuring how well the
secondary antenna RF connection matches the 50
characteristic impedance of the ANT2 port.
The impedance of the antenna termination must
match as much as possible the 50 nominal
impedance of the ANT2 port over the operating
frequency range, reducing as much as possible the
amount of reflected power.
Efficiency
> -1.5 dB ( > 70% ) recommended
> -3.0 dB ( > 50% ) acceptable
The radiation efficiency is the ratio of the radiated
power to the power delivered to antenna input: the
efficiency is a measure of how well an antenna
receives or transmits.
The radiation efficiency of the antenna connected to
the ANT2 port needs to be enough high over the
operating frequency range to comply with the
Over-The-Air (OTA) radiated performance
requirements, as the TIS, specified by applicable
related certification schemes.
Item
Requirement
Remark
Efficiency
imbalance
< 0.5 dB recommended
< 1.0 dB acceptable
The radiation efficiency imbalance is the ratio of the
primary (ANT1) antenna efficiency to the secondary
(ANT2) antenna efficiency: the efficiency imbalance is
a measure of how much better an antenna receives or
transmits compared to the other antenna.
The radiation efficiency of the secondary antenna
needs to be roughly the same of the radiation
efficiency of the primary antenna for good RF
performance.
Envelope
Correlation
Coefficient
< 0.4 recommended
< 0.5 acceptable
The Envelope Correlation Coefficient (ECC) between
the primary (ANT1) and the secondary (ANT2)
antenna is an indicator of 3D radiation pattern
similarity between the two antennas: low ECC results
from antenna patterns with radiation lobes in
different directions.
The ECC between primary and secondary antenna
needs to be enough low to comply with radiated
performance requirements specified by related
certification schemes.
Isolation
> 15 dB recommended
> 10 dB acceptable
The antenna to antenna isolation is the loss between
the primary (ANT1) and the secondary (ANT2)
antenna: high isolation results from low coupled
antennas.
The isolation between primary and secondary
antenna needs to be high for good RF performance.
Table 9: Summary of secondary Rx antenna RF interface (ANT2) requirements
Table 10: Summary of primary (ANT1) and secondary (ANT2) antennas relationship requirements
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1.7.2 Antenna detection interface (ANT_DET)
☞ Antenna detection (ANT_DET) is not available on MPCI-L2 series modules.
☞ Antenna detection (ANT_DET) is not supported by TOBY-L2 “00”, “01” and “60” product versions.
The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital
Converter (ADC) provided to sense the antenna presence.
The antenna detection function provided by ANT_DET pin is an optional feature that can be
implemented if the application requires it. The antenna detection is forced by the +UANTR AT
command. See the u-blox AT Commands Manual [3] for more details on this feature.
The ANT_DET pin generates a DC current (for detailed characteristics see the TOBY-L2 series Data
Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna
connector provided on the application board to GND. So, the requirements to achieve antenna
detection functionality are the following:
an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
an antenna detection circuit must be implemented on the application board
See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna
assembly design-in guidelines.
1.8 SIM interface
1.8.1 SIM interface
TOBY-L2 and MPCI-L2 series modules provide high-speed SIM/ME interface including automatic
detection and configuration of the voltage required by the connected SIM card or chip.
Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage
switch from 1.8 V to 3 V are implemented, according to ISO-IEC 7816-3 specifications. The VSIM or
UIM_PWR supply output provides internal short circuit protection to limit start-up current and
protect the SIM to short circuits.
1.8.2 SIM detection interface
☞ SIM detection (GPIO5) is not available on MPCI-L2 series modules.
☞ SIM detection (GPIO5) is not supported by TOBY-L2 “00”, “01” and “60” product versions.
The GPIO5 pin is by default configured to detect the external SIM card mechanical / physical presence.
The pin is configured as input, and it can sense SIM card presence as intended to be properly
connected to the mechanical switch of a SIM card holder as described in section 2.5:
Low logic level at GPIO5 input pin is recognized as SIM card not present
High logic level at GPIO5 input pin is recognized as SIM card present
The SIM card detection function provided by GPIO5 pin is an optional feature that can be implemented
/ used or not according to the application requirements: an Unsolicited Result Code (URC) is generated
each time that there is a change of status (for more details see u-blox AT Commands Manual [3],
+UGPIOC, +CIND, +CMER).
The optional function “SIM card hot insertion/removal” can be additionally enabled on the GPIO5 pin
by specific AT command (see the u-blox AT Commands Manual [3], +UDCONF=50), to enable / disable
the SIM interface upon detection of external SIM card physical insertion / removal.
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1.9 Data communication interfaces
TOBY-L2 and MPCI-L2 series modules provide the following serial communication interface:
USB interface: High-Speed USB 2.0 compliant interface available for the communication with an
external host application processor, for AT commands, data communication, FW upgrade by
means of the FOAT feature, FW upgrade by means of the u-blox EasyFlash tool and for diagnostic
purpose (see section 1.9.1 for functional description)
TOBY-L2 series modules additionally provide the following serial communication interfaces:
UART interface: asynchronous serial interface available for the communication with an external
host application processor, for AT commands, data communication, FW upgrade by means of the
FOAT feature (see section 1.9.2 for functional description)
DDC interface: I
devices as an audio codec (see section 1.9.3 for functional description)
SDIO interface: Secure Digital Input Output interface available for the communication with an
external u-blox Wi-Fi module (see section 1.9.4 for functional description)
1.9.1 Universal Serial Bus (USB)
1.9.1.1 USB features
2
C bus compatible interface available for the communication with external I2C
TOBY-L2 and MPCI-L2 series modules include a High-Speed USB 2.0 compliant interface with
maximum data rate of 480 Mb/s, representing the main interface for transferring high speed data
with a host application processor: the USB interface is available for AT commands, data
communication, FW upgrade by means of the FOAT feature, FW upgrade by means of the u-blox
EasyFlash tool and for diagnostic purpose.
The module itself acts as a USB device and can be connected to a USB host such as a Personal
Computer or an embedded application microprocessor equipped with compatible drivers.
The USB_D+ / USB_D- lines carry the USB serial bus data and signaling, providing all the
functionalities for the bus attachment, configuration, enumeration, suspension or remote wakeup
according to the Universal Serial Bus Revision 2.0 specification [7].
☞ The VUSB_DET functionality is not supported by all the TOBY-L2 modules product versions: the
pin should be left unconnected or it should not be driven high by any external device, because a
high logic level applied to the pin will represent a module switch-on event (additional to the ones
listed in section 1.6.1) and will prevent reaching the minimum possible consumption with power
saving enabled.
☞ The VUSB_DET pin is not available on MPCI-L2 series modules.
The USB interface is controlled and operated with:
AT commands according to 3GPP TS 27.007 [9], 3GPP TS 27.005 [10], 3GPP TS 27.010 [11]
u-blox AT commands
☞ For the complete list of supported AT commands and their syntax see u-blox AT Commands
Manual [3].
TOBY-L2 and MPCI-L2 modules provide by default the following USB profile with the listed set of USB
functions:
1 RNDIS for Ethernet-over-USB connection
1 CDC-ACM for AT commands and data communication
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Default profile configuration
Interface 0 Wireless Controller – Remote NDIS
Interface 1 Communication Data
EndPoint Transfer: Interrupt
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Interface 2 Communication Control – AT commands
EndPoint Transfer: Interrupt
Interface 3 Communication Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function RNDIS
Function CDC Serial
8
9
10
8
9
10
The USB profile of TOBY-L2 and MPCI-L2 modules identifies itself by its VID (Vendor ID) and PID
(Product ID) combination, included in the USB device descriptor according to the USB 2.0
specifications [7].
The VID and PID of the default USB profile configuration with the set of functions described above (1
RNDIS for Ethernet-over-USB, and 1 CDC-ACM for AT commands and data) are the following:
VID = 0x1546
PID = 0x1146
Figure 19 summarizes the USB end-points available with the default USB profile configuration.
Figure 19: TOBY-L2 and MPCI-L2 series USB End-Points summary for the default USB profile configuration
The USB of the modules can be configured by the AT+UUSBCONF command (for more details see the
u-blox AT Commands Manual [3]) to select different sets of USB functions available in mutually
exclusive way, selecting the active USB profile consisting of a specific set of functions with various
capabilities and purposes, such as:
CDC-ACM for AT commands and data
CDC-ACM for remote SIM Access Profile (SAP)
CDC-ACM for diagnostic
RNDIS for Ethernet-over-USB
CDC-ECM for Ethernet-over-USB
For example, the default USB profile configuration which provides 2 functions (1 RNDIS for
Ethernet-over-USB, and 1 CDC-ACM for AT commands and data) can be changed by means of the
AT+UUSBCONF command switching to a USB profile configuration which provides the following 6
functions:
3 CDC-ACM for AT commands and data
1 CDC-ACM for GNSS tunneling
1 CDC-ACM for remote SIM Access Profile (SAP)
1 CDC-ACM for diagnostic
Not supported by “00”, “01”, “02”, “60”, “62” product versions
Not supported by “00”, “01”, “02”, “03”, “60”, “62” product versions
Not supported by “00”, “01”, “02”, “60”, “62” product versions
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As each USB profile of TOBY-L2 and MPCI-L2 modules identifies itself by its specific VID and PID
combination included in the USB device descriptor according to the USB 2.0 specifications [7], the VID
and PID combination changes as following by switching the active USB profile configuration to the set
of functions described above (3 CDC-ACM for AT commands and data, and 1 CDC-ACM for
diagnostic):
VID = 0x1546
PID = 0x1141
Alternatively, as another example, the USB profile configuration can be changed by means of the
AT+UUSBCONF command switching to a USB profile configuration which provides the following
functions:
1 CDC-ECM for Ethernet-over-USB
3 CDC-ACM for AT commands and data
In case of this USB profile with the set of functions described above (1 CDC-ECM for Ethernet-overUSB, and 3 CDC-ACM for AT commands and data), the VID and PID are the following:
VID = 0x1546
PID = 0x1143
The switch of the active USB profile selected by the AT+UUSBCONF command is not performed
immediately. The settings are saved in the non-volatile memory of the module at the power off,
triggered by means of the AT+CPWROFF command, and the new configuration is effective at the
subsequent reboot of the module.
If the USB is connected to the host before the module is switched on, or if the module is reset
(rebooted) with the USB connected to the host, the VID and PID are automatically updated during the
boot of the module. First, VID and PID are the following:
VID = 0x1546
PID = 0x1140
This VID and PID combination identifies a USB profile where no USB function described above is
available: AT commands must not be sent to the module over the USB profile identified by this VID
and PID combination.
Then, after a time period (roughly 20 s, depending on the host / device enumeration timings), the VID
and PID are updated to the ones related to the USB profile selected by the AT+UUSBCONF command.
☞ For more details regarding the TOBY-L2 and MPCI-L2 series modules USB configurations and
capabilities, see the u-blox AT Commands Manual [3], +UUSBCONF AT command.
1.9.1.2 USB in Windows
USB drivers are provided for Windows operating system platforms and should be properly installed /
enabled by following the step-by-step instructions available in the EVK-L2x User Guide [4] or in the
Windows Embedded OS USB Driver Installation Application Note [5].
USB drivers are available for the following operating system platforms:
Windows Vista
Windows 7
Windows 8
Windows 8.1
Windows 10
Windows Embedded CE 6.0
Windows Embedded Compact 7
Windows Embedded Compact 2013
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The module firmware can be upgraded over the USB interface by means of the FOAT feature, or using
the u-blox EasyFlash tool (for more details see Firmware Update Application Note [6]).
1.9.1.3 USB in Linux/Android
It is not required to install a specific driver for each Linux-based or Android-based operating system
(OS) to use the module USB interface, which is compatible with standard Linux/Android USB kernel
drivers.
The full capability and configuration of the module USB interface can be reported by running “lsusb –
v” or an equivalent command available in the host operating system when the module is connected.
1.9.1.4 USB and power saving
The modules automatically enter the USB suspended state when the device has observed no bus
traffic for a specific time period according to the USB 2.0 specification [7]. In suspended state, the
module maintains any USB internal status as device. In addition, the module enters the suspended
state when the hub port it is attached to is disabled. This is referred to as USB selective suspend.
If the USB is suspended and a power saving configuration is enabled by the AT+UPSV command, the
module automatically enters the low power idle-mode whenever possible but it wakes up to
active-mode according to any required activity related to the network (e.g. the periodic paging
reception described in section 1.5.1.5) or any other required activity related to the functions /
interfaces of the module.
The USB exits suspend mode when there is bus activity. If the USB is connected and not suspended,
the module is forced to stay in active-mode, therefore the AT+UPSV settings are overruled but they
have effect on the power saving configuration of the other interfaces.
The modules are capable of USB remote wake-up signaling: i.e. it may request the host to exit suspend
mode or selective suspend by using electrical signaling to indicate remote wake-up, for example due
to incoming call, URCs, data reception on a socket. The remote wake-up signaling notifies the host
that it should resume from its suspended mode, if necessary, and service the external event. Remote
wake-up is accomplished using electrical signaling described in the USB 2.0 specifications [7].
For the module current consumption description with power saving enabled and USB suspended, or
with power saving disabled and USB not suspended, see the sections 1.5.1.5, 1.5.1.6 and the TOBY-L2
Data Sheet [1] or the MPCI-L2 Data Sheet [2].
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1.9.2 Asynchronous serial interface (UART)
☞ The UART interface is not available on MPCI-L2 series modules.
☞ The UART interface is not supported by TOBY-L2 series modules “00” product versions.
1.9.2.1 UART features
The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface (UART) that can be
connected to an application host processor for AT commands and data communication.
The module firmware can be upgraded over the UART interface by means of the Firmware upgrade
over AT (FOAT) feature only: for more details see section 1.15 and the Firmware Update Application
Note [6].
UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [8],
with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF
state (for detailed electrical characteristics see TOBY-L2 Data Sheet [1]), providing:
data lines (RXD as output, TXD as input),
hardware flow control lines (CTS as output, RTS as input),
modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output).
TOBY-L2 modules are designed to operate as LTE/3G/2G cellular modems, i.e. as the data
circuit-terminating equipment (DCE) according to the ITU-T V.24 Recommendation [8]. A host
application processor connected to the module through the UART interface represents the data
terminal equipment (DTE).
☞ UART signal names of TOBY-L2 modules conform to the ITU-T V.24 Recommendation [8]: e.g. TXD
line represents data transmitted by the DTE (host processor output) and received by the DCE
(module input).
The UART interface is controlled and operated with:
AT commands according to 3GPP TS 27.007 [9], 3GPP TS 27.005 [10], 3GPP TS 27.010 [11]
u-blox AT commands
☞ For the complete list of supported AT commands and their syntax see u-blox AT Commands
Manual [3], and in particular for the UART configuration see the +IPR, +ICF, +IFC, &K, \Q, +UPSV
AT commands.
Flow control handshakes are supported by the UART interface and can be set by appropriate AT
commands (see u-blox AT Commands Manual [3], &K, +IFC, \Q AT commands): hardware flow control
(over the RTS / CTS lines), software flow control (XON/XOFF), or none flow control.
☞ Hardware flow control is enabled by default.
☞ Software flow control is not supported by “00”, “01”, “60” and TOBY-L201-02S product versions.
The one-shot autobauding is supported: the automatic baud rate detection is performed only once, at
module start up. After the detection, the module works at the detected baud rate and the baud rate
can only be changed by AT command (see u-blox AT Commands Manual [3], +IPR).
☞ One-shot automatic baud rate recognition (autobauding) is enabled by default.
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D0 D1 D2 D3 D4 D5 D6 D7
Start of 1-Byte
transfer
Start Bit
(Always 0)
Possible Start of
next transfer
Stop Bit
(Always 1)
t
bit
= 1/(Baudrate)
Normal Transfer, 8N1
The following baud rates can be configured by AT command (see u-blox AT Commands Manual [3],
+IPR):
9'600 b/s
19'200 b/s
38'400 b/s
57'600 b/s
115'200 b/s, default value when one-shot autobauding is disabled
230'400 b/s
460'800 b/s
921'600 b/s
The following frame formats can be configured by AT command (see u-blox AT Commands
Manual [3], +ICF):
8N2 (8 data bits, no parity, 2 stop bits)
8N1 (8 data bits, no parity, 1 stop bit), default frame format
8E1 (8 data bits, even parity, 1 stop bit)
8O1 (8 data bits, odd parity, 1 stop bit)
7N2 (7 data bits, no parity, 2 stop bits)
7N1 (7 data bits, no parity, 1 stop bit)
7E1 (7 data bits, even parity, 1 stop bit)
7O1 (7 data bits, odd parity, 1 stop bit)
☞ Automatic frame recognition is not supported by all the TOBY-L2 modules product versions.
Figure 20 describes the 8N1 frame format, which is the default frame format configuration.
Figure 20: Description of UART default frame format (8N1, i.e. 8 data bits, no parity, 1 stop bit)
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Interface
AT settings
Comments
UART interface
AT interface: enabled
AT command interface is enabled by default on the UART physical interface
AT+IPR=0
One-shot autobauding enabled by default on the modules
AT+ICF=3,1
8N1 frame format enabled by default
AT&K3
HW flow control enabled by default
AT&S1
DSR line (Circuit 107 in ITU-T V.24) set ON in data mode11 and set OFF in command
mode16
AT&D1
Upon an ON-to-OFF transition of DTR line (Circuit 108/2 in ITU-T V.24), the module
(DCE) enters online command mode16 and issues an OK result code
AT&C1
DCD line (Circuit 109 in ITU-T V.24) changes in accordance with the Carrier detect
status; ON if the Carrier is detected, OFF otherwise
MUX protocol:
disabled
Multiplexing mode is disabled by default and it can be enabled by AT+CMUX
command. For more details, see the Mux Implementation Application Note [12].
The following virtual channels are defined:
Channel 0: control channel
Channel 1 – 5: AT commands / data connection
11
12
1.9.2.2 UART interface configuration
The UART interface of TOBY-L2 series modules is available as AT command interface with the default
configuration described in Table 11 (for more details and information about further settings, see the
u-blox AT Commands Manual [3]).
Table 11: Default UART interface configuration
1.9.2.3 UART signals behavior
At the module switch-on, before the UART interface initialization (as described in the power-on
sequence reported in Figure 14), each pin is first tri-stated and then is set to its relative internal reset
state12. At the end of the boot sequence, the UART interface is initialized, the module is by default in
active-mode, and the UART interface is enabled as AT commands interface.
The configuration and the behavior of the UART signals after the boot sequence are described below.
See section 1.4 for definition and description of module operating modes referred to in this section.
RXD signal behavior
The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization.
The module holds RXD in the OFF state until the module does not transmit some data.
TXD signal behavior
The module data input line (TXD) is set by default to the OFF state (high level) at UART initialization.
The TXD line is then held by the module in the OFF state if the line is not activated by the DTE: an
active pull-up is enabled inside the module on the TXD input.
For the definition of the interface data mode, command mode and online command mode see the u-blox AT Commands
Manual [3]
See the pin description table in the TOBY-L2 series Data Sheet [1]
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CTS signal behavior
The module HW flow control output (CTS line) is set to the ON state (low level) at UART initialization.
If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART
interface is enabled (data can be received): the module drives the CTS line to the ON state or to the
OFF state when it is either able or not able to accept data from the DTE over the UART (for example
see section 1.9.2.4, Figure 23).
☞ The module guarantees the reception of characters when the CTS line is set to the ON state, and
the module is also able to accept up to 3 characters after the CTS line is set to the OFF state.
☞ If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean
that the module is in low power idle-mode, but only that the UART is not enabled, as the module
could be forced to stay in active-mode for other activities, e.g. related to the network or related to
other interfaces.
☞ If hardware flow control is enabled and the multiplexer protocol is active, then the CTS line state
is mapped to Fcon / Fcoff MUX command for flow control matters outside the power saving
configuration while the physical CTS line is still used as a UART power state indicator (see the Mux
Implementation Application Note [12]).
The CTS hardware flow control setting can be changed by AT commands (for more details, see the
u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT commands).
If the hardware flow control is not enabled, the CTS line still indicates when the UART interface is
enabled, as it does when hardware flow control is enabled. The module drives the CTS line to the ON
state or to the OFF state when it is either able or not able to accept data from the DTE over the UART.
☞ When the power saving configuration is enabled by AT+UPSV command and the hardware flow-
control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first
character sent when the module is in low power idle-mode will not be a valid communication
character (see section 1.9.2.4 and in particular the sub-section “Wake up via data reception” for
further details).
RTS signal behavior
The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART
initialization. The module then holds the RTS line in the OFF state if the line is not activated by the
DTE: an active pull-up is enabled inside the module on the RTS input.
If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect
permission from the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any
on-going data transmission from the module is interrupted until the RTS line changes to the ON state.
☞ The DTE must still be able to accept a certain number of characters after the RTS line is set to the
OFF state: the module guarantees the transmission interruption within two characters from RTS
state change.
The module behavior according to the RTS HW flow control status can be configured by AT
commands (for more details, see the u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT
commands).
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13
If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage
the power saving configuration (for more details, see section 1.9.2.4 and u-blox AT Commands
Manual [3], AT+UPSV):
When an OFF-to-ON transition occurs on the RTS input, the UART is enabled and the module is
forced to active-mode; after ~5 ms from the transition the switch is completed and data can be
received without loss. The module cannot enter low power idle-mode and the UART is keep enabled
as long as the RTS input line is held in the ON state
If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power
mode) and the module automatically enters low power idle-mode whenever possible
DSR signal behavior
If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high
level) at UART initialization. The DSR line is then set to the OFF state when the module is in command
mode13 or in online command mode13 and is set to the ON state when the module is in data mode13.
If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART
initialization and is then always held in the ON state.
DTR signal behavior
The DTR module input line is set by default to the OFF state (high level) at UART initialization. The
module then holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up
is enabled inside the module on the DTR input.
Module behavior according to DTR status can be changed by AT command configuration (for more
details see the u-blox AT Commands Manual [3], &D AT command description).
If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving
configuration (for more details, see section 1.9.2.4 and u-blox AT Commands Manual [3], AT+UPSV):
When an OFF-to-ON transition occurs on the DTR input, the UART is enabled and the module is
forced to active-mode; after ~5 ms from the transition, the switch is completed and data can be
received without loss. The module cannot enter low power idle-mode and the UART is keep enabled
as long as the DTR input line is held in the ON state
If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power
mode) and the module automatically enters low power idle-mode whenever possible
DCD signal behavior
If AT&C1 is set, as it is by default, the DCD module output line is set by default to the OFF state (high
level) at UART initialization. The module then sets the DCD line according to the carrier detect status:
ON if the carrier is detected, OFF otherwise.
In case of voice calls, DCD is set to the ON state when the call is established.
If a Packet Switched Data call occurs before activating the PPP protocol (data mode), a dial-up
application must provide the ATD*99***<context_number># to the module: with this command the
module switches from command mode13 to data mode13 and can accept PPP packets. The module sets
the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The
DCD ON is not related to the context activation but with the data mode.
For the definition of the interface data mode, command mode and online command mode see the u-blox AT Commands
Manual [3]
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1s
time [s]
151050
RI ON
RI OFF
Call incomes
1s
time [s]
151050
RI ON
RI OFF
Call incomes
SMS arrives
time [s]
0
RI ON
RI OFF
1s
time [s]
0
RI ON
RI OFF
1s
☞ The DCD is set to ON during the execution of the +CMGS, +CMGW, +USOWR, +USODL AT
commands requiring input data from the DTE: the DCD line is set to the ON state as soon as the
switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as
soon as the input mode is interrupted or completed (for more details see the u-blox AT Commands
Manual [3]).
☞ The DCD line is kept in the ON state, even during the online command mode
13
, to indicate that the
data call is still established even if suspended, while if the module enters command mode13, the
DSR line is set to the OFF state. For more details see DSR signal behavior description.
☞ For scenarios when the DCD line setting is requested for different reasons (e.g. SMS texting
during online command mode13), the DCD line changes to guarantee the correct behavior for all the
scenarios. For example, in case of SMS texting in online command mode13, if the data call is
released, DCD is kept ON till the SMS command execution is completed (even if the data call
release would request DCD set OFF).
If AT&C0 is set, the DCD module output line is set by default to the ON state (low level) at UART
initialization and is then always held in the ON state.
RI signal behavior
The RI module output line is set by default to the OFF state (high level) at UART initialization.
The RI line can notify an incoming call: the RI line is switched from the OFF state to the ON state with
a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 21), until the DTE attached to the
module sends the ATA string and the module accepts the incoming data call. The RING string sent by
the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the
RI line to the ON state.
Figure 21: RI behavior during an incoming call
☞ RI incoming call notification is not supported by “00”, “01”, “60”, TOBY-L201-02S product versions.
The RI output line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to
ON for 1 s (see Figure 22), if the feature is enabled by AT+CNMI command (see the u-blox AT
Commands Manual [3]).
Figure 22: RI behavior at SMS arrival
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This behavior allows the DTE to stay in power saving mode until the DCE related event requests
service. For SMS arrival, if several events coincidently occur or in quick succession each event
independently triggers the RI line, although the line will not be deactivated between each event. As a
result, the RI line may stay to ON for more than 1 s, if an incoming call is answered within less than 1 s
(with ATA or if auto-answering is set to ATS0=1) than the RI line is set to OFF earlier, so that:
☞ RI line monitoring cannot be used by the DTE to determine the number of received SMSes.
☞ For multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate
the two events, but the DTE must rely on subsequent URCs and interrogate the DCE with the
proper commands.
The RI line can additionally notify all the URCs and/or all the incoming data in PPP and Direct Link
connections, if the feature is enabled by the AT+URING command (for more details see the u-blox AT
Commands Manual [3]): the RI line is asserted when one of the configured events occur and it remains
asserted for 1 s unless another configured event will happen, with the same behavior described in
Figure 22.
☞ The AT+URING command for the notification of all the URCs and/or incoming data in PPP and
Direct Link connections over RI line is not supported by “00”, “01”, “60”, TOBY-L201-02S product
versions.
1.9.2.4 UART and power-saving
The power saving configuration is controlled by the AT+UPSV command (for the complete
description, see the u-blox AT Commands Manual [3]). When power saving is enabled, the module
automatically enters low power idle-mode whenever possible, and otherwise the active-mode is
maintained by the module (see section 1.4 for definition and description of module operating modes
referred to in this section).
The AT+UPSV command configures both the module power saving and also the UART behavior in
relation to the power saving. The conditions for the module entering low power idle-mode also depend
on the UART power saving configuration, as the module does not enter the low power idle-mode
according to any required activity related to the network (within or outside an active call) or any other
required concurrent activity related to the functions and interfaces of the module, including the UART
interface.
The AT+UPSV command can set these different power saving configurations:
AT+UPSV=0, power saving disabled (default configuration)
AT+UPSV=1, power saving enabled cyclically
AT+UPSV=2, power saving enabled and controlled by the UART RTS input line
AT+UPSV=3, power saving enabled and controlled by the UART DTR input line
The different power saving configurations that can be set by the +UPSV AT command are described
in details in the following subsections. Table 12 summarizes the UART interface communication
process in the different power saving configurations, in relation with the hardware flow control
settings and the RTS input line status. For more details on the +UPSV AT command description, see
u-blox AT commands Manual [3].
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AT+UPSV
HW flow control
RTS line
DTR line
Communication during idle-mode and wake up
0
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE.
0
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON)
0
Disabled (AT&K0)
ON or OFF
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise the data is lost.
1
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE is buffered by the DTE and will be correctly received by
the module when it is ready to receive data (when the UART is enabled).
Data sent by the module is correctly received by the DTE.
1
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE is buffered by the DTE and will be correctly received by
the module when it is ready to receive data (when the UART is enabled).
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
1
Disabled (AT&K0)
ON or OFF
ON or OFF
The first character sent by the DTE is lost by the module, but after ~5 ms the
UART and the module are woken up: recognition of subsequent characters is
guaranteed only after the UART / module complete wake-up (i.e. after ~5 ms).
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise the data is lost.
2
Enabled (AT&K3)
ON or OFF
ON or OFF
Not Applicable: HW flow control cannot be enabled with AT+UPSV=2.
2
Disabled (AT&K0)
ON
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
2
Disabled (AT&K0)
OFF
ON or OFF
Data sent by the DTE is lost by the module14.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
3
Enabled (AT&K3)
ON
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
ON
OFF
Data sent by the DTE is buffered by the DTE and will be correctly received by
the module when it is ready to receive data (when the UART is enabled).
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Enabled (AT&K3)
OFF
OFF
Data sent by the DTE is buffered by the DTE and will be correctly received by
the module when it is ready to receive data (when the UART is enabled). Data
sent by the module is buffered by the module and will be correctly received by
the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Disabled (AT&K0)
ON or OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
3
Disabled (AT&K0)
ON or OFF
OFF
Data sent by the DTE is lost by the module15.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
14
15
Table 12: UART and power-saving summary
Only the first character sent by the DTE is lost by ‘01’, ‘60’ TOBY-L201-02S product versions: the UART and the module are
woken up after ~5 ms due to wake up via data reception, and recognition of subsequent characters is guaranteed after the
UART / module wake-up.
Only the first character sent by the DTE is lost by ‘01’, ‘60’ TOBY-L201-02S product versions: the UART and the module are
woken up after ~5 ms due to wake up via data reception, and recognition of subsequent characters is guaranteed after the
UART / module wake-up
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time [s]
~9.2 s (default)
Data input
CTS ON
CTS OFF
AT+UPSV=0: power saving disabled, fixed active-mode
The module does not enter low power idle-mode and the UART interface is enabled (data can be sent
and received): the CTS line is always held in the ON state after UART initialization. This is the default
configuration.
AT+UPSV=1: power saving enabled, cyclic idle/active-mode
When the AT+UPSV=1 command is issued by the DTE, the UART is disabled after the timeout set by
the second parameter of the +UPSV AT command (for more details see u-blox AT commands
Manual [3]).
Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as
following:
Periodically, for paging reception (see section 1.5.1.5) or other activities, to temporarily receive or
send data over the UART, e.g. data buffered by the DTE with HW flow control enabled will be
correctly received
If the module needs to transmit some data (e.g. URC), the UART is temporarily enabled to send
data
If the DTE send data with HW flow control disabled, the first character sent causes the UART and
module wake-up after ~5 ms: recognition of subsequent characters is guaranteed only after the
complete wake-up (see the following subsection “wake up via data reception”)
The module automatically enters the low power idle-mode whenever possible but it wakes up to
active-mode according to the UART periodic wake up so that the module cyclically enters the low
power idle-mode and the active-mode. Additionally, the module wakes up to active-mode according to
any required activity related to the network (e.g. for the periodic paging reception described in section
1.5.1.5, or for any other required RF Tx / Rx) or any other required activity related to module functions
/ interfaces (including the UART itself).
When the UART interface is enabled, data can be received. When a character is received, it forces the
UART interface to stay enabled for a longer time and it forces the module to stay in the active-mode
for a longer time, according to the timeout configured by the second parameter of the +UPSV AT
command. The timeout can be set from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to
65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). Default value is 2000 2G-frames
(i.e. 2000 x 4.615 ms = 9.2 s). Every subsequent character received during the active-mode, resets and
restarts the timer; hence the active-mode duration can be extended indefinitely.
The CTS output line is driven to the ON or OFF state when the module is either able or not able to
accept data from the DTE over the UART: Figure 23 illustrates the CTS output line toggling due to
paging reception and data received over the UART, with AT+UPSV=1 configuration.
Figure 23: CTS output pin indicates when module’s UART is enabled (CTS = ON = low level) or disabled (CTS = OFF = high
level)
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AT+UPSV=2: power saving enabled and controlled by the RTS line
This configuration can only be enabled with the module HW flow control disabled (i.e. AT&K0 setting).
The UART interface is disabled after the DTE sets the RTS line to OFF.
Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as
following:
If an OFF-to-ON transition occurs on the RTS input line, this causes the UART / module wake-up
after ~5 ms: recognition of subsequent characters is guaranteed only after the complete wakeup, and the UART is kept enabled as long as the RTS input line is set to ON.
If the module needs to transmit data (e.g. URC), the UART is temporarily enabled to send data
If the DTE sends data, the first character sent causes the wake-up of UART / module product
versions “01”, “60” and TOBY-L201-02S after ~5 ms: recognition of subsequent characters is
guaranteed only after the complete wake-up, and the UART will be then kept enabled after last
data received according to the timeout previously set with AT+UPSV=1 configuration (see
following subsection “wake up via data reception”)
The module automatically enters the low power idle-mode whenever possible but it wakes up to
active-mode according to any required activity related to the network (e.g. for the periodic paging
reception described in section 1.5.1.5, or for any other required RF transmission / reception) or any
other required activity related to the module functions / interfaces (including the UART itself).
The hardware flow-control output (CTS line) indicates when the module is either able or not able to
accept data from the DTE over the UART, even if hardware flow control is disabled with
AT+UPSV=2 configuration.
AT+UPSV=3: power saving enabled and controlled by the DTR line
The UART interface is disabled after the DTE sets the DTR line to OFF.
Afterwards, the UART is enabled again and the module does not enter low power idle-mode, as follows:
If an OFF-to-ON transition occurs on the DTR input line, this causes the UART / module wake-up
after ~5 ms: recognition of subsequent characters is guaranteed only after the complete wake-up,
and the UART is kept enabled as long as the DTR input line is set to ON
If the module needs to transmit data (e.g. URC), the UART is temporarily enabled to send data
If the DTE sends data, the first character sent causes the wake-up of UART / module product
versions “01”, “60” and TOBY-L201-02S after ~5 ms: recognition of subsequent characters is
guaranteed only after the complete wake-up, and the UART will be then kept enabled after last
data received according to the timeout previously set with AT+UPSV=1 configuration (see
following subsection “wake up via data reception”)
The module automatically enters the low power idle-mode whenever possible but it wakes up to
active-mode according to any required activity related to the network (e.g. for the periodic paging
reception described in section 1.5.1.5, or for any other required RF signal transmission or reception) or
any other required activity related to the functions / interfaces of the module.
The AT+UPSV=3 configuration can be enabled regardless the flow control setting on UART. In
particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this
configuration. In both cases, with the AT+UPSV=3 configuration, the CTS line indicates when the
module is either able or not able to accept data from the DTE over the UART.
When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to
control the module behavior according to AT&D command configuration (see u-blox AT commands
Manual [3]).
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Wake up character
Not recognized by DCE
OFF
ON
DCE UART is enabled for 2000 GSM frames
(~9.2 s)
time
Wake up time: ~5 ms
time
TXD input
UART
OFF
ON
Wake up character
Not recognized by DCE
Valid characters
Recognized by DCE
DCE UART is enabled for 2000 GSM frames
(~9.2s) after the last data received
time
Wake up time: ~5 ms
time
OFF
ON
TXD input
UART
OFF
ON
Wake up via data reception
The UART wake up via data reception consists of a special configuration of the module TXD input line
that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In
particular, the UART is enabled and the module switches from the low power idle-mode to active-mode
within ~5 ms from the first character received: this is the system “wake up time”.
As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake up
character) is not a valid communication character even if the wake up via data reception configuration
is active, because it cannot be recognized, and the recognition of the subsequent characters is
guaranteed only after the complete system wake-up (i.e. after ~5 ms).
The TXD input line is configured to wake up the system via data reception in the following case:
AT+UPSV=1 is set with HW flow control disabled
The TXD input line on “01”, “60” and TOBY-L201-02S modules product versions is additionally
configured to wake up the system via data reception in the following cases:
AT+UPSV=2 is set with HW flow control disabled, and the RTS line is set OFF
AT+UPSV=3 is set with HW flow control disabled, and the DTR line is set OFF
Figure 24 and Figure 25 show examples of common scenarios and timing constraints:
AT+UPSV=1 power saving configuration is active and the timeout from last data received to
idle-mode start is set to 2000 frames (AT+UPSV=1,2000)
Hardware flow control is disabled
Figure 24 shows the case where the module UART is disabled and only a wake-up is forced. In this
scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE
module UART is disabled when the timeout from last data received expires (2000 frames without data
reception, as the default case).
Figure 24: Wake-up via data reception without further communication
Figure 25 shows the case where in addition to the wake-up character further (valid) characters are
sent. The wake up character wakes-up the module UART. The other characters must be sent after
the “wake up time” of ~5 ms. If this condition is satisfied, the module (DCE) recognizes characters.
The module will disable the UART after 2000 GSM frames from the latest data reception.
Figure 25: Wake-up via data reception with further communication
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16
16
☞ The “wake-up via data reception” feature cannot be disabled.
☞ In command mode
should always send a dummy character to the module before the “AT” prefix set at the beginning
of each command line: the first dummy character is ignored if the module is in active-mode, or it
represents the wake-up character if the module is in low power idle-mode.
☞ In command mode
should always send a dummy “AT” to the module before each command line: the first dummy “AT”
is not ignored if the module is in active-mode (i.e. the module replies “OK”), or it represents the
wake up character if the module is in low power idle-mode (i.e. the module does not reply).
Additional considerations
If the USB is connected and not suspended, the module is forced to stay in active-mode, therefore the
AT+UPSV settings are overruled but they have effect on the UART behavior (they configure UART
power saving, so that UART is enabled / disabled according to the AT+UPSV settings).
, with “wake-up via data reception” enabled and autobauding enabled, the DTE
16
, with “wake-up via data reception” enabled and autobauding disabled, the DTE
1.9.2.5 UART multiplexer protocol
TOBY-L2 series modules include multiplexer functionality as per 3GPP TS 27.010 [11], on the UART
physical link.
This is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and
the application processor (DTE) and allows a number of simultaneous sessions over the used physical
link (UART): the user can concurrently use AT interface on one MUX channel and data communication
on another MUX channel.
The following virtual channels are defined (for more details, see Mux implementation Application
Note [12]):
Channel 0: control channel
Channel 1 – 5: AT commands / data connection
1.9.3 DDC (I
☞ The I
☞ The I
The SDA and SCL pins of TOBY-L2 series modules represent an I2C bus compatible Display Data
Channel (DDC) interface for the communication with external I2C devices as audio codecs: an I2C
master can communicate with more I2C slaves in accordance to the I2C bus specifications [13].
The AT commands interface is not available on the DDC (I2C) interface.
DDC (I2C) slave-mode operation is not supported: the TOBY-L2 modules can act as I2C master only.
The DDC (I2C) interface pads of the module, serial data (SDA) and serial clock (SCL), are open drain
output and external pull up resistors must be used conforming to the I2C bus specifications [13].
2
C bus compatible Display Data Channel interface is not available on the MPCI-L2 series
modules.
2
C bus compatible Display Data Channel interface is not supported by the TOBY-L2 series
modules “00”, “01”, “60” and TOBY-L201-02S product versions.
2
C) interface
See the u-blox AT Commands Manual [3] for the definition of data mode, command mode and online command mode.
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1.9.4 Secure Digital Input Output interface (SDIO)
☞ SDIO interface is not available on MPCI-L2 series modules.
☞ SDIO interface is not supported by TOBY-L2 “00”, “01”, “60” product versions.
TOBY-L2 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1,
SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with an external u-blox short
range Wi-Fi module: the TOBY-L2 cellular module acts as an SDIO host controller which can
communicate over SDIO bus with compatible u-blox short range Wi-Fi module acting as SDIO device.
The SDIO interface is the only one interface of TOBY-L2 series modules dedicated for communication
between the u-blox cellular module and the u-blox short range Wi-Fi module. The AT commands
interface is not available on the SDIO interface of TOBY-L2 series modules.
The SDIO interface supports 50 MHz bus clock frequency, allowing a data throughput of 200 Mb/s.
Combining a u-blox cellular module with a u-blox short range communication module gives designers
full access to the Wi-Fi module directly via the cellular module, so that a second interface connected
to the Wi-Fi module is not necessary. AT commands via the AT interfaces of the cellular module
(UART, USB) allows a full control of the Wi-Fi module from any host processor, because Wi-Fi control
messages are relayed to the Wi-Fi module via the dedicated SDIO interface (for more details, see the
Wi-Fi AT commands in the u-blox AT Commands Manual [3]).
u-blox has implemented special features in the cellular modules to ease the design effort for the
integration of a u-blox cellular module with a u-blox short range Wi-Fi module to provide Router
functionality (for more details, see the Wi-Fi / Cellular Integration Application Note [15]).
Additional custom function over GPIO pins is designed to improve the integration with u-blox Wi-Fi
modules:
Wi-Fi enable Switch-on / switch-off the Wi-Fi
☞ GPIOs are not supported by TOBY-L2 “00”, “01” and “60” product versions, except for the Wireless
Wide Area Network status indication configured on GPIO1 pin.
☞ GPIOs are not available on MPCI-L2 series modules.
1.10 Audio
1.10.1 Digital audio over I
☞ I
☞ I
2
S digital audio interface is not available on MPCI-L2 modules.
2
S digital audio interface is not supported by TOBY-L2 ’00‘, ’01‘, ’60‘, ‘L201-02’, ‘L220-62’ versions.
2
S interface
TOBY-L2 series modules include a 4-wire I2S digital audio interface (I2S_TXD data output, I2S_RXD
data input, I2S_CLK clock output, I2S_WA world alignment / synchronization signal output) that can
be configured by AT command for digital audio communication with external digital audio devices as
an audio codec (for more details see the u-blox AT Commands Manual [3], +UI2S AT command).
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ECHFP
To
Radio TX
From
Radio RX
RES
NS
DRCLPF EQAGC
I2S_RXD
I2S_TXD
Volume &
Mute
CNG
AGCEQ
LPF
DRC
NSHPF
Volume &
Mute
PCM
Player
Tone
Generator
PAM
Legend:
EC = Echo Cancellation
RES = Residual Echo Suppression
NS = Noise Suppression
LPF = Low Pass Filter
HPF = High Pass Filter
EQU = Equalizer
AGC = Additional Gain Control
DRC = Dynamic Range
Compression
CNG = Comfort Noise Generator
TOBY-L2
The I2S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command:
PCM mode (short synchronization signal): I
2
S word alignment signal is set high for 1 or 2 clock
cycles for the synchronization, and then is set low for 31 or 30 clock cycles according to the 32
clock cycles frame length.
Normal I
2
S mode (long synchronization signal): I2S word alignment is set high / low with a 50% duty
cycle (high for 16 clock cycles / low for 16 clock cycles, according to the 32 clock cycles frame
length).
The modules support I2S master role only: the I2S_CLK clock and the I2S_WA world alignment
synchronization signal are generated by the module.
The sample rate of transmitted/received words, which corresponds to the I2S word alignment
synchronization signal frequency, can be set by the <I2S_sample_rate> parameter of AT+UI2S to:
8 kHz
16 kHz
The modules support I2S transmit and I2S receive data 16-bit words long, linear, mono. Data is
transmitted and read in 2’s complement notation. MSB is transmitted and read first.
I2S clock signal frequency is set to 32 x <I2S_sample_rate>: the frame length, which corresponds to
the I2S word alignment / synchronization signal period, is 32 I2S clock cycles long.
☞ For the complete description of the possible configurations and settings of the I
2
S digital audio
interface for PCM and Normal I2S modes refer to the u-blox AT Commands Manual [3], +UI2S AT
command.
The internal audio processing system is summarized in Figure 26: external digital audio devices can
be interfaced directly to the digital signal processing part via the I2S digital interface. Audio
processing can be controlled by AT commands: see Audio Interface and Audio Parameters Tuning
sections in the u-blox AT Commands Manual [3].
Figure 26: TOBY-L2 modules internal audio processing system block diagram
☞ The internal audio processing system of TOBY-L2 modules does not support the side-tone.
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Function
Description
Default GPIO
Configurable GPIOs
Network status indication
Network status: registered home network,
registered roaming, data transmission, no service
--
All
SIM card detection
SIM card physical presence detection
GPIO5
GPIO5
SIM card hot
insertion/removal
Enable / disable SIM interface upon detection of
external SIM card physical insertion / removal
--
GPIO5
I2S digital audio interface17
I2S digital audio interface
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
Master clock output17
13 MHz / 26 MHz clock output for an external device
as an audio codec
GPIO6
GPIO6
Wi-Fi enable
Enable/disable the supply of the external u-blox
Wi-Fi module connected to the cellular module
GPIO1
All
DSR
UART data set ready output
DSR
DSR
DTR
UART data terminal ready input
DTR
DTR
DCD
UART data carrier detect output
DCD
DCD
RI
UART ring indicator output
RI
RI
General purpose input
Input to sense high or low digital level
--
All
General purpose output
Output to set the high or the low digital level
GPIO4
All
Pin disabled
Tri-state with an internal active pull-down enabled
GPIO2, GPIO3
All
17
1.11 General Purpose Input/Output
☞ GPIOs are not supported by TOBY-L2 modules “00”, “01” and “60” product versions, except for the
Wireless Wide Area Network status indication configured on GPIO1 pin.
☞ GPIOs are not available on MPCI-L2 series modules.
TOBY-L2 series modules include 14 pins (GPIO1-GPIO6, I2S_TXD, I2S_RXD, I2S_CLK, I2S_WA, DTR,
DSR, DCD, RI) that can be configured as General Purpose Input/Output or to provide custom functions
via u-blox AT commands (see the u-blox AT Commands Manual [3], +UGPIOC, +UGPIOR, +UGPIOW AT
commands), as summarized in Table 13.
Table 13: TOBY-L2 series GPIO custom functions configuration
Not supported by TOBY-L201-02S and TOBY-L220-62S product versions.
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Baseband
Processor
20
W_DISABLE#
MPCI-L2 series
3.3Vaux
W_DISABLE#
22k
1.12 Mini PCIe specific signals (W_DISABLE#, LED_WWAN#)
☞ Mini PCI Express specific signals (W_DISABLE#, LED_WWAN#) are not available on TOBY-L2
series.
MPCI-L2 series modules include the W_DISABLE# active-low input signal to disable the radio
operations as specified by the PCI Express Mini Card Electromechanical Specification [16].
As described in Figure 27, the W_DISABLE# input is equipped with an internal pull-up to the 3.3Vaux
supply. The W_DISABLE# input detailed electrical characteristics are described in the MPCI-L2 series
Data Sheet [2].
Figure 27: MPCI-L2 series modules W_DISABLE# input circuit description
MPCI-L2 series modules include the LED_WWAN# active-low open drain output to provide the
Wireless Wide Area Network status indication as specified by the PCI Express Mini Card
Electromechanical Specification [16].
☞ For more electrical characteristics details see the MPCI-L2 Data Sheet [2].
1.13 Reserved pins (RSVD)
☞ Pins reserved for future use, marked as RSVD, are not available on MPCI-L2 series.
TOBY-L2 series modules have pins reserved for future use, marked as RSVD: they can all be left
unconnected on the application board, except the RSVD pin number 6 that must be externally
connected to ground.
1.14 Not connected pins (NC)
☞ Pins internally not connected, marked as NC, are not available on TOBY-L2 series.
MPCI-L2 series modules have pins internally not connected, marked as NC: they can be left
unconnected or they can be connected on the application board according to any application
requirement, given that none function is provided by the modules over these pins.
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1.15 System features
1.15.1 Network indication
☞ MPCI-L2 series modules include the LED_WWAN# active-low open drain output to provide the
Wireless Wide Area Network status indication as per PCI Express Mini Card Electromechanical
Specification [16].
☞ GPIOs are not supported by TOBY-L2 modules “00”, “01”, “60” product versions, but the Wireless
Wide Area Network status indication is by default configured on the GPIO1 pin.
The GPIO1 can be configured by the AT+UGPIOC command (for further details see the u-blox AT
Commands Manual [3]), to indicate network status as described below:
No service (no network coverage or not registered)
Registered 2G / 3G / LTE home network
Registered 2G / 3G / LTE visitor network (roaming)
Call enabled (RF data transmission / reception)
1.15.2 Antenna supervisor
☞ Antenna supervisor (i.e. antenna detection) is not available on MPCI-L2 series.
☞ Antenna supervisor (i.e. antenna detection) is not supported by TOBY-L2 series modules “00”, “01”
and “60” product versions.
The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as
optional feature that can be implemented if the application requires it. The antenna supervisor is
forced by the +UANTR AT command (see the u-blox AT Commands Manual [3] for more details).
The requirements to achieve antenna detection functionality are the following:
an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
an antenna detection circuit must be implemented on the application board
See section 1.7.2 for detailed antenna detection interface functional description, and see section 2.4.2
for detection circuit on application board and diagnostic circuit on antenna assembly design-in.
1.15.3 Jamming detection
☞ Congestion detection (i.e. jamming detection) is not supported by “00”, “01”, “02” “03”, “60” and
“62” product versions.
In real network situations modules can experience various kind of out-of-coverage conditions: limited
service conditions when roaming to networks not supporting the specific SIM, limited service in cells
which are not suitable or barred due to operators’ choices, no cell condition when moving to poorly
served or highly interfered areas. In the latter case, interference can be artificially injected in the
environment by a noise generator covering a given spectrum, thus obscuring the operator’s carriers
entitled to give access to the LTE/3G/2G service.
The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT
command: the feature consists of detecting an anomalous source of interference and signaling the
start and stop of such conditions to the host application processor with an unsolicited indication,
which can react appropriately by e.g. switching off the radio transceiver of the module (i.e. configuring
the module in “airplane mode” by means of the +CFUN AT command) in order to reduce power
consumption and monitoring the environment at constant periods (for more details see the u-blox AT
Commands Manual [3]).
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1.15.4 IP modes of operation
IP modes of operation refer to the TOBY-L2 and MPCI-L2 series modules configuration related to the
network IP termination and network interfaces settings in general. IP modes of operation are the
following:
Bridge mode: In bridge mode the module acts as a cellular modem dongle connected to the host
over serial interface. The IP termination of the network is placed on the host IP stack. The module
is configured as a bridge which means the network IP address is assigned to the host (host IP
termination).
Router mode: In router mode the module acts as a cellular modem router which means the IP
termination of the network is placed on the internal IP stack of the module (on-target IP
termination). In particular, in this configuration the application processor belongs to a private
network and is not aware of the mobile connectivity setup of the module.
For more details about IP modes of operation see the u-blox AT Commands Manual [3].
1.15.5 Dual stack Ipv4/Ipv6
TOBY-L2 and MPCI-L2 series support both Internet Protocol version 4 and Internet Protocol version 6
in parallel.
For more details about dual stack Ipv4/Ipv6 see the u-blox AT Commands Manual [3].
1.15.6 TCP/IP and UDP/IP
☞ Embedded TCP/IP and UDP/IP stack as well as Direct Link mode are not supported by the “00” and
“60” product versions.
TOBY-L2 and MPCI-L2 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP
context can be configured, established and handled via the data connection management packet
switched data commands.
TOBY-L2 and MPCI-L2 series modules provide Direct Link mode to establish a transparent end-toend communication with an already connected TCP or UDP socket via serial interfaces (USB, UART).
In Direct Link mode, data sent to the serial interface from an external application processor is
forwarded to the network and vice-versa.
For more details about embedded TCP/IP and UDP/IP functionalities see the u-blox AT Commands
Manual [3].
1.15.7 FTP
☞ Embedded FTP services as well as Direct Link mode are not supported by “00” and “60” product
versions.
TOBY-L2 and MPCI-L2 series provide embedded File Transfer Protocol (FTP) services. Files are read
and stored in the local file system of the module.
FTP files can also be transferred using FTP Direct Link:
FTP download: data coming from the FTP server is forwarded to the host processor via USB /
UART serial interfaces (for FTP without Direct Link mode the data is always stored in the module’s
Flash File System)
FTP upload: data coming from the host processor via USB / UART serial interface is forwarded to
the FTP server (for FTP without Direct Link mode the data is read from the module’s Flash File
System)
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When Direct Link is used for a FTP file transfer, only the file content pass through USB / UART serial
interface, whereas all the FTP commands handling is managed internally by the FTP application.
For more details about embedded FTP functionalities see u-blox AT Commands Manual [3].
1.15.8 HTTP
☞ Embedded HTTP services are not supported by “00” and “60” product versions.
TOBY-L2 and MPCI-L2 series modules provide the embedded Hyper-Text Transfer Protocol (HTTP)
services via AT commands for sending requests to a remote HTTP server, receiving the server
response and transparently storing it in the module’s Flash File System (FFS).
For more details about embedded HTTP functionalities see the u-blox AT Commands Manual [3].
1.15.9 SSL / TLS
☞ Embedded Secure Sockets Layer (SSL) / Transport Layer Security (TLS) protocols are not
supported by the “00”, “01”, “60”, TOBY-L201-02S and MPCI-L201-02S product versions.
TOBY-L2 and MPCI-L2 series modules support the Secure Sockets Layer (SSL) / Transport Layer
Security (TLS) with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP
protocols.
The SSL/TLS support provides different connection security aspects:
Server authentication: use of the server certificate verification against a specific trusted
certificate or a trusted certificates list
Client authentication: use of the client certificate and the corresponding private key
Data security and integrity: data encryption and Hash Message Authentication Code (HMAC)
generation
The security aspects used during a connection depend on the SSL/TLS configuration and features
supported. For a complete list of supported SSL/TLS configurations and settings see the u-blox AT
Commands Manual [3].
1.15.10 Bearer Independent Protocol
☞ BIP is not supported by the “00”, “60” product versions and by TOBY-L201-01S and MPCI-L201-01S
TOBY-L201-02S-00, MPCI-L201-02S-00 in AT&T configuration
The Bearer Independent Protocol (BIP) is a mechanism by which a cellular module provides a SIM with
access to the data bearers supported by the network. With the BIP for Over-the-Air SIM provisioning,
the data transfer from and to the SIM uses either an already active PDP context or a new PDP context
established with the APN provided by the SIM card. For more details, see the u-blox AT Commands
Manual [3].
1.15.11 Wi-Fi integration
☞ u-blox short range communication Wi-Fi modules integration is not available for MPCI-L2 series
modules.
☞ u-blox short range communication Wi-Fi modules integration is not supported by the TOBY-L2
series modules “00”, “01” and “60” product versions.
Full access to u-blox short range communication Wi-Fi modules is available through a dedicated SDIO
interface (see sections 1.9.4 and 2.6.4). This means that combining a TOBY-L2 series cellular module
with a u-blox short range communication module gives designers full access to the Wi-Fi module
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directly via the cellular module, so that a second interface connected to the Wi-Fi module is not
necessary.
AT commands via the AT interfaces of the cellular module (UART, USB) allows a full control of the WiFi module from any host processor, because Wi-Fi control messages are relayed to the Wi-Fi module
via the dedicated SDIO interface (for more details, see the Wi-Fi AT commands in the u-blox AT
Commands Manual [3]).
All the management software for Wi-Fi module operations runs inside the cellular module in addition
to those required for cellular-only operation: Wi-Fi driver, Web User Interface (WebUI), Connection
Config Manager.
For more details, see the Wi-Fi / Cellular Integration Application Note [15].
1.15.12 Firmware update Over AT (FOAT)
This feature allows upgrading the module firmware over USB / UART serial interfaces, using AT
commands.
The +UFWUPD AT command triggers a reboot followed by the upgrade procedure at specified a
baud rate
A special boot loader on the module performs firmware installation, security verifications and
module reboot
Firmware authenticity verification is performed via a security signature during the download. The
firmware is then installed, overwriting the current version. In case of power loss during this phase,
the boot loader detects a fault at the next wake-up, and restarts the firmware download. After
completing the upgrade, the module is reset again and wakes-up in normal boot
For more details about Firmware update Over AT procedure see the Firmware Update Application
Note [6] and the u-blox AT Commands Manual [3], +UFWUPD AT command.
1.15.13 Firmware update Over The Air (FOTA)
☞ Firmware update Over The Air (FOTA) is not supported by “00” and “60” product versions.
This feature allows upgrading the module firmware over the LTE/3G/2G air interface.
In order to reduce the amount of data to be transmitted over the air, the implemented FOTA feature
requires downloading only a “delta file” instead of the full firmware. The delta file contains only the
differences between the two firmware versions (old and new), and is compressed. The firmware
update procedure can be triggered using dedicated AT command with the delta file stored in the
module file system via over the air FTP.
For more details about Firmware update Over The Air procedure see the Firmware Update Application
Note [6] and the u-blox AT Commands Manual [3], +UFWINSTALL AT command.
1.15.14 Smart temperature management
☞ Smart temperature management is not supported by “00”, “01” and “60” product versions.
Cellular modules – independent of the specific model – always have a well defined operating
temperature range. This range should be respected to guarantee full device functionality and long life
span.
Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the
device is located near a heating/cooling source, if there is/isn’t air circulating, etc.
The module itself can also influence the environmental conditions; such as when it is transmitting at
full power. In this case its temperature increases very quickly and can raise the temperature nearby.
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Warning
area
t
-1
t
+1
t
+2
t
-2
Valid temperature range
Safe
area
Dangerous
area
Dangerous
area
Warning
area
The best solution is always to properly design the system where the module is integrated.
Nevertheless an extra check/security mechanism embedded into the module is a good solution to
prevent operation of the device outside of the specified range.
Smart Temperature Supervisor (STS)
The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command.
See the u-blox AT Commands Manual [3] for more details.
The cellular module measures the internal temperature (Ti) and its value is compared with predefined
thresholds to identify the actual working temperature range.
☞ Temperature measurement is done inside the cellular module: the measured value could be
different from the environmental temperature (Ta).
Figure 28: Temperature range and limits
The entire temperature range is divided into sub-regions by limits (see Figure 28) named t-2, t-1, t+1 and
t+2.
Within the first limit, (t
< Ti < t+1), the cellular module is in the normal working range, the Safe
-1
Area
In the Warning Area, (t
< Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid
-2
temperature range, but the measured temperature approaches the limit (upper or lower). The
module sends a warning to the user (through the active AT communication interface), which can
take, if possible, the necessary actions to return to a safer temperature range or simply ignore the
indication. The module is still in a valid and good working condition
Outside the valid temperature range, (Ti < t
) or (Ti > t+2), the device is working outside the
-2
specified range and represents a dangerous working condition. This condition is indicated and the
device shuts down to avoid damage
☞ For security reasons the shutdown is suspended in case an emergency call in progress. In this case
the device will switch off at call termination.
☞ The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If
the feature is disabled there is no embedded protection against disallowed temperature
conditions.
Figure 29 shows the flow diagram implemented for the Smart Temperature Supervisor.
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IF STS
enabled
Read
temperature
IF
(t-1<Ti<t+1)
IF
(t-2<Ti<t+2)
Send
notification
(warning)
Send
notification
(dangerous)
Wait emergency
call termination
IF
emerg.
call in
progress
Shut the device
down
Yes
No
Yes
Yes
No
No
No
Yes
Send
shutdown
notification
Feature enabled
(full logic or
indication only)
IF
Full Logic
Enabled
Feature disabled:
no action
Temperature is
within normal
operating range
Yes
Tempetature
is within
warning area
Tempetature is
outside valid
temperature range
No
Featuere enabled
in full logic mode
Feature enabled in
indication only mode:
no further actions
Send
notification
(safe)
Previously
outside of
Safe Area
Tempetature
is back to
safe area
No
No
further
actions
Yes
Figure 29: Smart Temperature Supervisor (STS) flow diagram
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Symbol
Parameter
Temperature
Remarks
t-2
Low temperature shutdown
–40 °C
Equal to the absolute minimum temperature rating for the
wireless module (the lower limit of the extended temperature
range)
t-1
Low temperature warning
–30 °C
10°C above t-2
t+1
High temperature warning
+77 °C
20°C below t+2. The higher warning area for upper range ensures
that any countermeasures used to limit the thermal heating will
become effective, even considering some thermal inertia of the
complete assembly.
T+2
High temperature shutdown
+97 °C*
Equal to the internal temperature Ti measured in the worst case
operating condition at typical supply voltage when the ambient
temperature Ta in the reference setup** equals the absolute
maximum temperature rating (upper limit of the extended
temperature range)
* +90 °C for TOBY-L201-02S and MPCI-L201-02S product versions
** Module mounted on a 79 mm x 62 mm x 1.46 mm 4-Layers PCB with a high coverage of copper within climatic chamber
Threshold Definitions
When the application of cellular module operates at extreme temperatures with Smart Temperature
Supervisor enabled, the user should note that outside the valid temperature range the device will
automatically shut down as described above.
The input for the algorithm is always the temperature measured within the cellular module (Ti,
internal). This value can be higher than the working ambient temperature (Ta, ambient), as (for
example) during transmission at maximum power a significant fraction of DC input power is
dissipated as heat This behavior is partially compensated by the definition of the upper shutdown
threshold (t+2) that is slightly higher than the declared environmental temperature limit.
The temperature thresholds are defined according the Table 14.
Table 14: Thresholds definition for Smart Temperature Supervisor
☞ The sensor measures board temperature inside the shields, which can differ from ambient
temperature.
1.15.15 SIM Access Profile (SAP)
☞ Not supported by “00”, “01”, “02”, “60” and “62” product versions.
SIM access profile (SAP) feature allows cellular modules to access and use a remote (U)SIM card
instead of the local SIM card directly connected to the module (U)SIM interface.
The modules provide a dedicated USB SAP channel for communication with the remote (U)SIM card.
The communication between u-blox cellular modules and the remote SIM is conformed to
client-server paradigm: the module is the SAP client establishing a connection and performing data
exchange to an SAP server directly connected to the remote SIM that is used by the module for cellular
network operations. The SAP communication protocol is based on the SIM Access Profile
Interoperability Specification [29].
☞ u-blox cellular modules do not support SAP server role: the module acts as SAP client only.
A typical application using the SAP feature is the scenario where a device such as an embedded carphone with an integrated TOBY-L2 module uses a remote SIM included in an external user device (e.g.
a simple SIM card reader or a portable phone), which is brought into the car. The car-phone accesses
the cellular network using the remote SIM in the external device.
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Device including TOBY-L2
Cellular
Interface
SAP
Serial interface
(USB SAP channel)
Local SIM
(optional)
TOBY-L2
SAP client
Application
processor
Device including SIM
SAP
Serial interface
Remote SIM
Mobile
Equipment
SAP Server
Device including TOBY-L2
SAP
Serial interface
(USB SAP channel)
Cellular
Interface
Local SIM
(optional)
TOBY-L2
SAP client
Application
processor
SAP
Bluetooth
interface
Bluetooth
Transceiver
Device including SIM
Remote SIM
Mobile
Equipment
SAP Server
Bluetooth
transceiver
u-blox cellular modules, acting as an SAP client, can be connected to an SAP server by a completely
wired connection, as shown in Figure 30.
Figure 30: Remote SIM access via completely wired connection
As stated in the SIM Access Profile Interoperability Specification [29], the SAP client can be
connected to the SAP server by means of a Bluetooth wireless link, using additional Bluetooth
transceivers. In this case, the application processor wired to TOBY-L2 modules establishes and
controls the Bluetooth connection using the SAP profile, and routes data received over a serial
interface channel to data transferred over a Bluetooth interface and vice versa, as shown in Figure 31.
Figure 31: Remote SIM access via Bluetooth and wired connection
The application processor can start an SAP connection negotiation between TOBY-L2 module SAP
client and an SAP server using a custom AT command (for more details see the u-blox AT Commands
Manual [3]).
While the connection with the SAP server is not fully established, the TOBY-L2 module continues to
operate with the attached (local) SIM, if present. Once the connection is established and negotiated,
the module performs a detach operation from the local SIM followed by an attach operation to the
remote one. Then the remotely attached SIM is used for any cellular network operation.
URC indications are provided to inform the user about the state of both the local and remote SIM. The
insertion and the removal of the local SIM card are notified if a proper card presence detection circuit
using the SIM_DET pin of TOBY-L2 modules is implemented as shown in the section 2.5, and if the
related “SIM card detection” and “SIM hot insertion/removal” functions are enabled by AT commands
(for more details see u-blox AT Commands Manual [3], +UGPIOC, +UDCONF=50 AT commands).
Upon SAP deactivation, the TOBY-L2 modules perform a detach operation from the remote SIM
followed by an attach operation to the local one, if present.
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1.15.16 Power saving
The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV
command (for the complete description of the AT+UPSV command, see the u-blox AT Commands
Manual [3]).
When power saving is enabled, the module automatically enters the low power idle-mode whenever
possible, reducing current consumption (see section 1.5.1.5, TOBY-L2 Data Sheet [1] and MPCI-L2
Data Sheet [2]).
During the low power idle-mode, the module is not ready to communicate with an external device, as
it is configured to reduce power consumption. The module wakes up from low power idle-mode to
active-mode in the following events:
Automatic periodic monitoring of the paging channel for the reception of the paging block sent by
the base station according to network conditions (see section 1.5.1.5)
The connected USB host forces a remote wakeup of the module as USB device (see section 1.9.1.4)
Automatic periodic enable of the UART interface to receive / send data, with AT+UPSV=1 (see
1.9.2.4)
Data received on UART interface, with HW flow control disabled and power saving enabled (see
1.9.2.4)
RTS input set ON by the host DTE, with HW flow control disabled and AT+UPSV=2 (see 1.9.2.4)
DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.2.4)
The connected SDIO device forces a wakeup of the module as SDIO host (see 1.9.4)
A preset RTC alarm occurs (see u-blox AT Commands Manual [3], AT+CALA)
For the definition and the description of TOBY-L2 and MPCI-L2 series modules operating modes,
including the events forcing transitions between the different operating modes, see the section 1.4.
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2 Design-in
2.1 Overview
For an optimal integration of TOBY-L2 and MPCI-L2 series modules in the final application board
follow the design guidelines stated in this section.
Every application circuit must be properly designed to guarantee the correct functionality of the
relative interface, however a number of points require high attention during the design of the
application device.
The following list provides a rank of importance in the application design, starting from the highest
relevance:
1. Module antenna connection: ANT1, ANT2 and ANT_DET.
Antenna circuit directly affects the RF compliance of the device integrating a TOBY-L2 and
MPCI-L2 series module with applicable certification schemes. Very carefully follow the
suggestions provided in the relative section 2.4 for schematic and layout design.
2. Module supply: VCC or 3.3Vaux and GND pins.
The supply circuit affects the RF compliance of the device integrating a TOBY-L2 and MPCI-L2
series module with applicable required certification schemes as well as antenna circuit design.
Very carefully follow the suggestions provided in the relative section 2.2.1 for schematic and
layout design.
3. USB interface: USB_D+, USB_D- pins.
Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully
follow the suggestions provided in the relative section 2.6.1 for schematic and layout design.
4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST or UIM_PWR, UIM_DATA, UIM_CLK,
UIM_RESET pins.
Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling.
Carefully follow the suggestions provided in the relative section 2.5 for schematic and layout
design.
5. SDIO interface: SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD pins.
Accurate design is required to guarantee SDIO interface functionality. Carefully follow the
suggestions provided in the relative section 2.6.4 for schematic and layout design.
6. System functions: RESET_N or PERST#, PWR_ON pins.
Accurate design is required to guarantee that the voltage level is well defined during operation.
Carefully follow the suggestions provided in the relative section 2.3 for schematic and layout
design.
7. Other supplies: V_BCKP RTC supply and V_INT generic digital interfaces supply.
Accurate design is required to guarantee proper functionality. Follow the suggestions provided
in the corresponding sections 2.2.2 and 2.2.3 for schematic and layout design.
8. Other digital interfaces: UART, I
Reserved pins.
Accurate design is required to guarantee proper functionality. Follow the suggestions provided
in sections 2.6.2, 2.6.3, 2.7.1, 2.3.3, 2.8, 2.9 and 2.10 for schematic and layout design.
2
C, I2S, Host Select, GPIOs, Mini PCIe specific signals and
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Main Supply
Available?
Battery
Li-Ion 3.7 V
Linear LDO
Regulator
Main Supply
Voltage > 5V?
Switching Step-Down
Regulator
No, portable device
No, less than 5 V
Yes, greater than 5 V
Yes, always available
2.2 Supply interfaces
2.2.1 Module supply (VCC or 3.3Vaux)
2.2.1.1 General guidelines for VCC or 3.3Vaux supply circuit selection and design
VCC or 3.3Vaux pins are internally connected. Application design shall connect all the available pads
to the external supply to minimize the power loss due to series resistance.
GND pins are internally connected. Application design shall connect all the available pads to solid
ground on the application board, since a good (low impedance) connection to external ground can
minimize power loss and improve RF and thermal performance.
TOBY-L2 and MPCI-L2 series modules must be sourced through the VCC or the 3.3Vaux pins with a
proper DC power supply that should meet the following prerequisites to comply with the modules’
VCC or 3.3Vaux requirements summarized in Table 7.
The proper DC power supply can be selected according to application requirements (see Figure 32)
between different possible supply source types, of which most common ones are the following:
Switching regulator
Low Drop-Out (LDO) linear regulator
Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery, for TOBY-L2 series only
Primary (disposable) battery, for TOBY-L2 series only
Figure 32: VCC supply concept selection
The switching step-down regulator is the typical choice when the available primary supply source has
a nominal voltage much higher (e.g. greater than 5 V) than the operating supply voltage of TOBY-L2
and MPCI-L2 series. The use of switching step-down provides the best power efficiency for the overall
application and minimizes current drawn from the main supply source. See 2.2.1.2, 2.2.1.6, 2.2.1.9,
2.2.1.10 for specific design-in.
The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low
voltage (e.g. less or equal than 5 V). In this case the typical 90% efficiency of the switching regulator
diminishes the benefit of voltage step-down and no true advantage is gained in input current savings.
On the opposite side, linear regulators are not recommended for high voltage step-down as they
dissipate a considerable amount of energy in thermal power. See 2.2.1.3, 2.2.1.6, 2.2.1.9, 2.2.1.10 for
specific design-in.
If TOBY-L2 modules are deployed in a mobile unit where no permanent primary supply source is
available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack
directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries
with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC,
and should therefore be avoided. See 2.2.1.4, 2.2.1.6, 2.2.1.9, 2.2.1.10 for specific design-in.
Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger
circuit which is not included in the modules. The charger circuit has to be designed to prevent
over-voltage on VCC pins of the module, and it should be selected according to the application
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requirements: a DC/DC switching charger is the typical choice when the charging source has an high
nominal voltage (e.g. ~12 V), whereas a linear charger is the typical choice when the charging source
has a relatively low nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g.
~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time in the
application as possible supply source, then a proper charger / regulator with integrated power path
management function can be selected to supply the module while simultaneously and independently
charging the battery. See 2.2.1.7, 2.2.1.8 and 2.2.1.6, 2.2.1.9, 2.2.1.10 for specific design-in.
The use of a primary (not rechargeable) battery is in general uncommon, but appropriate parts can be
selected given that the most cells available are seldom capable of delivering the maximum current
specified in TOBY-L2 series Data Sheet [1] during connected-mode. Carefully evaluate the usage of
super-capacitors as supply source since aging and temperature conditions significantly affect the
actual capacitor characteristics. See 2.2.1.5 and 2.2.1.6, 2.2.1.9, 2.2.1.10 for specific design-in.
Rechargeable 3-cell Li-Ion or Li-Pol and Ni-MH chemistry batteries reach a maximum voltage that is
above the maximum rating for the 3.3Vaux supply of MPCI-L2 modules, and should be avoided. The
use of rechargeable, not-rechargeable battery or super-capacitors is very uncommon for Mini PCI
Express applications, so that these supply sources types are not considered for MPCI-L2 modules.
The usage of more than one DC supply at the same time should be carefully evaluated: depending on
the supply source characteristics, different DC supply systems can result as mutually exclusive.
The following sections highlight some design aspects for each of the supplies listed above providing
application circuit design-in compliant with the module VCC requirements summarized in Table 7.
2.2.1.2 Guidelines for supply circuit design using a switching regulator
The use of a switching regulator is suggested when the difference from the available supply rail to the
VCC or the 3.3Vaux value is high, since switching regulators provide good efficiency transforming a
12 V or greater voltage supply to the typical 3.8 V value of the VCC supply or the typical 3.3 V value of
the 3.3Vaux supply.
The characteristics of the switching regulator connected to VCC or 3.3Vaux pins should meet the
following prerequisites to comply with module VCC or 3.3Vaux requirements summarized in Table 7:
Power capability: the switching regulator with its output circuit must be capable of providing a
voltage value to the VCC or 3.3Vaux pins within the specified operating range and must be capable
of delivering to VCC or 3.3Vaux pins the maximum peak / pulse current consumption during Tx
burst at maximum Tx power specified in the TOBY-L2 or MPCI-L2 Data Sheet [1] [2].
Low output ripple: the switching regulator together with its output circuit must be capable of
providing a clean (low noise) VCC or 3.3Vaux voltage profile.
High switching frequency: for best performance and for smaller applications it is recommended
to select a switching frequency ≥ 600 kHz (since L-C output filter is typically smaller for high
switching frequency). The use of a switching regulator with a variable switching frequency or with
a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise
in the VCC or 3.3Vaux voltage profile and therefore negatively impact LTE/3G/2G modulation
spectrum performance. An additional L-C low-pass filter between the switching regulator output
to VCC or 3.3Vaux supply pins can mitigate the ripple at the input of the module, but adds extra
voltage drop due to resistive losses on series inductors.
PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM)
mode. While in connected-mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM
modes transitions must be avoided to reduce the noise on the VCC or 3.3Vaux voltage profile.
Switching regulators can be used that are able to switch between low ripple PWM mode and high
ripple PFM mode, provided that the mode transition occurs when the module changes status from
the idle/active-modes to connected-mode. It is permissible to use a regulator that switches from
the PWM mode to the burst or PFM mode at an appropriate current threshold
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12V
C5
R3
C4
R2
C2C1
R1
VIN
RUN
VC
RT
PG
SYNC
BD
BOOST
SW
FB
GND
6
7
10
9
5
C6
1
2
3
8
11
4
C7 C8
D1
R4
R5
L1
C3
U1
TOBY-L2 series
71
VCC
72
VCC
70
VCC
GND
12V
C5
R3
C4
R2
C2C1
R1
VIN
RUN
VC
RT
PG
SYNC
BD
BOOST
SW
FB
GND
6
7
10
9
5
C6
1
2
3
8
11
4
C7 C8
D1
R6
R5
L1
C3
U1
MPCI-L2 series
24
3.3Vaux
39
3.3Vaux
2
3.3Vaux
GND
41
3.3Vaux
52
3.3Vaux
Reference
Description
Part Number – Manufacturer
C1
10 µ F Capacitor Ceramic X7R 5750 15% 50 V
C5750X7R1H106MB – TDK
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 – Murata
C3
680 pF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71H681KA01 – Murata
C4
22 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1H220JZ01 – Murata
C5
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 – Murata
C6
470 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E474KA12 – Murata
C7
22 µ F Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 – Murata
C8
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
D1
Schottky Diode 40 V 3 A
MBRA340T3G – ON Semiconductor
L1
10 µ H Inductor 744066100 30% 3.6 A
744066100 – Wurth Electronics
R1
470 k Resistor 0402 5% 0.1 W
2322-705-87474-L – Yageo
R2
15 k Resistor 0402 5% 0.1 W
2322-705-87153-L – Yageo
R3
22 k Resistor 0402 5% 0.1 W
2322-705-87223-L – Yageo
R4
390 k Resistor 0402 1% 0.063 W
RC0402FR-07390KL – Yageo
R5
100 k Resistor 0402 5% 0.1 W
2322-705-70104-L – Yageo
R6
330 k Resistor 0402 1% 0.063 W
RC0402FR-07330KL – Yageo
U1
Step-Down Regulator MSOP10 3.5 A 2.4 MHz
LT3972IMSE#PBF – Linear Technology
Figure 33 and Table 15 show an example of a high reliability power supply circuit, where the module
VCC or 3.3Vaux input is supplied by a step-down switching regulator capable of delivering maximum
current with low output ripple and with fixed switching frequency in PWM mode operation greater
than 1 MHz.
Figure 33: Example of high reliability VCC and 3.3Vaux supply application circuit using a step-down regulator
Table 15: Components for high reliability VCC and 3.3Vaux supply application circuit using a step-down regulator
UBX-13004618 - R28 Design-in Page 71 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
12V
R5
C6C1
VCC
INH
FSW
SYNC
OUT
GND
2
6
3
1
7
8
C3
C2
D1
R1
R2
L1
U1
GND
FB
COMP
5
4
R3
C4
R4
C5
71
VCC
72
VCC
70
VCC
12V
R5
C6C1
VCC
INH
FSW
SYNC
OUT
GND
2
6
3
1
7
8
C3
C2
D1
R6
R7
L1
U1
GND
FB
COMP
5
4
R3
C4
R4
C5
MPCI-L2 series
24
3.3Vaux
39
3.3Vaux
2
3.3Vaux
41
3.3Vaux
52
3.3Vaux
Reference
Description
Part Number – Manufacturer
C1
22 µ F Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 – Murata
C2
100 µ F Capacitor Tantalum B_SIZE 20% 6.3V 15m
T520B107M006ATE015 – Kemet
C3
5.6 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H562KA88 – Murata
C4
6.8 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H682KA88 – Murata
C5
56 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H560JA01 – Murata
C6
220 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E224KA88 – Murata
D1
Schottky Diode 25V 2 A
STPS2L25 – STMicroelectronics
L1
5.2 µ H Inductor 30% 5.28A 22 m
MSS1038-522NL – Coilcraft
R1
4.7 k Resistor 0402 1% 0.063 W
RC0402FR-074K7L – Yageo
R2
910 Resistor 0402 1% 0.063 W
RC0402FR-07910RL – Yageo
R3
82 Resistor 0402 5% 0.063 W
RC0402JR-0782RL – Yageo
R4
8.2 k Resistor 0402 5% 0.063 W
RC0402JR-078K2L – Yageo
R5
39 k Resistor 0402 5% 0.063 W
RC0402JR-0739KL – Yageo
R6
1.5 k Resistor 0402 1% 0.063 W
RC0402FR-071K5L – Yageo
R7
330 Resistor 0402 1% 0.063 W
RC0402FR-07330RL – Yageo
U1
Step-Down Regulator 8-VFQFPN 3 A 1 MHz
L5987TR – ST Microelectronics
Figure 34 and the components listed in Table 16 show an example of a low cost power supply circuit,
where the VCC module supply is provided by a step-down switching regulator capable of delivering to
VCC pins the specified maximum peak / pulse current, transforming a 12 V supply input.
Figure 34: Example of low cost VCC and 3.3Vaux supply application circuit using step-down regulator
Table 16: Components for low cost VCC and 3.3Vaux supply application circuit using a step-down regulator
UBX-13004618 - R28 Design-in Page 72 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
5V
C1 R1
IN OUT
ADJ
GND
1
2
4
5
3
C2R2
R3
U1
SHDN
TOBY-L2 series
71
VCC
72
VCC
70
VCC
GND
C3
5V
C1 R1
IN OUT
ADJ
GND
1
2
4
5
3
C2R4
R5
U1
SHDN
MPCI-L2 series
GND
C3
24
3.3Vaux
39
3.3Vaux
2
3.3Vaux
41
3.3Vaux
52
3.3Vaux
Reference
Description
Part Number – Manufacturer
C1, C2
10 µ F Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 – Murata
C3
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
R1
47 k Resistor 0402 5% 0.1 W
RC0402JR-0747KL – Yageo Phycomp
R2
9.1 k Resistor 0402 5% 0.1 W
RC0402JR-079K1L – Yageo Phycomp
R3
3.9 k Resistor 0402 5% 0.1 W
RC0402JR-073K9L – Yageo Phycomp
R4
3.3 k Resistor 0402 5% 0.1 W
RC0402JR-073K3L – Yageo Phycomp
R5
1.8 k Resistor 0402 5% 0.1 W
RC0402JR-071K8L – Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LT1764AEQ#PBF – Linear Technology
2.2.1.3 Guidelines for supply circuit design using a Low Drop-Out linear regulator
The use of a linear regulator is suggested when the difference from the available supply rail and the
VCC or the 3.3Vaux value is low. The linear regulators provide high efficiency when transforming a 5
VDC supply to a voltage value within the module VCC or 3.3Vaux normal operating range.
The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC or 3.3Vaux pins
should meet the following prerequisites to comply with the module VCC or 3.3Vaux requirements
summarized in Table 7:
Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a
voltage value to the VCC or 3.3Vaux pins within the specified operating range and must be capable
of delivering to VCC or 3.3Vaux pins the maximum peak / pulse current consumption during Tx
burst at maximum Tx power specified in TOBY-L2 or MPCI-L2 Data Sheet [1] [2].
Power dissipation: the power handling capability of the linear regulator must be checked to limit
its junction temperature to the maximum rated range (i.e. check the voltage drop from the max
input voltage to the minimum output voltage to evaluate the power dissipation of the regulator).
Figure 35 and the components listed in Table 17 show an example of a power supply circuit, where the
VCC or 3.3Vaux module supply is provided by an LDO linear regulator capable of delivering the required
current, with proper power handling capability.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC or 3.3Vaux normal operating range (e.g. ~4.1 V for the
VCC and ~3.44 V for the 3.3Vaux as in the circuits described in Figure 35 and Table 17). This reduces
the power on the linear regulator and improves the thermal design of the circuit.
Figure 35: Suggested schematic design for the VCC and 3.3Vaux supply application circuit using an LDO linear regulator
Table 17: Suggested components for VCC and 3.3Vaux supply application circuit using an LDO linear regulator
UBX-13004618 - R28 Design-in Page 73 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
5V
C1
IN OUT
ADJ
GND
1
2
4
5
3
C2R1
R2
U1
EN
TOBY-L2 series
71
VCC
72
VCC
70
VCC
GND
C3
5V
C1
IN OUT
ADJ
GND
1
2
4
5
3
C2R3
R4
U1
EN
MPCI-L2 series
GND
C3
24
3.3Vaux
39
3.3Vaux
2
3.3Vaux
41
3.3Vaux
52
3.3Vaux
Reference
Description
Part Number – Manufacturer
C1, C2
10 µ F Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 – Murata
C3
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
R1
27 k Resistor 0402 5% 0.1 W
RC0402JR-0727KL – Yageo Phycomp
R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L – Yageo Phycomp
R3
12 k Resistor 0402 5% 0.1 W
RC0402JR-0712KL – Yageo Phycomp
R4
2.7 k Resistor 0402 5% 0.1 W
RC0402JR-072K7L – Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LP38501ATJ-ADJ/NOPB – Texas Instrument
Figure 36 and the components listed in Table 18 show an example of a low cost power supply circuit,
where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified
highest peak / pulse current, with proper power handling capability. The regulator described in this
example supports a limited input voltage range and it includes internal circuitry for current and
thermal protection.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit
described in Figure 36 and Table 18). This reduces the power on the linear regulator and improves the
whole thermal design of the supply circuit.
Figure 36: Suggested schematic design for the VCC and 3.3Vaux supply application circuit using an LDO linear regulator
Table 18: Suggested components for VCC voltage supply application circuit using an LDO linear regulator
2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following
prerequisites to comply with the module VCC requirements summarized in Table 7:
Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output
circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum
peak current consumption during Tx burst at maximum Tx power specified in TOBY-L2 series Data
Sheet [1] and must be capable of extensively delivering a DC current as the maximum average
current consumption specified in TOBY-L2 series Data Sheet [1]. The maximum discharge current
is not always reported in battery data sheets, but the maximum DC discharge current is typically
almost equal to the battery capacity in Amp-hours divided by 1 hour.
DC series resistance: the rechargeable battery with its output circuit must be capable of avoiding
a VCC voltage drop below the operating range summarized in Table 7 during transmit bursts.
UBX-13004618 - R28 Design-in Page 74 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the
following prerequisites to comply with the module VCC requirements summarized in Table 7:
Maximum pulse and DC discharge current: the non-rechargeable battery with its related output
circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum
peak current consumption during Tx burst at maximum Tx power specified in TOBY-L2 series Data
Sheet [1] and must be capable of extensively delivering a DC current as the maximum average
current consumption specified in TOBY-L2 series Data Sheet [1]. The maximum discharge current
is not always reported in battery data sheets, but the maximum DC discharge current is typically
almost equal to the battery capacity in Amp-hours divided by 1 hour.
DC series resistance: the non-rechargeable battery with its output circuit must be capable of
avoiding a VCC voltage drop below the operating range summarized in Table 7 during transmit
bursts.
2.2.1.6 Additional guidelines for VCC or 3.3Vaux supply circuit design
To reduce voltage drops, use a low impedance power source. The series resistance of the power supply
lines (connected to the modules’ VCC / 3.3Vaux and GND pins) on the application board and battery
pack should also be considered and minimized: cabling and routing must be as short as possible to
minimize power losses.
Three pins are allocated to VCC supply and five pins to 3.3Vaux supply. Several pins are designated
for GND connection. Even if all the VCC / 3.3Vaux pins and all the GND pins are internally connected
within the module, it is recommended to properly connect all of them to supply the module to minimize
series resistance losses.
To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a GSM
call (when current consumption on the VCC or 3.3Vaux supply can rise up as specified in TOBY-L2
series Data Sheet [1] or in MPCI-L2 series Data Sheet [2]), place a bypass capacitor with large
capacitance (at least 100 µF) and low ESR near the VCC pins, for example:
330 µF capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)
To reduce voltage ripple and noise, improving RF performance especially if the application device
integrates an internal antenna, place the following bypass capacitors near the VCC / 3.3Vaux pins:
68 pF 0402 capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata
GRM1555C1H680J) to filter EMI in the RF low frequencies bands
15 pF 0402 capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata
GRM1555C1E150J) to filter EMI in the RF high frequencies bands
8.2 pF 0402 capacitor with Self-Resonant Frequency in 2500/2600 MHz range (e.g. Murata
GRM1555C1H8R2D) to filter EMI in the RF very high frequencies band
10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data
sources
100 nF capacitor (e.g. Murata GRM155R61C104K) to filter digital logic noise from clocks and data
sources
A suitable series ferrite bead can be properly placed on the VCC / 3.3Vaux line for additional noise
filtering if required by the specific application according to the whole application board design.
☞ The necessity of each part depends on the specific design, but it is recommended to provide all
the bypass capacitors described in Figure 37 / Table 19 if the application device integrates an
internal antenna.
UBX-13004618 - R28 Design-in Page 75 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
C2
GND
C3 C4
TOBY-L2 series
71
VCC
72
VCC
70
VCC
C1 C5 C6
3V8
C2
GND
C3 C4
MPCI-L2 series
C1 C5 C6
3V3
24
3.3Vaux
39
3.3Vaux
2
3.3Vaux
41
3.3Vaux
52
3.3Vaux
Reference
Description
Part Number – Manufacturer
C1
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 – Murata
C2
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 – Murata
C3
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 – Murata
C4
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 – Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 – Murata
C6
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
Figure 37: Suggested schematic for the VCC / 3.3Vaux bypass capacitors to reduce ripple / noise on supply voltage profile
Table 19: Suggested components to reduce ripple / noise on VCC / 3.3Vaux
☞ ESD sensitivity rating of the VCC / 3.3Vaux supply pins is 1 kV (HBM according to JESD22-A114).
2.2.1.7 Guidelines for battery charging circuit
TOBY-L2 modules do not have an on-board charging circuit. Figure 38 provides an example of a
battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer)
cell.
In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse
and DC discharge current capabilities and proper DC series resistance, is directly connected to the
VCC supply input of TOBY-L2 module. Battery charging is completely managed by the
STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges
as a linear charger the battery, in three phases:
Pre-charge constant current (active when the battery is deeply discharged): the battery is
Fast-charge constant current: the battery is charged with the maximum current, configured by
UBX-13004618 - R28 Design-in Page 76 of 164
Higher protection level can be required if the line is externally accessible on the application board,
e.g. if accessible battery connector is directly connected to the supply pins. Higher protection level
can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to
accessible point.
charged with a low current, set to 10% of the fast-charge current
the value of an external resistor to a value suitable for USB power source (~500 mA)
TOBY-L2 and MPCI-L2 series - System Integration Manual
C5 C8C7C6 C9
GND
TOBY-L2 series
71
VCC
72
VCC
70
VCC
+
USB
C3
R4
θ
U1
IUSB
IAC
IEND
TPRG
SD
VIN
VINSNS
MODE
ISEL
C2C1
5V0
TH
GND
VOUT
VOSNS
VREF
R1
R2
R3
Li-Ion/Li-Pol
Battery Pack
D1
B1
C4
Li-Ion/Li-Polymer
Battery Charger IC
C10
Reference
Description
Part Number – Manufacturer
B1
Li-Ion (or Li-Polymer) battery pack with 470 NTC
Various manufacturer
C1, C4
1 µ F Capacitor Ceramic X7R 0603 10% 16 V
GRM188R71C105KA12 – Murata
C2, C6
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 – Murata
C3
1 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H102KA01 – Murata
C5
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
C7
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 – Murata
C8
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 – Murata
C9
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 – Murata
C10
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 – Murata
D1
Low Capacitance ESD Protection
USB0002RP or USB0002DP – AVX
R1, R2
24 k Resistor 0402 5% 0.1 W
RC0402JR-0724KL – Yageo Phycomp
R3
3.3 k Resistor 0402 5% 0.1 W
RC0402JR-073K3L – Yageo Phycomp
R4
1.0 k Resistor 0402 5% 0.1 W
RC0402JR-071K0L – Yageo Phycomp
U1
Single Cell Li-Ion (or Li-Polymer) Battery Charger IC
L6924U – STMicroelectronics
Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the
L6924U starts to reduce the current until the charge termination is done. The charging process
ends when the charging current reaches the value configured by an external resistor to ~15 mA or
when the charging timer reaches the value configured by an external capacitor to ~9800 s
Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature
to protect the battery from operating under unsafe thermal conditions.
Alternatively the L6924U, providing input voltage range up to 12 V, can charge from an AC wall
adapter. When a current-limited adapter is used, it can operate in quasi-pulse mode, reducing power
dissipation.
Figure 38: Li-Ion (or Li-Polymer) battery charging application circuit
Table 20: Suggested components for Li-Ion (or Li-Polymer) battery charging application circuit
2.2.1.8 Guidelines for battery charging and power path management circuit
Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a
rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply
source should implement a suitable charger / regulator with integrated power path management
function to supply the module and the whole device while simultaneously and independently charging
the battery.
Figure 39 reports a simplified block diagram circuit showing the working principle of a
charger / regulator with integrated power path management function. This component allows the
UBX-13004618 - R28 Design-in Page 77 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
GND
Power path management IC
VoutVin
θ
Li-Ion/Li-Pol
Battery Pack
GND
System
12 V
Primary
Source
Charge
controller
DC/DC
converter and
battery FET
control logic
Vbat
system to be powered by a permanent primary supply source (e.g. ~12 V) using the integrated
regulator which simultaneously and independently recharges the battery (e.g. 3.7 V Li-Pol) that
represents the back-up supply source of the system: the power path management feature permits
the battery to supplement the system current requirements when the primary supply source is not
available or cannot deliver the peak system currents.
A power management IC should meet the following prerequisites to comply with the module VCC
requirements summarized in Table 7:
High efficiency internal step down converter, compliant with the performances specified in section
2.2.1.2
Low internal resistance in the active path Vout – Vbat, typically lower than 50 m
High efficiency switch mode charger with separate power path control
Figure 39: Charger / regulator with integrated power path management circuit block diagram
Figure 40 and the components listed in Table 21 provide an application circuit example where the MPS
MP2617H switching charger / regulator with integrated power path management function provides
the supply to the cellular module. At the same time it also concurrently and autonomously charges a
suitable Li-Ion (or Li-Polymer) battery with correct pulse and DC discharge current capabilities and
the appropriate DC series resistance according to the rechargeable battery recommendations
described in section 2.2.1.4.
The MP2617H IC constantly monitors the battery voltage and selects whether to use the external
main primary supply / charging source or the battery as supply source for the module, and starts a
charging phase accordingly.
The MP2617H IC normally provides a supply voltage to the module regulated from the external main
primary source allowing immediate system operation even under missing or deeply discharged
battery: the integrated switching step-down regulator is capable to provide up to 3 A output current
with low output ripple and fixed 1.6 MHz switching frequency in PWM mode operation. The module
load is satisfied in priority, then the integrated switching charger will take the remaining current to
charge the battery.
Additionally, the power path control allows an internal connection from battery to the module with a
low series internal ON resistance (40 m typical), in order to supplement additional power to the
module when the current demand increases over the external main primary source or when this
external source is removed.
Battery charging is managed in three phases:
Pre-charge constant current (active when the battery is deeply discharged): the battery is
charged with a low current, set to 10% of the fast-charge current
Fast-charge constant current: the battery is charged with the maximum current, configured by
the value of an external resistor to a value suitable for the application
UBX-13004618 - R28 Design-in Page 78 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
C10 C13
GND
C12C11
TOBY-L2 series
71
VCC
72
VCC
70
VCC
+
Primary
Source
R3
U1
ENn
ILIM
ISET
TMR
AGND
VIN
C2C1
12V
NTC
PGND
SW
SYS
BAT
C4
R1
R2
D1
θ
Li-Ion/Li-Pol
Battery Pack
B1
C5
Li-Ion/Li-Polymer Battery
Charger / Regulator with
Power Path Managment
VCC
C3 C6
L1
BST
D2
VLIM
R4
R5
C7 C8
D3
R6
SYSFB
R7
C9
C15C14
Reference
Description
Part Number – Manufacturer
B1
Li-Ion (or Li-Polymer) battery pack with 10 k NTC
Various manufacturer
C1, C5, C6
22 µ F Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 – Murata
C2, C4, C11
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 – Murata
C3
1 µ F Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E105KA12 – Murata
C7, C13
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 – Murata
C8, C14
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 – Murata
C9, C15
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 – Murata
C10
330 µ F Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 – KEMET
C12
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 – Murata
D1, D2
Low Capacitance ESD Protection
CG0402MLE-18G – Bourns
D3
Schottky Diode 40 V 3 A
MBRA340T3G - ON Semiconductor
R1, R3, R5, R7
10 k Resistor 0402 5% 1/16 W
Generic manufacturer
R2
1.0 k Resistor 0402 5% 0.1 W
Generic manufacturer
R4
22 k Resistor 0402 5% 1/16 W
Generic manufacturer
R6
26.5 k Resistor 0402 1% 1/16 W
Generic manufacturer
L1
2.2 µH Inductor 7.4 A 13 m 20%
SRN8040-2R2Y - Bourns
U1
Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator
with integrated Power Path Management function
MP2617H – Monolithic Power Systems (MPS)
Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the
current is progressively reduced until the charge termination is done. The charging process ends
when the charging current reaches the 10% of the fast-charge current or when the charging timer
reaches the value configured by an external capacitor
Using a battery pack with an internal NTC resistor, the MP2617H can monitor the battery temperature
to protect the battery from operating under unsafe thermal conditions.
Several parameters as the charging current, the charging timings, the input current limit, the input
voltage limit, the system output voltage can be easily set according to the specific application
requirements, as the actual electrical characteristics of the battery and the external supply / charging
source: proper resistors or capacitors have to be accordingly connected to the related pins of the IC.
Figure 40: Li-Ion (or Li-Polymer) battery charging and power path management application circuit
Table 21: Suggested components for Li-Ion (or Li-Polymer) battery charging and power path management application circuit
UBX-13004618 - R28 Design-in Page 79 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
2.2.1.9 Guidelines for VCC or 3.3Vaux supply layout design
Good connection of the module VCC or 3.3Vaux pins with DC supply source is required for correct RF
performance. Guidelines are summarized in the following list:
All the available VCC / 3.3Vaux pins must be connected to the DC source
VCC / 3.3Vaux connection must be as wide as possible and as short as possible
Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must
be avoided
VCC / 3.3Vaux connection must be routed through a PCB area separated from RF lines / parts,
sensitive analog signals and sensitive functional units: it is good practice to interpose at least one
layer of PCB ground between the VCC / 3.3Vaux track and other signal routing
VCC / 3.3Vaux connection must be routed as far as possible from the antenna, in particular if
embedded in the application device
Coupling between VCC / 3.3Vaux and digital lines, especially USB, must be avoided.
The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.6
should be placed close to the VCC / 3.3Vaux pins. If the main DC source is a switching DC-DC
converter, place the large capacitor close to the DC-DC output and minimize VCC / 3.3Vaux track
length. Otherwise consider using separate capacitors for DC-DC converter and module
The bypass capacitors in the pF range described in Figure 37 and Table 19 should be placed as
close as possible to the VCC / 3.3Vaux pins. This is highly recommended if the application device
integrates an internal antenna
Since VCC / 3.3Vaux input provide the supply to RF Power Amplifiers, voltage ripple at high
frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely
to happen with switching DC-DC converters, in which case it is better to select the highest
operating frequency for the switcher and add a large L-C filter before connecting to the TOBY-L2
and MPCI-L2 series modules in the worst case
If VCC / 3.3Vaux is protected by transient voltage suppressor to ensure that the voltage maximum
ratings are not exceeded, place the protecting device along the path from the DC source toward
the module, preferably closer to the DC source, otherwise protection functionality may be affected
2.2.1.10 Guidelines for grounding layout design
Good connection of the module GND pins with application board solid ground layer is required for
correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the
module.
Connect each GND pin with application board solid GND layer. It is strongly recommended that
each GND pad surrounding VCC pins have one or more dedicated via down to the application board
solid ground layer
The VCC supply current flows back to main DC source through GND as ground current: provide
adequate return path with suitable uninterrupted ground plane to main DC source
It is recommended to implement one layer of the application PCB as wide as possible ground plane
If the application board is a multilayer PCB, then all the board layers should be filled with GND plane
as much as possible and each GND area should be connected together with complete via stack
down to the main ground layer of the board. Use as many vias as possible to connect ground planes
Provide a dense line of vias at the edges of each GND area, specially along RF and high speed lines
If the whole application device is composed by more than one PCB, then it is required to provide a
good and solid ground connection between the GND areas of all the different PCBs
Good grounding of GND pads also ensures thermal heat sink. This is critical during connection,
when the real network commands the module to transmit at maximum power: proper grounding
helps prevent module overheating.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
C1
(a)
3
V_BCKP
R2
TOBY-L2 series
C2
(superCap)
(b)
3
V_BCKP
D3
TOBY-L2 series
B3
(c)
3
V_BCKP
Reference
Description
Part Number – Manufacturer
C1
100 µ F Tantalum Capacitor
GRM43SR60J107M – Murata
R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L – Yageo Phycomp
C2
70 mF Capacitor
XH414H-IV01E – Seiko Instruments
2.2.2 RTC supply output (V_BCKP)
☞ The RTC supply V_BCKP pin is not available on MPCI-L2 series modules.
2.2.2.1 Guidelines for V_BCKP circuit design
TOBY-L2 series modules provide the V_BCKP RTC supply input/output, which can be mainly used to:
Provide RTC back-up when VCC supply is removed
If RTC timing is required to run for a time interval of T [s] when VCC supply is removed, place a
capacitor with a nominal capacitance of C [µF] at the V_BCKP pin. Choose the capacitor using the
following formula:
C [µ F] = (Current_Consumption [µ A] x T [s]) / Voltage_Drop [V]
= 1.25 x T [s]
For example, a 100 µF capacitor can be placed at V_BCKP to provide RTC backup holding the V_BCKP
voltage within its valid range for around 80 s at 25 °C, after the VCC supply is removed. If a longer
buffering time is required, a 70 mF super-capacitor can be placed at V_BCKP, with a 4.7 k series
resistor to hold the V_BCKP voltage within its valid range for approximately 15 hours at 25 °C, after
the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current
due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the
V_BCKP pin after VCC supply has been provided. These capacitors allow the time reference to run
during battery disconnection.
☞ If the RTC timing is not required when the VCC supply is removed, it is not needed to connect the
Figure 41: Real time clock supply (V_BCKP) application circuits: (a) using a 100 µ F capacitor to let the RTC run for ~80 s after
VCC removal; (b) using a 70 mF capacitor to let RTC run for ~15 hours after VCC removal; (c) using a non-rechargeable battery
Table 22: Example of components for V_BCKP buffering
If very long buffering time is required to allow the RTC time reference to run during a disconnection of
the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able
to provide a proper nominal voltage and must never exceed the maximum operating voltage for
V_BCKP (specified in the Input characteristics of Supply/Power pins table in TOBY-L2 series Data
Sheet [1]). The connection of the battery to V_BCKP should be done with a suitable series resistor for
a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The
purpose of the series resistor is to limit the battery charging current due to the battery specifications,
and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been
provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to
the non-rechargeable battery.
V_BCKP pin to an external capacitor or battery. In this case the date and time are not updated
when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from
the main supply and there is no need for an external component on V_BCKP.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
V_BCKP supply output pin provides internal short circuit protection to limit start-up current and
protect the device in short circuit situations. No additional external short circuit protection is required.
☞ Do not apply loads which might exceed the limit for maximum available current from V_BCKP
supply (see TOBY-L2 series Data Sheet [1]) as this can cause malfunctions in internal circuitry.
☞ ESD sensitivity rating of the V_BCKP pin is 1 kV (HBM as per JESD22-A114). Higher protection level
could be required if the line is externally accessible and it can be achieved by mounting an ESD
protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible point.
2.2.2.2 Guidelines for V_BCKP layout design
V_BCKP supply requires careful layout: avoid injecting noise on this voltage domain as it may affect
the stability of the internal circuitry.
2.2.3 Generic digital interfaces supply output (V_INT)
☞ The generic digital interfaces supply V_INT pin is not available on MPCI-L2 series modules.
2.2.3.1 Guidelines for V_INT circuit design
TOBY-L2 series provide the V_INT digital interfaces 1.8 V supply output, which can be mainly used to:
Indicate when the module is switched on (as described in sections 1.6.1, 1.6.2)
Pull-up SIM detection signal (see section 2.5 for more details)
Supply voltage translators to connect 1.8 V module digital interfaces to 3.0 V devices (see 2.6.2)
Pull-up DDC (I
Enable external voltage regulators providing supply for external devices, as linear LDO regulators
providing the 3.3 V / 1.8 V supply rails for a u-blox ELLA-W1 series module (see section 2.6.4)
Supply an external device, as an external 1.8 V audio codec (see section 2.7.1 for more details)
V_INT supply output pin provides internal short circuit protection to limit start-up current and protect
the device in short circuit situations. No additional external short circuit protection is required.
2
C) interface signals (see section 2.6.3 for more details)
☞ Do not apply loads which might exceed the limit for maximum available current from V_INT supply
(see the TOBY-L2 series Data Sheet [1]) as this can cause malfunctions in internal circuitry.
☞ Since the V_INT supply is generated by an internal switching step-down regulator, the V_INT
voltage ripple can range as specified in the TOBY-L2 series Data Sheet [1]: it is not recommended
to supply sensitive analog circuitry without adequate filtering for digital noise.
☞ V_INT can only be used as an output: do not connect any external supply source on V_INT.
☞ ESD sensitivity rating of the V_INT supply pin is 1 kV (HBM, as per JESD22-A114). Higher protection
level could be required if the line is externally accessible and it can be achieved by mounting an
ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible point.
☞ It is recommended to provide direct access to the V_INT pin on the application board by means of
an accessible test point directly connected to the V_INT pin.
2.2.3.2 Guidelines for V_INT layout design
V_INT supply output is generated by an integrated switching step-down converter. Because of this, it
can be a source of noise: avoid coupling with sensitive signals.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
50 k
VCC
20
PWR_ON
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
TOBY-L2 series
50 k
VCC
20
PWR_ON
TP
TP
Reference
Description
Part Number – Manufacturer
ESD
Varistor array for ESD protection
CT0402S14AHSG – EPCOS
2.3 System functions interfaces
2.3.1 Module power-on (PWR_ON)
☞ The PWR_ON input pin is not available on MPCI-L2 series modules.
2.3.1.1 Guidelines for PWR_ON circuit design
TOBY-L2 series PWR_ON input is equipped with an internal active pull-up resistor to the VCC module
supply as described in Figure 42: an external pull-up resistor is not required and should not be
provided.
If connecting the PWR_ON input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD
protection should be provided close to the accessible point, as described in Figure 42 and Table 23.
☞ ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level can be required if the line is externally accessible on the application board,
e.g. if an accessible push button is directly connected to PWR_ON pin, and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to the accessible point.
An open drain or open collector output is suitable to drive the PWR_ON input from an application
processor as PWR_ON input is equipped with an internal active pull-up resistor to the VCC supply, as
described in Figure 42.
A compatible push-pull output of an application processor can also be used. In any case, take care to
set the proper level in all the possible scenarios to avoid an inappropriate module switch-on.
Figure 42: PWR_ON application circuits using a push button and an open drain output of an application processor
Table 23: Example ESD protection component for the PWR_ON application circuit
☞ It is recommended to provide direct access to the PWR_ON pin on the application board by means
of an accessible test point directly connected to the PWR_ON pin.
2.3.1.2 Guidelines for PWR_ON layout design
The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to
switch on the TOBY-L2 modules. It is required to ensure that the voltage level is well defined during
operation and no transient noise is coupled on this line, otherwise the module might detect a spurious
power-on request.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
VCC
23
RESET_N
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
TOBY-L2 series
VCC
23
RESET_N
TP
TP
50 k
50 k
MPCI-L2 series
22
PERST#
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
MPCI-L2 series
22
PERST#
45 k 45 k
3V3
3V3
Reference
Description
Part Number – Manufacturer
ESD
Varistor for ESD protection
CT0402S14AHSG – EPCOS
2.3.2 Module reset (RESET_N or PERST#)
2.3.2.1 Guidelines for RESET_N and PERST# circuit design
The TOBY-L2 series RESET_N is equipped with an internal pull-up to the VCC supply and the MPCI-L2
series PERST# is equipped with an internal pull-up to the 3.3 V rail, as described in Figure 43. An
external pull-up resistor is not required and should not be provided.
If connecting the RESET_N or PERST# input to a push button, the pin will be externally accessible on
the application device. According to EMC/ESD requirements of the application, an additional ESD
protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible
point on the line connected to this pin, as described in Figure 43 and Table 24.
☞ ESD sensitivity rating of the RESET_N and PERST# pins is 1 kV (HBM according to JESD22-A114).
Higher protection level can be required if the line is externally accessible on the application board,
e.g. if an accessible push button is directly connected to the RESET_N or PERST# pin, and it can
be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to
accessible point.
An open drain output is suitable to drive the RESET_N and PERST# inputs from an application
processor as they are equipped with an internal pull-up to VCC supply and to the 3.3 V rail respectively,
as described in Figure 43.
A compatible push-pull output of an application processor can also be used. In any case, take care to
set the proper level in all the possible scenarios to avoid an inappropriate module reset, switch-on or
switch-off.
Figure 43: RESET_N and PERST# application circuits using a push button and an open drain output of an application
processor
Table 24: Example of ESD protection component for the RESET_N and PERST# application circuits
☞ If the external reset function is not required by the customer application, the RESET_N pin can be
UBX-13004618 - R28 Design-in Page 84 of 164
left unconnected to external components, but it is recommended providing direct access on the
application board by means of an accessible test point directly connected to the RESET_N pin.
TOBY-L2 and MPCI-L2 series - System Integration Manual
2.3.2.2 Guidelines for RESET_N and PERST# layout design
The RESET_N and PERST# circuits require careful layout due to the pin function: ensure that the
voltage level is well defined during operation and no transient noise is coupled on this line, otherwise
the module might detect a spurious reset request. It is recommended to keep the connection line to
RESET_N and PERST# pins as short as possible.
2.3.3 Module configuration selection by host processor
☞ The HOST_SELECT0 and HOST_SELECT1 pins are not available on MPCI-L2 series modules.
2.3.3.1 Guidelines for HOST_SELECTx circuit design
☞ The functionality of HOST_SELECT0 and HOST_SELECT1 pins is not supported by all the TOBY-
L2 series modules product versions: the two input pins should not be driven by the host application
processor or any other external device.
TOBY-L2 series modules include two input pins (HOST_SELECT0 and HOST_SELECT1) for the
selection of the module configuration by the host application processor.
☞ Do not apply voltage to HOST_SELECT0 and HOST_SELECT1 pins before the switch-on of their
supply source (V_INT), to avoid latch-up of circuits and allow a proper boot of the module. If the
external signals connected to the cellular module cannot be tri-stated or set low, insert a multi
channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit
connections and set to high impedance before V_INT switch-on.
☞ ESD sensitivity rating of the HOST_SELECT0 and HOST_SELECT1 pins is 1 kV (HBM as per
JESD22-A114). Higher protection level could be required if the lines are externally accessible and it
can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array)
close to accessible points
☞ If the HOST_SELECT0 and HOST_SELECT1 pins are not used, they can be left unconnected on
the application board.
2.3.3.2 Guidelines for HOST_SELECTx layout design
The input pins for the selection of the module configuration by the host application processor
(HOST_SELECT0 and HOST_SELECT1) are generally not critical for layout.
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TOBY-L2 and MPCI-L2 series - System Integration Manual
2.4 Antenna interface
TOBY-L2 and MPCI-L2 series modules provide two RF interfaces for connecting external antennas:
ANT1 represents the primary RF input/output for LTE/3G/2G RF signal transmission and reception
ANT2 represents the secondary RF input for LTE MIMO 2 x 2 or 3G Rx diversity RF signal reception
Both the ANT1 and the ANT2 pins have a nominal characteristic impedance of 50 and must be
connected to the related antenna through a 50 transmission line to allow proper transmission /
reception of RF signals.
☞ Two antennas (one connected to ANT1 pin and one connected to ANT2 pin) must be used to
support the Down-Link MIMO 2 x 2 radio technology. This is a required feature for LTE category 4
User Equipments (up to 150 Mb/s Down-Link data rate) according to 3GPP specifications.
2.4.1 Antenna RF interfaces (ANT1 / ANT2)
2.4.1.1 General guidelines for antenna selection and design
The antenna is the most critical component to be evaluated. Designers must take care of the
antennas from all perspective at the very start of the design phase when the physical dimensions of
the application board are under analysis/decision, since the RF compliance of the device integrating
TOBY-L2 and MPCI-L2 series modules with all the applicable required certification schemes depends
on antennas radiating performance.
LTE/3G/2G antennas are typically available in the types of linear monopole or PCB antennas such as
patches or ceramic SMT elements.
External antennas (e.g. linear monopole)
o External antennas basically do not imply physical restriction to the design of the PCB where
the TOBY-L2 and MPCI-L2 series module is mounted.
o The radiation performance mainly depends on the antennas. It is required to select antennas
with optimal radiating performance in the operating bands.
o RF cables should be carefully selected to have minimum insertion losses. Additional insertion
loss will be introduced by low quality or long cable. Large insertion loss reduces both transmit
and receive radiation performance.
o A high quality 50 RF connector provides proper PCB-to-RF-cable transition. It is
recommended to strictly follow the layout and cable termination guidelines provided by the
connector manufacturer.
Integrated antennas (e.g. patch-like antennas):
o Internal integrated antennas imply physical restriction to the design of the PCB:
Integrated antenna excites RF currents on its counterpoise, typically the PCB ground plane of
the device that becomes part of the antenna: its dimension defines the minimum frequency
that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that
should be similar to the quarter of the wavelength of the minimum frequency that has to be
radiated, given that the orientation of the ground plane relative to the antenna element must
be considered.
The isolation between the primary and the secondary antennas has to be as high as possible
and the correlation between the 3D radiation patterns of the two antennas has to be as low as
possible. In general, a separation of at least a quarter wavelength between the two antennas
is required to achieve a good isolation and low pattern correlation.
As numerical example, the physical restriction to the PCB design can be seen as following:
Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm
UBX-13004618 - R28 Design-in Page 86 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Min.
250 µm
Min. 400 µm
GND
ANT1
GND clearance
on very close buried layer
below ANT1 pad
GND clearance
on top layer
around ANT1 pad
Min.
250 µm
Min. 400 µm
GND
ANT2
GND clearance
on very close buried layer
below ANT2 pad
GND clearance
on top layer
around ANT2 pad
o Radiation performance depends on the whole PCB and antenna system design, including
product mechanical design and usage. Antennas should be selected with optimal radiating
performance in the operating bands according to the mechanical specifications of the PCB and
the whole product.
o It is recommended to select a pair of custom antennas designed by an antennas’ manufacturer
if the required ground plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm
wide). The antenna design process should begin at the start of the whole design process
o It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including PCB layout and matching circuitry
o Further to the custom PCB and product restrictions, antennas may require tuning to obtain
the required performance for compliance with all the applicable required certification schemes.
It is recommended to consult the antenna manufacturer for the design-in guidelines for
antenna matching relative to the custom application
In both of cases, selecting external or internal antennas, these recommendations should be observed:
Select antennas providing optimal return loss / V.S.W.R. figure over all the operating frequencies.
Select antennas providing optimal efficiency figure over all the operating frequencies.
Select antennas providing similar efficiency for both the primary and the secondary antenna.
Select antennas providing appropriate gain figure (i.e. combined antenna directivity and efficiency
figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits
specified in some countries (e.g. by FCC in the United States, as reported in the section 4.2.2).
Select antennas capable to provide low Envelope Correlation Coefficient between the primary
(ANT1) and the secondary (ANT2) antenna: the 3D antenna radiation patterns should have lobes
in different directions.
2.4.1.2 General guidelines for antenna selection and design
Guidelines for TOBY-L2 series ANT1 / ANT2 pins RF connection design
Proper transition between ANT1 / ANT2 pads and the application board PCB must be provided,
implementing the following design-in guidelines for the layout of the application PCB close to the
ANT1 / ANT2 pads:
On a multilayer board, the whole layer stack below the RF connection should be free of digital lines
Increase GND keep-out (i.e. clearance, a void area) around the ANT1 / ANT2 pads, on the top layer
of the application PCB, to at least 250 µm up to adjacent pads metal definition and up to 400 µm
on the area below the module, to reduce parasitic capacitance to ground, as described in the left
picture in Figure 44
Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT1 / ANT2
pads if the top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic
capacitance to ground, as described in the right picture in Figure 44
Figure 44: GND keep-out area on top layer around ANT1 / ANT2 pads and on very close buried layer below ANT1 / ANT2 pads
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Manufacturer
Series
Remarks
Hirose
U.FL® Ultra Small Surface Mount Coaxial Connector
Recommended
I-PEX
MHF® Micro Coaxial Connector
Tyco
UMCC® Ultra-Miniature Coax Connector
Amphenol RF
AMC® Amphenol Micro Coaxial
Lighthorse Technologies, Inc
IPX ultra micro-miniature RF connector
MPCI-L2 series
Baseboard
Stripline/Microstrip
Internal
Antenna
Baseboard
Application
Chassis
Connector to
External Antenna
MPCI-L2 series
Screw / Fastener
for Mini PCIe
Screw / Fastener for Mini PCIe
Guidelines for MPCI-L2 series ANT1 / ANT2 receptacles RF connection design
The Hirose U.FL-R-SMT RF receptacles implemented on the MPCI-L2 series modules for ANT1 / ANT2
ports require a suitable mated RF plug from the same connector series. Due to its wide usage in the
industry, several manufacturers offer compatible equivalents.
Table 25 lists some RF connector plugs that fit MPCI-L2 series modules RF connector receptacles,
based on the declaration of the respective manufacturers. Only the Hirose has been qualified for the
MPCI-L2 series modules; contact other producers to verify compatibility.
Table 25: MPCI-L2 series U.FL compatible plug connector
Typically the RF plug is available as a cable assembly: several kinds are available and the user should
select the cable assembly best suited to the application. The key characteristics are:
RF plug type: select U.FL or equivalent
Nominal impedance: 50
Cable thickness: typically from 0.8 mm to 1.37 mm. Select thicker cables to minimize insertion loss
Cable length: standard length is typically 100 mm or 200 mm, custom lengths may be available on
request. Select shorter cables to minimize insertion loss
RF connector on the other side of the cable: for example another U.FL (for board-to-board
connection) or SMA (for panel mounting)
For applications requiring an internal integrated SMT antenna, it is suggested to use a U-FL-to-U.FL
cable to provide RF path from the MPCI-L2 series module to PCB strip line or micro strip connected to
antenna pads as shown in Figure 45. Take care that the PCB-to-RF-cable transition, strip line and
antenna pads must be designed so that the characteristic impedance is as close as possible to 50 :
see the following subsections for specific guidelines regarding RF transmission line design and RF
termination design.
If an external antenna is required, consider that the connector is typically rated for a limited number
of insertion cycles. In addition, the RF coaxial cable may be relatively fragile compared to other types
of cables. To increase application ruggedness, connect U.FL to a more robust connector (e.g. SMA or
MMCX) fixed on panel or on flange as shown in Figure 45.
Figure 45: Example of RF connections, U.FL-to-U.FL cable for internal antenna and U.FL-to-SMA for external antenna
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TOBY-L2 and MPCI-L2 series - System Integration Manual
35 µm
35 µm
35 µm
35 µm
270 µm
270 µm
760 µm
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
380 µm 500 µm500 µm
35 µm
35 µm
1510 µm
L2 Copper
L1 Copper
FR-4 dielectric
1200 µm 400 µm400 µm
Guidelines for RF transmission line design
Any RF transmission line, such as the ones from the ANT1 and ANT2 pads up to the related antenna
connector or up to the related internal antenna pad, must be designed so that the characteristic
impedance is as close as possible to 50 .
RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from
a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is
sandwiched between two parallel ground planes within a dielectric material). The micro strip,
implemented as a coplanar waveguide, is the most common configuration for printed circuit board.
Figure 46 and Figure 47 provide two examples of proper 50 coplanar waveguide designs. The first
example of RF transmission line can be implemented in case of 4-layer PCB stack-up herein described,
and the second example of RF transmission line can be implemented in case of 2-layer PCB stack-up
herein described.
Figure 46: Example of 50 coplanar waveguide transmission line design for the described 4-layer board layup
Figure 47: Example of 50 coplanar waveguide transmission line design for the described 2-layer board layup
If the two examples do not match the application PCB stack-up the 50 characteristic impedance
calculation can be made using the HFSS commercial finite element method solver for
electromagnetic structures from Ansys Corporation, or using freeware tools like Avago / Broadcom
AppCAD (https://www.broadcom.com/appcad), taking care of the approximation formulas used by
the tools for the impedance computation.
To achieve a 50 characteristic impedance, the width of the transmission line must be chosen
depending on:
the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 46 and Figure 47)
the thickness of the dielectric material between the top layer (where the transmission line is
routed) and the inner closer layer implementing the ground plane (e.g. 270 µm in Figure 46, 1510 µm
in Figure 47)
the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric
material in Figure 46 and Figure 47)
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TOBY-L2 and MPCI-L2 series - System Integration Manual
SMA Connector
Primary Antenna
SMA Connector
Secondary Antenna
TOBY-L2 series
the gap from the transmission line to the adjacent ground plane on the same layer of the
transmission line (e.g. 500 µm in Figure 46, 400 µm in Figure 47)
If the distance between the transmission line and the adjacent GND area (on the same layer) does not
exceed 5 times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50
calculation.
Additionally to the 50 impedance, the following guidelines are recommended for transmission lines
design:
Minimize the transmission line length: the insertion loss should be minimized as much as possible,
in the order of a few tenths of a dB,
Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component
present on the RF transmission lines, if top-layer to buried layer dielectric thickness is below
200 µm, to reduce parasitic capacitance to ground,
The transmission lines width and spacing to GND must be uniform and routed as smoothly as
possible: avoid abrupt changes of width and spacing to GND,
Add GND stitching vias around transmission lines, as described in Figure 48,
Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground
layer, providing enough vias on the adjacent metal layer, as described in Figure 48,
Route RF transmission lines far from any noise source (as switching supplies and digital lines) and
from any sensitive circuit (as USB),
Avoid stubs on the transmission lines,
Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried
metal layer,
Do not route microstrip lines below discrete component or other mechanics placed on top layer
An example of proper RF circuit design is reported in Figure 48. In this case, the ANT1 and ANT2 pins
are directly connected to SMA connectors by means of proper 50 transmission lines, designed with
proper layout.
Figure 48: Suggested circuit and layout for antenna RF circuits on application board
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Guidelines for RF termination design
RF terminations must provide a characteristic impedance of 50 as well as the RF transmission lines
up to the RF terminations themselves, to match the characteristic impedance of the ANT1 / ANT2
ports of the modules.
However, real antennas do not have perfect 50 load on all the supported frequency bands.
Therefore, to reduce as much as possible performance degradation due to antennas mismatch, RF
terminations must provide optimal return loss (or V.S.W.R.) figure over all the operating frequencies,
as summarized in Table 8 and Table 9.
If external antennas are used, the antenna connectors represent the RF termination on the PCB:
Use suitable 50 connectors providing proper PCB-to-RF-cable transition.
Strictly follow the connector manufacturer’s recommended layout, for example:
o SMA Pin-Through-Hole connectors require GND keep-out (i.e. clearance, a void area) on all the
layers around the central pin up to annular pads of the four GND posts, as shown in Figure 48
o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in
the area below the connector between the GND land pads.
Cut out the GND layer under RF connectors and close to buried vias, to remove stray capacitance
and thus keep the RF line 50 , e.g. the active pad of UFL connectors needs to have a GND keepout (i.e. clearance, a void area) at least on first inner layer to reduce parasitic capacitance to GND.
If integrated antennas are used, the RF terminations are represented by the integrated antennas
themselves. The following guidelines should be followed:
Use antennas designed by an antenna manufacturer, providing best possible return loss / VSWR.
Provide a ground plane large enough according to the relative integrated antenna requirements.
The GND plane of the application PCB can be reduced down to a minimum size that must be similar
to 1 / 4 of wavelength of the minimum frequency that has to be radiated. As numerical example:
Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm
It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including PCB layout and matching circuitry.
Further to the custom PCB and product restrictions, antennas may require a tuning to comply with
all the applicable required certification schemes. It is recommended to consult the antenna
manufacturer for the antenna matching guidelines relative to the custom application.
Additionally, these recommendations regarding the antenna system placement must be followed:
Do not place antennas within closed metal case.
Do not place the antennas in close vicinity to end user since the emitted radiation in human tissue
is limited by regulatory requirements.
Place the antennas far from sensitive analog systems taking countermeasures to avoid EMC issue
Take care of interaction between co-located RF systems since the LTE/3G/2G transmitted power
may interact or disturb the performance of companion systems.
Place the two LTE/3G antennas providing low Envelope Correlation Coefficient (ECC) between
primary (ANT1) and secondary (ANT2) antenna: the antenna 3D radiation patterns should have
lobes in different directions. The ECC between primary and secondary antenna needs to be enough
low to comply with the radiated performance requirements specified by related certification
schemes, as indicated in Table 10.
Place the two LTE/3G antennas providing enough high isolation (see Table 10) between primary
(ANT1) and secondary (ANT2) antenna. The isolation depends on the distance between antennas
(separation of at least a quarter wavelength required for good isolation), antenna type (using
antennas with different polarization improves isolation), antenna 3D radiation patterns
(uncorrelated patterns improve isolation).
UBX-13004618 - R28 Design-in Page 91 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Manufacturer
Part Number
Product Name
Description
Taoglas
PA.710.A
Warrior
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
40.0 x 6.0 x 5.0 mm
Taoglas
PA.711.A
Warrior II
GSM / WCDMA / LTE SMD Antenna
Pairs with the Taoglas PA.710.A Warrior for LTE MIMO applications
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
40.0 x 6.0 x 5.0 mm
Taoglas
PCS.06.A
Havok
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2500..2690 MHz
42.0 x 10.0 x 3.0 mm
Antenova
SR4L002
Lucida
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
35.0 x 8.5 x 3.2 mm
Ethertronics
P822601
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2490..2700 MHz
50.0 x 8.0 x 3.2 mm
Ethertronics
P822602
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2490..2700 MHz
50.0 x 8.0 x 3.2 mm
Ethertronics
1002436
GSM / WCDMA / LTE Vertical Mount Antenna
698..960 MHz, 1710..2700 MHz
50.6 x 19.6 x 1.6 mm
Manufacturer
Part Number
Product Name
Description
Taoglas
FXUB63.07.0150C
GSM / WCDMA / LTE PCB Antenna with cable and U.FL
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz
96.0 x 21.0 mm
Taoglas
FXUB66.07.0150C
Maximus
GSM / WCDMA / LTE PCB Antenna with cable and U.FL
698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz,
2400..2700 MHz, 3400..3600 MHz, 4800..6000 MHz
120.2 x 50.4 mm
Taoglas
FXUB70.A.07.C.001
GSM / WCDMA / LTE PCB MIMO Antenna with cables and U.FL
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz
182.2 x 21.2 mm
Antenova
SRFL029
Moseni
GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL
689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz
110.0 x 20.0 mm
Antenova
SRFL026
Mitis
GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL
689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz
110.0 x 20.0 mm
Ethertronics
5001537
Prestta
GSM / WCDMA / LTE PCB Antenna with cable
704..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz
80.0 x 18.0 mm
EAD
FSQS35241-UF-10
SQ7
GSM / WCDMA / LTE PCB Antenna with cable and U.FL
690..960 MHz, 1710..2170 MHz, 2500..2700 MHz
110.0 x 21.0 mm
Examples of antennas
Table 26 lists some examples of possible internal on-board surface-mount antennas.
Table 26: Examples of internal surface-mount antennas
Table 27 lists some examples of possible internal off-board antennas with cable and connector.
Table 27: Examples of internal antennas with cable and connector
UBX-13004618 - R28 Design-in Page 92 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Manufacturer
Part Number
Product Name
Description
Taoglas
GSA.8827.A.101111
Phoenix
GSM / WCDMA / LTE adhesive-mount antenna with cable and
SMA(M)
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz
105 x 30 x 7.7 mm
Taoglas
TG.30.8112
GSM / WCDMA / LTE swivel dipole antenna with SMA(M)
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz
148.6 x 49 x 10 mm
Taoglas
MA241.BI.001
Genesis
GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination
antenna waterproof IP67 rated with cable and SMA(M)
698..960 MHz, 1710..2170 MHz, 2400..2700 MHz
205.8 x 58 x 12.4 mm
Laird Tech.
TRA6927M3PW-001
GSM / WCDMA / LTE screw-mount antenna with N-type(F)
698..960 MHz, 1710..2170 MHz, 2300..2700 MHz
83.8 x Ø 36.5 mm
Laird Tech.
CMS69273
GSM / WCDMA / LTE ceiling-mount antenna with cable and N-type(F)
698..960 MHz, 1575.42 MHz, 1710..2700 MHz
86 x Ø 199 mm
Laird Tech.
OC69271-FNM
GSM / WCDMA / LTE pole-mount antenna with N-type(M)
698..960 MHz, 1710..2690 MHz
248 x Ø 24.5 mm
Laird Tech.
CMD69273-30NM
GSM / WCDMA / LTE ceiling-mount MIMO antenna with cables &
N-type(M)
698..960 MHz, 1710..2700 MHz
43.5 x Ø 218.7 mm
Pulse Electronics
WA700/2700SMA
GSM / WCDMA / LTE clip-mount MIMO antenna with cables and
SMA(M)
698..960 MHz,1710..2700 MHz
149 x 127 x 5.1 mm
Table 28 lists some examples of possible external antennas.
Table 28: Examples of external antennas
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TOBY-L2 and MPCI-L2 series - System Integration Manual
Application Board
Antenna Cable
TOBY-L2 series
81
ANT1
75
ANT_DET
R1
C1 D1
C2
J1
Z0= 50 ohm Z0= 50 ohm
Z0= 50 ohm
Primary Antenna Assembly
R2
C4
L3
Radiating
Element
Diagnostic
Circuit
L2
L1
Antenna Cable
87
ANT2
C3
J2
Z0= 50 ohm Z0= 50 ohm
Z0= 50 ohm
Secondary Antenna Assembly
R3
C5
L4
Radiating
Element
Diagnostic
Circuit
Reference
Description
Part Number – Manufacturer
C1
27 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H270J – Murata
C2, C3
33 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H330J – Murata
D1
Very Low Capacitance ESD Protection
PESD0402-140 – Tyco Electronics
L1, L2
68 nH Multilayer Inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 – Murata
R1
10 k Resistor 0402 1% 0.063 W
RK73H1ETTP1002F – KOA Speer
J1, J2
SMA Connector 50 Through Hole Jack
SMA6251A1-3GT50G-50 – Amphenol
C4, C5
22 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1H220J – Murata
L3, L4
68 nH Multilayer Inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 – Murata
R2, R3
15 k Resistor for Diagnostic
Various Manufacturers
2.4.2 Antenna detection interface (ANT_DET)
☞ Antenna detection (ANT_DET) is not available on MPCI-L2 series modules
☞ Antenna detection (ANT_DET) is not supported by TOBY-L2 ”00”, “01” and “60” product versions
2.4.2.1 Guidelines for ANT_DET circuit design
Figure 49 and Table 29 describe the recommended schematic / components for the antennas
detection circuit that must be provided on the application board and for the diagnostic circuit that
must be provided on the antennas’ assembly to achieve primary and secondary antenna detection
functionality.
Figure 49: Schematic example for antenna detection circuit on application PCB and diagnostic circuit on antennas assembly
Table 29: Example of parts for antenna detection circuit on application board and diagnostic circuit on antennas assembly
The antenna detection circuit and diagnostic circuit suggested in Figure 49 and Table 29 are explained
here:
When antenna detection is forced by AT+UANTR command, ANT_DET generates a DC current
measuring the resistance (R2 // R3) from antenna connectors (J1, J2) provided on the application
board to GND.
DC blocking capacitors are needed at the ANT1 / ANT2 pins (C2, C3) and at the antenna radiating
element (C4, C5) to decouple the DC current generated by the ANT_DET pin.
Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series
at the ANT_DET pin (L1, L2) and in series at the diagnostic resistor (L3, L4), to avoid a reduction of
the RF performance of the system, improving the RF isolation of the load resistor.
Additional components (R1, C1 and D1 in Figure 49) are needed at the ANT_DET pin as ESD
protection
The ANT1 / ANT2 pins must be connected to the antenna connector by means of a transmission
line with nominal characteristics impedance as close as possible to 50 .
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TOBY-L2 and MPCI-L2 series - System Integration Manual
The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short
to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 49,
the measured DC resistance is always at the limits of the measurement range (respectively open or
short), and there is no means to distinguish between a defect on antenna path with similar
characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna).
Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating
element will alter the measurement and produce invalid results for antenna detection.
☞ It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to
30 k to assure good antenna detection functionality and avoid a reduction of module RF
performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the
range of 1 GHz to improve the RF isolation of load resistor.
For example:
Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the
module reports the resistance value evaluated from the antenna connector provided on the
application board to GND:
Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k
if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected.
Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit
“over range” report (see u-blox AT Commands Manual [3]) means that that the antenna is not
connected or the RF cable is broken.
Reported values below the measurement range minimum limit (1 k) highlights a short to GND at
antenna or along the RF cable.
Measurement inside the valid measurement range and outside the expected range may indicate
an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic.
Reported value could differ from the real resistance value of the diagnostic resistor mounted
inside the antenna assembly due to antenna cable length, antenna cable capacity and the used
measurement method.
☞ If the primary / secondary antenna detection function is not required by the customer application,
the ANT_DET pin can be left not connected and the ANT1 / ANT2 pins can be directly connected
to the related antenna connector by means of a 50 transmission line as described in Figure 48.
2.4.2.2 Guidelines for ANT_DET layout design
The recommended layout for the primary antenna detection circuit to be provided on the application
board to achieve the primary antenna detection functionality, implementing the recommended
schematic described in Figure 49 and Table 29, is explained here:
The ANT1 / ANT2 pins have to be connected to the antenna connector by means of a 50
transmission line, implementing the design guidelines described in section 2.4.1 and the
recommendations of the SMA connector manufacturer.
DC blocking capacitor at ANT1 / ANT2 pins (C2, C3) has to be placed in series to the 50 RF line.
The ANT_DET pin has to be connected to the 50 transmission line by means of a sense line.
Choke inductors in series at ANT_DET pin (L1, L2) have to be placed so that one pad is on the 50
transmission line and the other pad represents the start of the sense line to the ANT_DET pin.
The additional components (R1, C1 and D1) on ANT_DET line have to be placed as ESD protection.
UBX-13004618 - R28 Design-in Page 95 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
2.5 SIM interface
☞ SIM detection interface (GPIO5) is not available on the MPCI-L2 series modules.
☞ SIM detection interface (GPIO5) is not supported by the TOBY-L2 modules “00”, “01” and “60”
product versions: the pin should not be driven by any external device.
2.5.1.1 Guidelines for SIM circuit design
Guidelines for SIM cards, SIM connectors and SIM chips selection
The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical,
electrical and functional characteristics of Universal Integrated Circuit Cards (UICC), which contains
the Subscriber Identification Module (SIM) integrated circuit that securely stores all the information
needed to identify and authenticate subscribers over the LTE/3G/2G network.
Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as
follows:
Contact C1 = VCC (Supply) It must be connected to VSIM or UIM_PWR
Contact C2 = RST (Reset) It must be connected to SIM_RST or UIM_RESET
Contact C3 = CLK (Clock) It must be connected to SIM_CLK or UIM_CLK
Contact C4 = AUX1 (Auxiliary contact) It must be left not connected
Contact C5 = GND (Ground) It must be connected to GND
Contact C6 = VPP (Programming supply) It can be left not connected
Contact C7 = I/O (Data input/output) It must be connected to SIM_IO or UIM_DATA
Contact C8 = AUX2 (Auxiliary contact) It must be left not connected
A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the
auxiliary contacts C4 and C8. Only 6 contacts are required and must be connected to the module SIM
interface. Removable SIM cards are suitable for applications requiring a change of SIM card during
the product lifetime.
A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or
it can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch
integrated in the SIM connector for the mechanical card presence detection are provided. Select a
SIM connector providing 6+2 or 8+2 positions if the optional SIM detection feature (not available on
MPCI-L2 series) is required by the custom application, otherwise a connector without integrated
mechanical presence switch can be selected.
Solderable UICC / SIM chip contact mapping (M2M UICC form factor) is defined by ETSI TS 102 671 as:
Case Pin 8 = UICC Contact C1 = VCC (Supply) It must be connected to VSIM / UIM_PWR
Case Pin 7 = UICC Contact C2 = RST (Reset) It must be connected to SIM_RST / UIM_RESET
Case Pin 6 = UICC Contact C3 = CLK (Clock) It must be connected to SIM_CLK / UIM_CLK
Case Pin 5 = UICC Contact C4 = AUX1 It must be left not connected
Case Pin 1 = UICC Contact C5 = GND (Ground) It must be connected to GND
Case Pin 2 = UICC Contact C6 = VPP It can be left not connected
Case Pin 3 = UICC Contact C7 = I/O (Data I/O) It must be connected to SIM_IO / UIM_DATA
Case Pin 4 = UICC Contact C8 = AUX2 It must be left not connected
A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other
uses, but only 6 contacts are required and must be connected to the module SIM card interface as
described above. Solderable SIM chips are suitable for M2M applications where it is not required to
change the SIM once installed.
UBX-13004618 - R28 Design-in Page 96 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
59
VSIM
57
SIM_IO
56
SIM_CLK
58
SIM_RST
SIM CARD
HOLDER
C5C6C
7
C1C2C
3
SIM Card
Bottom View
(contacts
side)
C1
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
J1
C4
D1 D2 D3 D4
C
8
C
4
MPCI-L2 series
8
UIM_PWR
10
UIM_DATA
12
UIM_CLK
14
UIM_RESET
SIM CARD
HOLDER
C5C6C
7
C1C2C
3
SIM Card
Bottom View
(contacts
side)
C1
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
J1
C4
D1 D2 D3 D4
C
8
C
4
Reference
Description
Part Number – Manufacturer
C1, C2, C3, C4
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 – Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 – Murata
D1, D2, D3, D4
Very Low Capacitance ESD Protection
PESD0402-140 – Tyco Electronics
J1
SIM Card Holder, 6 p, without card presence switch
Various manufacturers, as C707 10M006 136 2 –
Amphenol
Guidelines for single SIM card connection without detection
A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of
TOBY-L2 and MPCI-L2 series modules as described in Figure 50, where the optional SIM detection
feature is not implemented.
Follow these guidelines to connect the module to a SIM connector without SIM presence detection:
Connect the UICC / SIM contacts C1 (VCC) to the VSIM / UIM_PWR pin of the module.
Connect the UICC / SIM contact C7 (I/O) to the SIM_IO / UIM_DATA pin of the module.
Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK / UIM_CLK pin of the module.
Connect the UICC / SIM contact C2 (RST) to the SIM_RST / UIM_RESET pin of the module.
Connect the UICC / SIM contact C5 (GND) to ground.
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the
relative pad of the SIM connector, to prevent digital noise.
Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM
line, very close to each related pad of the SIM connector, to prevent RF coupling especially in case
the RF antenna is placed closer than 10 – 30 cm from the SIM card holder.
Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on
each externally accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity
rating of the SIM interface pins is 1 kV (HBM). So that, according to EMC/ESD requirements of the
custom application, higher protection level can be required if the lines are externally accessible on
the application device.
Limit capacitance and series resistance on each SIM signal to match the SIM requirements
(26.2 ns is the maximum allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on
data and reset lines).
Figure 50: Application circuits for the connection to a single removable SIM card, with SIM detection not implemented
Table 30: Example of components for the connection to a single removable SIM card, with SIM detection not implemented
UBX-13004618 - R28 Design-in Page 97 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
1:1 scaling
TOBY-L2 series
59
VSIM
57
SIM_IO
56
SIM_CLK
58
SIM_RST
SIM CHIP
SIM Chip
Bottom View
(contacts
side)
C1
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
U1
C4
2
8
3
6
7
1
C1 C5
C2 C6
C3 C7
C4 C8
8
7
6
5
1
2
3
4
MPCI-L2 series
8
UIM_PWR
10
UIM_DATA
12
UIM_CLK
14
UIM_RESET
SIM CHIP
SIM Chip
Bottom View
(contacts
side)
C1
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
U1
C4
2
8
3
6
7
1
C1 C5
C2 C6
C3 C7
C4 C8
8
7
6
5
1
2
3
4
Reference
Description
Part Number – Manufacturer
C1, C2, C3, C4
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 – Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 – Murata
U1
SIM chip (M2M UICC Form Factor)
Various Manufacturers
Guidelines for single SIM chip connection
A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of
TOBY-L2 and MPCI-L2 series modules as described in Figure 51.
Follow these guidelines to connect the module to a solderable SIM chip without SIM presence
detection:
Connect the UICC / SIM contacts C1 (VCC) to the VSIM / UIM_PWR pin of the module.
Connect the UICC / SIM contact C7 (I/O) to the SIM_IO / UIM_DATA pin of the module.
Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK / UIM_CLK pin of the module.
Connect the UICC / SIM contact C2 (RST) to the SIM_RST / UIM_RESET pin of the module.
Connect the UICC / SIM contact C5 (GND) to ground.
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to
the relative pad of the SIM chip, to prevent digital noise.
Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM
line, to prevent RF coupling especially in case the RF antenna is placed closer than 10 – 30 cm from
the SIM lines.
Limit capacitance and series resistance on each SIM signal to match the SIM requirements (26.2
ns is the maximum allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on data
and reset lines).
Figure 51: Application circuits for the connection to a single solderable SIM chip, with SIM detection not implemented
Table 31: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented
UBX-13004618 - R28 Design-in Page 98 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
TOBY-L2 series
5
V_INT
60
GPIO5
SIM CARD
HOLDER
C5C6C
7
C1C2C
3
SIM Card
Bottom View
(contacts side)
C1
VPP (C6)
VCC (C1)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
C2 C3 C5
J1
C4
SW1
SW2
D1 D2 D3 D4 D5 D6
R2
R1
C
8
C
4
TP
59
VSIM
57
SIM_IO
56
SIM_CLK
58
SIM_RST
Reference
Description
Part Number – Manufacturer
C1, C2, C3, C4
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 – Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 – Murata
D1, … , D6
Very Low Capacitance ESD Protection
PESD0402-140 – Tyco Electronics
R1
1 k Resistor 0402 5% 0.1 W
RC0402JR-071KL – Yageo Phycomp
R2
470 k Resistor 0402 5% 0.1 W
RC0402JR-07470KL- Yageo Phycomp
J1
SIM Card Holder, 6 + 2 p, with card presence switch
Various manufacturers, as CCM03-3013LFT R102 – C&K
Guidelines for single SIM card connection with detection
A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of
TOBY-L2 modules as described in Figure 52, where the optional SIM card detection feature is
implemented.
Follow these guidelines to connect the module to a SIM connector with SIM presence detection:
Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.
Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.
Connect the UICC / SIM contact C5 (GND) to ground.
Connect one pin of the normally-open mechanical switch integrated in the SIM connector (e.g. the
SW2 pin as described in Figure 52) to the GPIO5 input pin of the module.
Connect the other pin of the normally-open mechanical switch integrated in the SIM connector
(e.g. the SW1 pin as described in Figure 52) to the V_INT 1.8 V supply output of the module by
means of a strong (e.g. 1 k) pull-up resistor, as the R1 resistor in Figure 52.
Provide a weak (e.g. 470 k) pull-down resistor at SIM detection line, as R2 resistor in Figure 52
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line, close to
the related pad of the SIM connector, to prevent digital noise.
Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM
line, very close to each related pad of the SIM connector, to prevent RF coupling especially in case
the RF antenna is placed closer than 10 – 30 cm from the SIM card holder.
Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on
each externally accessible SIM line, close to each related pad of the SIM connector: ESD sensitivity
rating of the SIM interface pins is 1 kV (HBM), so that, according to the EMC/ESD requirements of
the custom application, higher protection level can be required if the lines are externally accessible
on the application device.
Limit capacitance and series resistance on each SIM signal to match the SIM requirements
(26.2 ns max allowed rise time on clock line, 1.0 µs max allowed rise time on data and reset lines).
Figure 52: Application circuit for the connection to a single removable SIM card, with SIM detection implemented
Table 32: Example of components for the connection to a single removable SIM card, with SIM detection implemented
UBX-13004618 - R28 Design-in Page 99 of 164
TOBY-L2 and MPCI-L2 series - System Integration Manual
Guidelines for dual SIM card / chip connection
Two SIM card / chip can be connected to the SIM interface of TOBY-L2 and MPCI-L2 series modules
as described in the application circuits of Figure 53.
TOBY-L2 and MPCI-L2 series modules do not support the usage of two SIM at the same time, but two
SIM can be populated on the application board, providing a proper switch to connect only the first or
only the second SIM at a time to the SIM interface of the modules, as described in Figure 53.
TOBY-L2 modules “00”, “01” and “60” product versions and MPCI-L2 modules do not support SIM hot
insertion / removal functionality, to enable / disable SIM interface upon detection of external SIM card
physical insertion / removal: the physical connection between the external SIM and the module has to
be provided before the module boot and then held for normal operation. Switching from one SIM to
another can only be properly done within one of these two time periods:
after TOBY-L2 module switch-off by the AT+CPWROFF and before TOBY-L2 module switch-on by
PWR_ON
after TOBY-L2 / MPCI-L2 module deregistration from network by AT+COPS=2 or by AT+CFUN=4
and before TOBY-L2 / MPCI-L2 module reset (reboot) by AT+CFUN=16 or AT+CFUN=1,1
TOBY-L2 modules (except “00”, “01” and “60” product versions) support SIM hot insertion / removal
on the GPIO5 pin: if the feature is enabled using the specific AT commands (see sections 1.8.2 and 1.11,
and u-blox AT Commands Manual [3], +UGPIOC, +UDCONF=50 commands), the switch from first SIM
to the second SIM can be properly done when a Low logic level is present on the GPIO5 pin (“SIM not
inserted” = SIM interface not enabled), without the necessity of a module re-boot, so that the SIM
interface will be re-enabled by the module to use the second SIM when a high logic level is re-applied
on the GPIO5 pin.
In the application circuit example represented in Figure 53, the application processor will drive the SIM
switch using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be
used to handle the SIM hot insertion / removal function of TOBY-L2 modules, which can also be
handled by other external circuits or by the cellular module GPIO according to the application
requirements.
The dual SIM connection circuit described in Figure 53 can be implemented for SIM chips as well,
providing proper connection between SIM switch and SIM chip as described in Figure 51.
If it is required to switch between more than 2 SIM, a circuit similar to the one described in Figure 53
can be implemented: in case of 4 SIM circuit, using proper 4-throw switch instead of the suggested
2-throw switches.
Follow these guidelines to connect the module to two external SIM connectors:
Use a proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) 2-throw analog
switch (e.g. Fairchild FSA2567) as SIM switch to ensure high-speed data transfer according to SIM
requirements.
Connect the contacts C1 (VCC) and C6 (VPP) of the two UICC / SIM to the VSIM / UIM_PWR pin of
the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO / UIM_DATA pin of the module
by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK / UIM_CLK pin of the module
by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST / UIM_RESET pin of the
module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567).
Connect the contact C5 (GND) of the two UICC / SIM to ground.
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply
(VSIM / UIM_PWR), close to the related pad of the two SIM connectors, to prevent digital noise.
UBX-13004618 - R28 Design-in Page 100 of 164
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