u blox LISAU200 Users Manual

Abstract
This document describes the features and the system integration of LISA-U1 series HSPA and LISA-U2 series HSPA+ wireless modules.
These modules are complete and cost efficient 3.75G solutions offering up to six-band HSDPA/HSUPA and quad-band GSM/EGPRS voice and/or data transmission technology in a compact form factor.
www.u-blox.com
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LISA-U series
3.75G HSPA / HSPA+ Wireless Modules
System Integration Manual
LISA-U series - System Integration Manual
Document Information
Title
LISA-U series
Subtitle
3.75G HSPA / HSPA+ Wireless Modules
Document type
System Integration Manual
Document number
3G.G2-HW-10002-A2
Document status
Preliminary
Document status information
Objective Specification
This document contains target values. Revised and supplementary data will be published later.
Advance Information
This document contains data based on early testing. Revised and supplementary data will be published later.
Preliminary
This document contains data from product verification. Revised and supplementary data may be published later.
Released
This document contains the final product specification.
Name
Type number
Firmware version
PCN / IN
LISA-U100
LISA-U100-00S-00
10.72
3G.G2-SW-11000
LISA-U100-01S-00
11.40
n.a.
LISA-U110
LISA-U110-00S-00
10.72
3G.G2-SW-11000
LISA-U110-01S-00
11.40
n.a.
LISA-U120
LISA-U120-00S-00
10.72
3G.G2-SW-11000
LISA-U120-01S-00
11.40
n.a.
LISA-U130
LISA-U130-00S-00
10.72
3G.G2-SW-11000
LISA-U130-01S-00
11.40
n.a.
LISA-U130-01A-00
11.40
n.a.
LISA-U200
LISA-U200-00S-00
21.21
n.a.
LISA-U200-01S-00
TBD
n.a.
LISA-U230
LISA-U230-01S-00
TBD
n.a.
LISA-U230-01A-00
TBD
n.a.
This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They can be downloaded from www.u-blox.com. u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without express permission is strictly prohibited. Copyright © 2012, u-blox AG. u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries.
This document applies to the following products:
Trademark Notice
Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners.
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LISA-U series - System Integration Manual

Preface

u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.
AT Commands Manual: This document provides the description of the supported AT commands by the
LISA-U series modules to verify all implemented functionalities.
System Integration Manual: This Manual provides hardware design instructions and information on how to
set up production and final product tests.
Application Note: document provides general design instructions and information that applies to all u-blox
Wireless modules. See Section Related documents for a list of Application Notes related to your Wireless Module.
How to use this Manual
The LISA-U series System Integration Manual provides the necessary information to successfully design in and configure these u-blox wireless modules.
This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox Wireless Integration, please:
Read this manual carefully. Contact our information service on the homepage http://www.u-blox.com Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com
Technical Support
Worldwide Web
Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and helpful FAQ can be accessed 24h a day.
By E-mail
Contact the nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal email address of our staff. This makes sure that your request is processed as soon as possible. You will find the contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support please have the following information ready:
Module type (e.g. LISA-U100) and firmware version Module configuration Clear description of your question or the problem A short description of the application Your complete contact details
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Contents

Preface ................................................................................................................................ 3
Contents .............................................................................................................................. 4
1 System description ....................................................................................................... 7
1.1 Overview .............................................................................................................................................. 7
1.2 Architecture .......................................................................................................................................... 9
1.2.1 Functional blocks ......................................................................................................................... 10
1.2.2 Hardware differences between LISA-U series modules ................................................................. 12
1.3 Pin-out ............................................................................................................................................... 13
1.4 Operating modes ................................................................................................................................ 17
1.5 Power management ........................................................................................................................... 19
1.5.1 Power supply circuit overview ...................................................................................................... 19
1.5.2 Module supply (VCC) .................................................................................................................. 20
1.5.3 Current consumption profiles ...................................................................................................... 28
1.5.4 RTC Supply (V_BCKP) .................................................................................................................. 32
1.5.5 Interface supply (V_INT) ............................................................................................................... 34
1.6 System functions ................................................................................................................................ 35
1.6.1 Module power-on ....................................................................................................................... 35
1.6.2 Module power-off ....................................................................................................................... 39
1.6.3 Module reset ............................................................................................................................... 40
1.7 RF connection ..................................................................................................................................... 42
1.8 (U)SIM interface .................................................................................................................................. 42
1.8.1 (U)SIM functionality ..................................................................................................................... 44
1.9 Serial communication ......................................................................................................................... 45
1.9.1 Serial interfaces configuration ..................................................................................................... 45
1.9.2 Asynchronous serial interface (UART)........................................................................................... 46
1.9.3 USB interface............................................................................................................................... 61
1.9.4 SPI interface ................................................................................................................................ 64
1.9.5 MUX Protocol (3GPP 27.010) ...................................................................................................... 68
1.10 DDC (I2C) interface .......................................................................................................................... 69
1.10.1 Overview ..................................................................................................................................... 69
1.10.2 DDC application circuit ................................................................................................................ 69
1.11 Audio Interface ............................................................................................................................... 74
1.11.1 Analog Audio interface ............................................................................................................... 74
1.11.2 Digital Audio interface ................................................................................................................. 80
1.11.3 Voiceband processing system ...................................................................................................... 85
1.12 General Purpose Input/Output (GPIO) ............................................................................................. 87
1.13 Reserved pins (RSVD) ...................................................................................................................... 96
1.14 Schematic for LISA-U series module integration .............................................................................. 97
1.15 Approvals ........................................................................................................................................ 99
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1.15.1 R&TTED and European Conformance CE mark ............................................................................ 99
1.15.2 IC .............................................................................................................................................. 100
1.15.3 Federal communications commission notice .............................................................................. 100
1.15.4 a-tick AUS Certification ............................................................................................................. 102
2 Design-In ................................................................................................................... 103
2.1 Design-in checklist ............................................................................................................................ 103
2.1.1 Schematic checklist ................................................................................................................... 103
2.1.2 Layout checklist ......................................................................................................................... 104
2.1.3 Antenna checklist ...................................................................................................................... 104
2.2 Design Guidelines for Layout ............................................................................................................ 105
2.2.1 Layout guidelines per pin function ............................................................................................. 105
2.2.2 Footprint and paste mask .......................................................................................................... 115
2.2.3 Placement ................................................................................................................................. 117
2.3 Thermal aspects ................................................................................................................................ 118
2.4 Antenna guidelines ........................................................................................................................... 119
2.4.1 Antenna termination ................................................................................................................. 120
2.4.2 Antenna radiation ..................................................................................................................... 121
2.4.3 Antenna detection functionality ................................................................................................ 122
2.5 ESD precautions ................................................................................................................................ 125
2.5.1 ESD immunity test overview ...................................................................................................... 125
2.5.2 ESD immunity test of LISA-U series reference design.................................................................. 125
2.5.3 ESD application circuits .............................................................................................................. 127
3 Features description ................................................................................................. 130
3.1 Firmware (upgrade) Over AT (FOAT) ................................................................................................. 130
3.1.1 Overview ................................................................................................................................... 130
3.1.2 FOAT procedure ........................................................................................................................ 130
3.2 TCP/IP and UDP/IP ............................................................................................................................. 130
3.2.1 Multiple PDP contexts and sockets............................................................................................. 130
3.3 FTP and FTPS .................................................................................................................................... 131
3.4 HTTP and HTTPS ............................................................................................................................... 131
3.5 AssistNow clients and GPS integration .............................................................................................. 131
3.6 Jamming Detection ........................................................................................................................... 131
3.7 In-Band modem ................................................................................................................................ 132
3.8 Smart Temperature Management ..................................................................................................... 132
3.8.1 Smart Temperature Supervisor (STS) .......................................................................................... 133
3.8.2 Threshold Definitions ................................................................................................................. 135
3.9 Hybrid positioning and CellLocate ..................................................................................................... 135
3.9.1 Positioning through cellular information: CellLocate .................................................................. 135
3.9.2 Hybrid positioning ..................................................................................................................... 137
4 Handling and soldering ........................................................................................... 138
4.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 138
4.2 Soldering .......................................................................................................................................... 138
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4.2.1 Soldering paste.......................................................................................................................... 138
4.2.2 Reflow soldering ....................................................................................................................... 138
4.2.3 Optical inspection ...................................................................................................................... 140
4.2.4 Cleaning .................................................................................................................................... 140
4.2.5 Repeated reflow soldering ......................................................................................................... 140
4.2.6 Wave soldering.......................................................................................................................... 140
4.2.7 Hand soldering .......................................................................................................................... 140
4.2.8 Rework ...................................................................................................................................... 140
4.2.9 Conformal coating .................................................................................................................... 140
4.2.10 Casting ...................................................................................................................................... 141
4.2.11 Grounding metal covers ............................................................................................................ 141
4.2.12 Use of ultrasonic processes ........................................................................................................ 141
5 Product Testing......................................................................................................... 142
5.1 u-blox in-series production test ......................................................................................................... 142
5.2 Test parameters for OEM manufacturer ............................................................................................ 142
5.2.1 ‘Go/No go’ tests for integrated devices ...................................................................................... 143
5.2.2 Functional tests providing RF operation ..................................................................................... 143
Appendix ........................................................................................................................ 146
A Migration to LISA-U2 series wireless modules ....................................................... 146
A.1 Checklist for migration ..................................................................................................................... 146
A.2 Software migration ........................................................................................................................... 147
A.2.1 Software migration from LISA-U1 series to LISA-U2 series wireless modules .............................. 147
A.3 Hardware migration.......................................................................................................................... 147
A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series wireless modules ............................. 147
A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series ................................................................. 148
A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series .................................................................. 154
B Glossary .................................................................................................................... 155
Related documents......................................................................................................... 157
Revision history .............................................................................................................. 158
Contact ............................................................................................................................ 159
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3G UMTS/HSDPA/HSUPA Characteristics
2G GSM/GPRS/EDGE Characteristics
Class A User Equipment1
Class B Mobile Station2
UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD)
3GPP Release 6 High Speed Packet Access (HSPA) for LISA-U1
series
3GPP Release 7 Evolved High Speed Packet Access (HSPA+) for
LISA-U2 series
Rx Diversity for LISA-U230
GSM EDGE Radio Access (GERA)
3GPP Release 6 for LISA-U1 series 3GPP Release 7 for LISA-U2 series Rx Diversity for LISA-U230
2-band support for LISA-U100, LISA-U120:
Band II (1900 MHz), Band V (850 MHz)
2-band support for LISA-U110, LISA-U130:
Band I (2100 MHz), Band VIII (900 MHz)
4-band support for LISA-U200-00:
Band I (2100 MHz), Band II (1900 MHz),
Band V (850 MHz), Band VI (800 MHz)
6-band support for LISA-U200-01, LISA-U230:
Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz),
Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz)
4-band support
GSM 850 MHz, E-GSM 900 MHz,
DCS 1800 MHz, PCS 1900 MHz
WCDMA/HSDPA/HSUPA Power Class
Power Class 3 (24 dBm) for WCDMA/HSDPA/HSUPA mode
GSM/GPRS Power Class
Power Class 4 (33 dBm) for GSM/E-GSM bands Power Class 1 (30 dBm) for DCS/PCS bands
EDGE Power Class
Power Class E2 (27 dBm) for GSM/E-GSM bands Power Class E2 (26 dBm) for DCS/PCS bands
PS (Packet Switched) Data Rate
HSUPA category 6, up to 5.76 Mb/s UL HSDPA category 8 up to 7.2 Mb/s DL for LISA-U1 series,
LISA-U200
HSDPA category 14 up to 21.1 Mb/s DL for LISA-U230 WCDMA PS data up to 384 kb/s DL/UL
PS (Packet Switched) Data Rate
GPRS multislot class 33
4
, coding scheme CS1-CS4,
up to 107 kb/s DL, 85.6 kb/s UL for LISA-U2 series
GPRS multislot class 12
4
, coding scheme CS1-CS4,
up to 85.6 kb/s DL/UL for LISA-U1 for LISA-U1 series
EDGE multislot class 33
3
, coding scheme MCS1-MCS9,
up to 296 kb/s DL, 236.8 kb/s UL for LISA-U2
EDGE multislot class 12
4
, coding scheme MCS1-MCS9,
up to 236.8 kb/s DL/UL for LISA-U1
CS (Circuit Switched) Data Rate
WCDMA CS data up to 64 kb/s DL/UL
CS (Circuit Switched) Data Rate
GSM CS data up to 9.6 kb/s DL/UL
supported in transparent/non transparent mode
1
2
3
4

1 System description

1.1 Overview

LISA-U series wireless modules integrate full-feature 3G UMTS/HSxPA and 2G GSM/GPRS/EDGE protocol stack with Assisted GPS support. These SMT modules come in the compact LISA form factor, featuring Leadless Chip Carrier (LCC) packaging technology.
Table 1: LISA-U series UMTS/HSDPA/HSUPA and GSM/GPRS/EDGE characteristics
Operation modes I to III are supported on GSM/GPRS network, with user-defined preferred service selectable from GSM to GPRS. Paging messages for GSM calls can be optionally monitored during GPRS data transfer in not-coordinating NOM II-III.
Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active
without any interruption in service.
Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. If for example during data transmission an incoming call occurs, the data connection is suspended to allow the voice communication. Once the voice call has terminated, the data service is resumed.
GPRS/EDGE multislot class 33 implies a maximum of 5 slots in DL (reception) and 4 slots in UL (transmission) with 6 slots in total.
GPRS/EDGE multislot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total.
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Module
Technology
Bands
Interface
Audio
Functions
HSUPA [Mb/s]
HSDPA [Mb/s]
UMTS/HSPA bands [MHz]
GSM/GPRS/EDGE quad-band
UART
SPI (5 wire)
USB
DDC for u-blox GPS
GPIO
Analog Audio
Digital Audio
Network indication
Antenna Supervisor
Jamming detection
Embedded TCP/UDP stack
HTTP, SSL
GPS via Modem
Embedded AssistNow
FW update over AT (FOAT)
In-band modem
Rx diversity
CellLocate
SIM Access Profile (SAP)
LISA-U100-00
5.76
7.2
850/1900
1 1 1 1 5 • LISA-U100-01
5.76
7.2
850/1900
1 1 1 1 5 • LISA-U110-00
5.76
7.2
900/2100
1 1 1 1 5 • LISA-U110-01
5.76
7.2
900/2100
1 1 1 1 5 • LISA-U120-00
5.76
7.2
850/1900
1 1 1 1 5 1 1 • LISA-U120-01
5.76
7.2
850/1900
1 1 1 1 5 1 1 • LISA-U130-00
5.76
7.2
900/2100
1 1 1 1 5 1 1 • LISA-U130-01
5.76
7.2
900/2100
1 1 1 1 5 1 1 •
LISA-U200-00
5.76
7.2
800/850/
1900/2100
1 1 1 1 9 • LISA-U200-01
5.76
7.2
800/850/900/
1700/1900/2100
1 1 1 1
14 2 • • • • • • • • • • •
LISA-U230-01
5.76
21.1
800/850/900/
1700/1900/2100
1 1 1 1
14 2 • • • • • • • • • • • •
Direct Link mode is supported for TCP / UDP sockets except for LISA-U1xx-00 module versions. Regarding 3G transmit and receive data rate capability, LISA-U series modules implement 3G High-Speed Uplink
Packet Access (HSUPA) category 6, LISA-U1 series and LISA-U200 modules implement 3G High Speed Downlink Packet Access (HSDPA) category 8, while LISA-U230 modules implement the 3G HSDPA category 14. HSUPA and HSDPA categories determine the maximum speed at which data can be respectively transmitted and received: higher categories allowing faster data transfer rates as indicated in Table 1.
The 3G network automatically performs adaptive coding and modulation using a choice of forward error correction code rate and choice of modulation type, to achieve the highest possible data rate and data transmission robustness according to the quality of the radio channel.
Regarding 2G transmit and receive data rate capability, LISA-U1 series modules implement GPRS/EGPRS class 12, while LISA-U2 series modules implement GPRS/EGPRS class 33. GPRS and EGPRS classes determine the maximum number of timeslots available for upload and download and thus the speed at which data can be transmitted and received: higher classes typically allowing faster data transfer rates as indicated in Table 1.
The 2G network automatically configures the number of timeslots used for reception or transmission (voice calls take precedence over GPRS/EGPRS traffic) and channel encoding (from Coding Scheme 1 up to Modulation and Coding Scheme 9), performing link adaptation to achieve the highest possible data rate.
A summary of interfaces and features provided by LISA-U series modules is described in the Table 2. Note that LISA-U130-01 and LISA-U230-01 are available in standard and automotive quality grade versions.
Table 2: LISA-U series features summary
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1.2 Architecture

Wireless
Base-band
Processor
Memory
Power Management Unit
RF
Transceiver
26 MHz
32.768 kHz
SAW Filter
FEM & 2G PA
ANT
LNA
3G PA
LNA
3G PA
DDC (for GPS)
(U)SIM Card
UART
SPI
USB
GPIO(s)
Power On
External Reset
V_BCKP (RTC)
Vcc (Supply)
V_INT (I/O)
Digital Audio (I2S)
AnalogAudio
Wireless
Base-band
Processor
Memory
Power Management Unit
26 MHz
32.768 kHz
ANT
Switch & Multi band & mode PA
DDC (for GPS)
(U)SIM Card
UART
SPI
USB
GPIO(s)
Power On
External Reset
V_BCKP (RTC)
Vcc (Supply)
V_INT (I/O)
Digital Audio (I2S)
RF
SWITCH
RF
Transceiver
Duplexers
& Filters
ANT_DIV
RF
SWITCH
Filter
Bank
PA
PMU
Transceiver
PMU
LISA-U series - System Integration Manual
Figure 1: LISA-U1 series block diagram (for available options refer to the product features summary in Table 2)
Figure 2: LISA-U2 series block diagram (for available options refer to the product features summary in Table 2)
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1.2.1 Functional blocks

LISA-U series modules consist of the following internal functional blocks: RF section, Baseband and Power Management Unit section.
LISA-U1 series RF section
A shielding box includes the RF high-power signal circuitry, namely:
Front-End Module (FEM) with integrated quad-band 2G Power Amplifier and antenna switch multiplexer Two single-band 3G HSPA/WCDMA Power Amplifier modules with integrated duplexers
The RF antenna pad (ANT) is directly connected to the FEM, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied to integrated SAW filters for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the 2G power amplifier module and then directed to the antenna through the FEM. The 3G transmitter and receiver are instead active at the same time due to frequency-domain duplex operation. The switch integrated in the FEM connects the antenna port to the passive duplexer which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the fixed gain linear power amplifier.
In the same shielding box that includes the RF high-power signal circuitry there are all the low-level analog RF components, namely:
Dual-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO) Low Noise Amplifier (LNA) and SAW RF filters for 2G and 3G receivers
While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the external LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing.
For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted.
In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal.
The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode.
LISA-U2 series RF section
A shielding box contains the RF high-power signal circuitry, including:
Multimode Single Chain Power Amplifier Module used for 3G HSPA/WCDMA and 2G EDGE/GSM operations Power Management Unit with integrated DC/DC converter for the Power Amplifier Module
The RF antenna pad (ANT) is directly connected to the main antenna switch, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied by the main antenna switch to the duplexer SAW filter bank for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the power amplifier and then directed to the antenna pad through the main antenna switch. The 3G transmitter and receiver are active at the same time due to frequency ­domain duplex operation. The switch integrated in the main antenna switch connects the antenna port to the duplexer SAW filter bank which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the power amplifier.
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A separated shielding box contains all the other analog RF components, including:
Main Antenna Switch Duplexer SAW filter bank Antenna Switch for diversity receiver SAW filter bank for diversity receiver Six-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Power Management Unit with integrated DC/DC converter for the Power Amplifier Module Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO)
While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the integrated LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing.
For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to the baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted.
The RF antenna pad for the diversity receiver (ANT_DIV) available on LISA-U230 modules is directly connected to the antenna switch for the diversity receiver, which dispatches the incoming RF signals to the dedicated SAW filter bank for out-of-band rejection and then to the diversity receiver port of the RF transceiver.
In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal.
The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode.
LISA-U series modulation techniques
Modulation techniques related to radio technologies supported by LISA-U series modules, are listed as follows:
GSM GSMK GPRS GMSK EDGE GMSK / 8-PSK WCDMA QPSK HSDPA QPSK / 16-QAM HSUPA QPSK / 16-QAM
LISA-U series Baseband and Power Management Unit section
Another shielding box of LISA-U series modules includes all the digital circuitry and the power supplies, basically the following functional blocks:
Wireless baseband processor, a mixed signal ASIC which integrates:
Microprocessor for controller functions, 2G & 3G upper layer software DSP core for 2G Layer 1 and audio processing 3G coprocessor and HW accelerator for 3G Layer 1 control software and routines Dedicated HW for interfaces management
Memory system in a Multi-Chip Package (MCP) integrating two devices:
NOR flash non-volatile memory DDR SRAM volatile memory
Power Management Unit (PMU), used to derive all the system supply voltages from the module supply VCC
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Characteristic
LISA-U1 series
LISA-U2 series
3G bands
LISA-U100, LISA-U120:
Band II (1900 MHz), Band V (850 MHz)
LISA-U110, LISA-U130:
Band I (2100 MHz), Band VIII (900 MHz)
LISA-U200-00:
Band I (2100 MHz), Band II (1900 MHz),
Band V (850 MHz), Band VI (800 MHz)
LISA-U200-01, LISA-U230:
Band I (2100 MHz), Band II (1900 MHz),
Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz)
HSDPA data rate
LISA-U1 series:
HSDPA category 8, up to 7.2 Mb/s DL
LISA-U200:
HSDPA category 8, up to 7.2 Mb/s DL
LISA-U230:
HSDPA category 14, up to 21.1 Mb/s DL
EDGE/GPRS data rate
EDGE multislot class 12, MCS1-MCS9, up to 236.8 kb/s DL/UL GPRS multislot class 12, CS1-CS4, up to 85.6 kb/s DL/UL
EDGE multislot class 33, MCS1-MCS9, up to 296 kb/s DL, 236.8 kb/s UL GPRS multislot class 33, CS1-CS4, up to 107 kb/s DL, 85.6 kb/s UL
Rx diversity
LISA-U1 series:
Not supported
LISA-U200:
Not supported
LISA-U230:
Supported: ANT_DIV RF input for Rx diversity
Analog audio
LISA-U100, LISA-U110:
Not supported
LISA-U120, LISA-U130:
One differential input, one differential output
LISA-U2 series:
Not supported
Digital audio
LISA-U100, LISA-U110:
Not supported
LISA-U120, LISA-U130:
One 4-wire digital audio interface
LISA-U200-00:
Not supported
LISA-U200-01, LISA-U230:
Two 4-wire digital audio interfaces CODEC_CLK clock output for external codec
GPIO
5 GPIOs
Up to 14 GPIOs
VCC operating range
VCC normal operating range: 3.4 V – 4.2 V VCC extended operating range: 3.1 V – 4.2 V
VCC normal operating range: 3.3 V – 4.4 V VCC extended operating range: 3.1 V – 4.5 V
V_BCKP operating range
V_BCKP output: 2.3 V typ. V_BCKP input: 1.0 V – 2.5 V
V_BCKP output: 1.8 V typ. V_BCKP input: 1.0 V – 1.9 V
Exposed GND area
One signals keep-out area on the top layer of the application board, due to one exposed GND area on the bottom layer of the module (see Figure 61)
Two signals keep-out areas on the top layer of the application board, due to two exposed GND areas on the bottom layer of the module (see Figure 62)
32.768 kHz crystal, connected to the Real Time Clock (RTC) oscillator to provide the clock reference in idle or
power-off mode

1.2.2 Hardware differences between LISA-U series modules

Main hardware differences between the LISA-U series modules are summarized in Table 3.
Table 3: Main hardware differences between LISA-U series modules
For additional details and minor hardware differences between the LISA-U series modules, refer to section A.3.
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Function
Pin
Module
No
I/O
Description
Remarks
Power
VCC
All
61, 62, 63
I
Module supply input
Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided has to be always above the minimum limit of the operating range. Consider that there are large current spikes in connected mode, when a GSM call is enabled. VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize power loss due to series resistance. See section 1.5.2
GND
All
1, 3, 6, 7, 8, 17, 25, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 60, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76
N/A
Ground
GND pins are internally connected but a good (low impedance) external ground connection can improve RF performance: all GND pins must be externally connected to ground.
V_BCKP
All 2 I/O
Real Time Clock supply input/output
V_BCKP = 2.3 V (typical) on LISA-U1 series V_BCKP = 1.8 V (typical) on LISA-U2 series
generated by the module when VCC supply voltage is within valid operating range. See section 1.5.4
V_INT
All 4 O
Digital Interfaces supply output
V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level.
See section 1.5.5
VSIM
All
50 O SIM supply output
VSIM = 1.80 V typical or 2.90 V typical generated by the module according to the SIM card type. See section 1.8
RF
ANT
All
68
I/O
RF input/output for main Tx/Rx antenna
50 nominal impedance. See section 1.7, section 2.4 and section 2.2.1.1
ANT_DIV
LISA-U230
74 I RF input for Rx diversity antenna
50 Ω nominal impedance See section 1.7, section 2.4 and section 2.2.1.1
SIM
SIM_IO
All
48
I/O
SIM data
Internal 4.7 k pull-up to VSIM. Must meet SIM specifications. See section 1.8
SIM_CLK
All
47 O SIM clock
Must meet SIM specifications. See section 1.8
SIM_RST
All
49 O SIM reset
Must meet SIM specifications. See section 1.8
SPI
SPI_MISO
All
57 O SPI Data Line Output
Module Output: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. See section 1.9.4
SPI_MOSI
All
56 I SPI Data Line Input
Module Input: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.4

1.3 Pin-out

Table 4 lists the pin-out of the LISA-U series modules, with pins grouped by function.
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Function
Pin
Module
No
I/O
Description
Remarks
SPI_SCLK
All
55 I SPI Serial Clock Input
Module Input: module runs as an SPI slave. Idle low (CPOL=0). Internal active pull-down to GND enabled. See section 1.9.4
SPI_SRDY
All
58 O SPI Slave Ready Output
Module Output: module runs as an SPI slave. Idle low. See section 1.9.4
SPI_MRDY
All
59 I SPI Master Ready Input
Module Input: module runs as an SPI slave. Idle low. Internal active pull- down to GND enabled. See section 1.9.4
DDC
SCL
All
45 O I2C bus clock line
Fixed open drain. External pull-up required.
See section 1.10
SDA
All
46
I/O
I2C bus data line
Fixed open drain. External pull-up required.
See section 1.10
UART
RxD
All
16 O UART data output
Circuit 104 (RxD) in ITU-T V.24. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2
TxD
All
15 I UART data input
Circuit 103 (TxD) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for FW update and
debugging if the USB interface is connected to the application processor. See section 1.9.2
CTS
All
14 O UART clear to send output
Circuit 106 (CTS) in ITU-T V.24. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2
RTS
All
13 I UART ready to send input
Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2
DSR
All 9 O
UART data set ready output
Circuit 107 (DSR) in ITU-T V.24. See section 1.9.2
RI
All
10 O UART ring indicator output
Circuit 125 (RI) in ITU-T V.24. See section 1.9.2
DTR
All
12 I UART data terminal ready input
Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.2
DCD
All
11 O UART data carrier detect output
Circuit 109 (DCD) in ITU-T V.24. See section 1.9.2
GPIO
GPIO1
All
20
I/O
GPIO
See section 1.12
GPIO2
All
21
I/O
GPIO
See section 1.12
GPIO3
All
23
I/O
GPIO
See section 1.12
GPIO4
All
24
I/O
GPIO
See section 1.12
GPIO5
All
51
I/O
GPIO
See section 1.12
GPIO6
LISA-U2
39
I/O
GPIO
See section 1.12
GPIO7
LISA-U2
40
I/O
GPIO
See section 1.12
GPIO8
LISA-U2
53
I/O
GPIO
See section 1.12
GPIO9
LISA-U2
54
I/O
GPIO
See section 1.12
GPIO10
LISA-U200-01 LISA-U230
55
I/O
GPIO
See section 1.12
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Function
Pin
Module
No
I/O
Description
Remarks
GPIO11
LISA-U200-01 LISA-U230
56
I/O
GPIO
See section 1.12
GPIO12
LISA-U200-01 LISA-U230
57
I/O
GPIO
See section 1.12
GPIO13
LISA-U200-01 LISA-U230
58
I/O
GPIO
See section 1.12
GPIO14
LISA-U200-01 LISA-U230
59
I/O
GPIO
See section 1.12
USB
VUSB_DET
All
18 I USB detect input
Input for VBUS (5 V typical) USB supply sense to enable USB interface. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3
USB_D-
All
26
I/O
USB Data Line D-
90 Ω nominal differential impedance Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3
USB_D+
All
27
I/O
USB Data Line D+
90 Ω nominal differential impedance Pull-up or pull-down resistors and external series
resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor.
See section 1.9.3
System
PWR_ON
All
19 I Power-on input
PWR_ON pin has high input impedance. Do not keep floating in noisy environment: external pull-up required. See section 1.6.1
RESET_N
All
22 I External reset input
Internal 10 kΩ pull-up to V_BCKP. See section 1.6.3
Analog Audio
MIC_N
LISA-U120 LISA-U130
39 I Differential analog audio input (negative)
Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1
MIC_P
LISA-U120 LISA-U130
40 I Differential analog audio input (positive)
Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1
SPK_P
LISA-U120 LISA-U130
53 O Differential analog audio output (positive)
Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode.
See section 1.11.1
SPK_N
LISA-U120 LISA-U130
54 O Differential analog audio output (negative)
Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode.
See section 1.11.1
Digital Audio
I2S_CLK
LISA-U120 LISA-U130 LISA-U200-01 LISA-U230
43
I/O
First I2S clock
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
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Function
Pin
Module
No
I/O
Description
Remarks
I2S_RXD
LISA-U120 LISA-U130
LISA-U200-01 LISA-U230
44 I First I2S receive data
Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S_TXD
LISA-U120 LISA-U130 LISA-U200-01 LISA-U230
42 O First I2S transmit data
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S_WA
LISA-U120 LISA-U130 LISA-U200-01 LISA-U230
41
I/O
First I2S word alignment
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S1_CLK
LISA-U200-01, LISA-U230
53
I/O
Second I2S clock
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S1_RXD
LISA-U200-01 LISA-U230
39 I Second I2S receive data
Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S1_TXD
LISA-U200-01 LISA-U230
40 O Second I2S transmit data
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
I2S1_WA
LISA-U200-01 LISA-U230
54
I/O
Second I2S word alignment
Check device specifications to ensure compatibility to module supported modes. See section 1.11.2.
CODEC_CLK
LISA-U200-01 LISA-U230
52 O Clock output
Digital clock output for external audio codec See section 1.11.2.
Reserved
RSVD
All 5 N/A
RESERVED pin
This pin must be connected to ground See section 1.13
RSVD
LISA-U1 LISA-U200-00
52
N/A
RESERVED pin
Pad disabled See section 1.13
RSVD
LISA-U1 LISA-U200
74
N/A
RESERVED pin
Do not connect See section 1.13
RSVD
LISA-U100 LISA-U110 LISA-U200-00
43
N/A
RESERVED pin
Pad disabled See section 1.13
RSVD
LISA-U100 LISA-U110 LISA-U200-00
44
N/A
RESERVED pin
Pad disabled See section 1.13
RSVD
LISA-U100 LISA-U110 LISA-U200-00
42
N/A
RESERVED pin
Pad disabled See section 1.13
RSVD
LISA-U100 LISA-U110 LISA-U200-00
41
N/A
RESERVED pin
Pad disabled See section 1.13
RSVD
LISA-U100 LISA-U110
39
N/A
RESERVED pin
Do not connect See section 1.13
RSVD
LISA-U100 LISA-U110
40
N/A
RESERVED pin
Do not connect See section 1.13
RSVD
LISA-U100 LISA-U110
53
N/A
RESERVED pin
Do not connect See section 1.13
RSVD
LISA-U100 LISA-U110
54
N/A
RESERVED pin
Do not connect See section 1.13
Table 4: LISA-U series modules pin definition, grouped by function
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Operating Mode
Description
Features / Remarks
Transition condition
General Status: Power-down
Not-Powered
Mode
VCC supply not present or
below operating range. Microprocessor switched off (not operating). RTC only operates if supplied through V_BCKP pin.
Module is switched off. Application interfaces are not accessible. Internal RTC timer operates only if a valid voltage is applied to V_BCKP pin.
Module cannot be switched on by a low level on the PWR_ON input, by a rising edge on the RESET_N input, or by a preset RTC alarm. Module can be switched on applying
VCC supply.
Power-Off Mode
VCC supply within operating
range. Microprocessor switched off (not operating). Only RTC runs.
Module is switched off: normal shutdown by AT+CPWROFF command (refer to u-blox AT Commands Manual [3]), or by PWR_ON held low for more than 1 s (LISA-U2xx-01 only).
Application interfaces are not accessible. Only the internal RTC timer in operation.
Module can be switched on by a low level on the PWR_ON input, by a rising edge on the RESET_N input, or by a preset RTC alarm.
General Status: Normal Operation
Idle-Mode
Microprocessor runs with 32 kHz as reference oscillator. Module does not accept data signals from an external device.
If power saving is enabled, the module automatically enters idle-mode whenever possible.
Application interfaces are disabled. If hardware flow control is enabled, the CTS line to ON state indicates that the module is in active mode and the UART interface is enabled: the line is driven in the OFF state when the module is not prepared to accept data by the UART interface. If hardware flow control is disabled, the CTS line is fixed to ON state. Module by default is not set to automatically enter idle-mode whenever possible, unless power saving configuration is enabled by appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV).
Module enters automatically idle-mode when power saving is enabled and there is no activity for the defined time interval:
Module registered with the
network and power saving enabled. Periodically wakes up to active mode to monitor the paging channel for the paging block reception according to network indication
Module not registered with the
network and power saving is enabled. Periodically wakes up to
monitor external activity Module wakes up from idle-mode to active-mode in the following events:
Incoming voice or data call RTC alarm occurs Data received on UART interface
(refer to 1.9.2)
RTS input line set to the ON state
by the DTE if the AT+UPSV=2
command is sent to the module
(refer to 1.9.2)
USB detection, applying 5 V (typ.)
to the VUSB_DET pin
The connected USB host forces a
remote wakeup of the module as
USB device (refer to 1.9.3)
The connected SPI master indicates
to the module that it is ready for
transmission or reception, by the
SPI/IPC SPI_MRDY input signal
(refer to 1.9.4)

1.4 Operating modes

LISA-U series modules have several operating modes. Table 5 summarizes the various operating modes and provides general guidelines for operation.
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Operating Mode
Description
Features / Remarks
Transition condition
Active-Mode
Microprocessor runs with 26 MHz as reference oscillator. The module is prepared to accept data signals from an external device.
Module is switched on and is fully active. The application interfaces are enabled, unless power saving configuration is
enabled by the AT+UPSV command (refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3]). Power saving is not enabled by default: it can be enabled by the AT+UPSV command (see u-blox AT Commands Manual [3]).
If power saving is enabled, the module automatically enters idle-mode and application interfaces are disabled whenever possible (refer to sections
1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3], AT+UPSV).
Connected-Mode
Voice or data call enabled. Microprocessor runs with
26 MHz as reference oscillator. The module is prepared to accept data signals from an external device.
The module is switched on and a voice call or a data call (2G/3G) is in progress. Module is fully active. The application interfaces are enabled, unless power saving configuration is enabled by the AT+UPSV command (see section 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [3]).
When call terminates, the module returns to the active operating mode.
Table 5: Module operating modes summary
Switch ON:
Apply VCC
If power saving is enabled and there is no activity for a defined time interval
Any wake up event described
in the module operating modes summary table above
Incoming/outgoing call or other dedicated device network communication
Call terminated,
communication dropped
Remove VCC
Switch ON:
PWR_ON
RESET_N
RTC Alarm
Not
powered
Power off
ActiveConnected Idle
Switch OFF:
AT+CPWROFF
PWR_ON (LISA-U2xx-01 only)
Transition between the different modes is described in Figure 3.
LISA-U series - System Integration Manual
Figure 3: Operating modes transition
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Baseband Processor
2G/3G
Power Amplifier(s)
Switching
Step-Down
5 x 10 µF
61
VCC
62
VCC
63
VCC
50
VSIM
2
V_BCKP
4
V_INT
Linear
LDO
Linear
LDO
Switching
Step-Down
Linear
LDO
Linear
LDO
Linear
LDO
I/O
EBU
CORE
Analog
SIM
RTC
NOR Flash
DDR SRAM
RF Transceiver
Memory
Power Management Unit
22 µF
10 µF (LISA-U1) 220 nF (LISA-U2)
220 nF
2G/3G PA
PMU
(LISA-U2)
Transceiver
PMU
(LISA-U2)
(LISA-U1)

1.5 Power management

1.5.1 Power supply circuit overview

LISA-U series modules feature a power management concept optimized for the most efficient use of supplied power. This is achieved by hardware design utilizing a power efficient circuit topology (Figure 4), and by power management software controlling the module’s power saving mode.
Figure 4: LISA-U series power management simplified block diagram
Pins with supply function are reported in Table 6, Table 11 and Table 14. LISA-U series modules must be supplied via the VCC pins. There is only one main power supply input, available
on the three VCC pins that must be all connected to the external power supply
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Name
Description
Remarks
VCC
Module power supply input
VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range. Consider that during a GSM call there are large current spikes in connected mode.
GND
Ground
GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads must be connected to ground.
The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit (PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators.
V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time Clock can be externally supplied via the V_BCKP pin (see section 1.5.4).
When a 1.8 V or a 3 V SIM card type is connected, LISA-U series modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance to the ISO-IEC 7816-3 specifications.
The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-U series modules in the final application.
The integrated Power Management Unit also provides the control state machine for system start up and system reset control.

1.5.2 Module supply (VCC)

The LISA-U series modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system power supply circuit is able to support peak power (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the detailed specifications).
Table 6: Module supply pins
VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level can be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point.
The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage normal operating range.
The module cannot be switched on if the VCC voltage value is below the specified normal operating
range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for more than 3 s after the start of the module switch-on sequence.
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Time
undershoot
overshoot
ripple
ripple
drop
Voltage
3.8 V
(typ)
RX slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
When LISA-U series modules are in operation, the voltage provided to VCC pins can go outside the normal operating range limits but must be within the extended operating range limits specified in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Occasional deviations from the ETSI specifications may occur when the input voltage at VCC pins is outside the normal operating range and is within the extended operating range.
LISA-U series modules switch off when VCC voltage value drops below the specified extended operating
range minimum limit: ensure that the input voltage at VCC pins never drops below the minimum limit of the extended operating range when the module is switched on, not even during a GSM transmit burst, where the current consumption can rise up to maximum peaks of 2.5 A in case of a mismatched antenna load.
Operation above the normal operating range maximum limit is not recommended and
extended exposure beyond it may affect device reliability.
Stress beyond the VCC absolute maximum ratings can cause permanent damage to the
module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection.
When designing the power supply for the application, pay specific attention to power losses and
transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics:
o Voltage drop during transmit slots must be lower than 400 mV o No undershoot or overshoot at the start and at the end of transmit slots o Voltage ripple during transmit slots must be minimized:
lower than 70 mVpp if f
lower than 10 mVpp if 200 kHz < f lower than 2 mVpp if f
200 kHz
ripple
> 400 kHz
ripple
400 kHz
ripple
Figure 5: Description of the VCC voltage profile versus time during a GSM call
Any degradation in power supply performance (due to losses, noise or transients) will directly affect the
RF performance of the module since the single external DC power source indirectly supplies all the digital and analog interfaces, and also directly supplies the RF power amplifier (PA).
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Main Supply
Available?
Battery
Li-Ion 3.7 V
Linear LDO
Regulator
Main Supply
Voltage
>5 V?
Switching
Step-Down
Regulator
No, portable device
No, less than 5 V
Yes, greater than 5 V
Yes, always available
The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms. This VCC slope allows a proper
switch on of the module when the voltage rises to the VCC normal operating range from a voltage of less than 2.25 V. If the external supply circuit cannot raise the VCC voltage from 2.5 V to 3.2 V within 1 ms RESET_N should be kept low during VCC rising edge, so that the module will switch on releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal operating range.
1.5.2.1 VCC application circuits
LISA-U series modules must be supplied through the VCC pins by one (and only one) proper DC power supply that must be one of the following:
Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery
Figure 6: VCC supply concept selection
The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the LISA-U series modules operating supply voltage. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source.
The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less than 5 V). In this case the typical 90% efficiency of the switching regulator will diminish the benefit of voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy in thermal power.
If LISA-U series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided.
The use of primary (not rechargeable) battery is uncommon, since the most cells available are seldom capable of delivering the burst peak current for a GSM call due to high internal resistance.
Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in LISA-U series modules). The charger circuit should be designed in order to prevent over-voltage on VCC beyond the upper limit of the absolute maximum rating.
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LISA-U series
12V
C5
R3
C4
R2
C2C1
R1
VIN
RUN
VC
RT
PG
SYNC
BD
BOOST
SW
FB
GND
6
7
10
9
5
C6
1
2
3
8
11
4
C7 C8
D1
R4
R5
L1
C3
U1
62
VCC
63
VCC
61
VCC
GND
The following sections highlight some design aspects for each of the supplies listed above.
Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements:
Power capability: the switching regulator with its output circuit must be capable of providing a voltage
value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current pulses with 1/8 duty cycle to the VCC pins
Low output ripple: the switching regulator together with its output circuit must be capable of providing a
clean (low noise) VCC voltage profile
High switching frequency: for best performance and for smaller applications select a switching frequency
600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors
PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in
active mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the module changes status from idle/active mode to connected mode (where current consumption increases to a value greater than 100 mA): it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA)
Output voltage slope: the use of the soft start function provided by some voltage regulator must be
carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module
Figure 7 and the components listed in Table 7 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high: switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply.
Figure 7: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator
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Reference
Description
Part Number - Manufacturer
C1
10 µF Capacitor Ceramic X7R 5750 15% 50 V
C5750X7R1H106MB - TDK
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
680 pF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71H681KA01 - Murata
C4
22 pF Capacitor Ceramic COG 0402 5% 25 V
GRM1555C1H220JZ01 - Murata
C5
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C6
470 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E474KA12 - Murata
C7
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 - Murata
C8
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
D1
Schottky Diode 40 V 3 A
MBRA340T3G - ON Semiconductor
L1
10 µH Inductor 744066100 30% 3.6 A
744066100 - Wurth Electronics
R1
470 k Resistor 0402 5% 0.1 W
2322-705-87474-L - Yageo
R2
15 k Resistor 0402 5% 0.1 W
2322-705-87153-L - Yageo
R3
22 k Resistor 0402 5% 0.1 W
2322-705-87223-L - Yageo
R4
390 k Resistor 0402 1% 0.063 W
RC0402FR-07390KL - Yageo
R5
100 k Resistor 0402 5% 0.1 W
2322-705-70104-L - Yageo
U1
Step Down Regulator MSOP10 3.5 A 2.4 MHz
LT3972IMSE#PBF - Linear Technology
5V
C1 R1
IN OUT
ADJ
GND
1
2
4
5
3
C2R2
R3
U1
SHDN
LISA-U series
62
VCC
63
VCC
61
VCC
GND
C3
Table 7: Suggested components for the VCC voltage supply application circuit using a step-down regulator
Low Drop-Out (LDO) linear regulator
The characteristics of the LDO linear regulator connected to the VCC pins should meet the following requirements:
Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper
voltage value to the VCC pins and of delivering 2.5 A current pulses with 1/8 duty cycle
Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its
junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator)
Output voltage slope: the use of the soft start function provided by some voltage regulators must be
carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module
Figure 8 and the components listed in Table 8 show an example of a power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering 2.5 A current pulses, with proper power handling capability. The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to the 3.8 V typical value of the VCC supply.
Figure 8: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator
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Reference
Description
Part Number - Manufacturer
C1, C2
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
C3
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
R1
47 k Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
2.2 k Resistor 0402 5% 0.1 W
RC0402JR-072K2L - Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LT1764AEQ#PBF - Linear Technology
Table 8: Suggested components for VCC voltage supply application circuit using an LDO linear regulator
Rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following requirements:
Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be
capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption to VCC pins. The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour
DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a
VCC voltage drop greater than 400 mV during transmit bursts
Primary (disposable) battery
The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following requirements:
Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be
capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption at the VCC pins. The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour
DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a
VCC voltage drop greater than 400 mV during transmit bursts
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3V8
C1 C4
GND
C3C2
C5
LISA-U series
62
VCC
63
VCC
61
VCC
+
Reference
Description
Part Number - Manufacturer
C1
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C3
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C4
39 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E390JA01 - Murata
C5
10 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E100JA01 - Murata
Additional recommendations for the VCC supply application circuits
To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines (connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible in order to minimize power losses.
Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. Even if all the VCC pins and all the GND pins are internally connected within the module, it is recommended to properly connect all of them to supply the module in order to minimize series resistance losses.
To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a GSM call (when current consumption on the VCC supply can rise up to as much as 2.5 A in the worst case), place a capacitor with large capacitance (more than 100 µF) and low ESR near the VCC pins, for example:
330 µF capacitance, 45 mΩ ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)
The use of very large capacitors (i.e. greater then 1000 µF) on the VCC line and the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch on of the module.
To reduce voltage ripple and noise, place the following near the VCC pins:
100 nF capacitor (e.g Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources 10 pF capacitor (e.g. Murata GRM1555C1E100J) to filter EMI in the 1800 / 1900 / 2100 MHz bands 39 pF capacitor (e.g. Murata GRM1555C1E390J) to filter EMI in the 850 / 900 MHz bands
Figure 9 shows the complete configuration but the mounting of each single component depends on the
application design.
Figure 9: Suggested schematic design to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops
Table 9: Suggested components to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops
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C5 C8
GND
C7C6 C9
LISA-U series
62
VCC
63
VCC
61
VCC
+
USB
Supply
C3
R4
θ
U1
IUSB
IAC
IEND
TPRG
SD
VIN
VINSNS
MODE
ISEL
C2C1
5V0
TH
GND
VOUT
VOSNS
VREF
R1
R2
R3
Li-Ion/Li-Pol
Battery Pack
D1
B1
C4
Li-Ion/Li-Polymer Battery Charger IC
Reference
Description
Part Number - Manufacturer
B1
Li-Ion (or Li-Polymer) battery pack with 470 Ω NTC
Various manufacturer
C1, C4
1 µF Capacitor Ceramic X7R 0603 10% 16 V
GRM188R71C105KA12 - Murata
C2, C6
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
1 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H102KA01 - Murata
C5
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C7
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C8
39 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E390JA01 - Murata
C9
10 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E100JA01 - Murata
D1
Low Capacitance ESD Protection
USB0002RP or USB0002DP - AVX
R1, R2
24 k Resistor 0402 5% 0.1 W
RC0402JR-0724KL - Yageo Phycomp
R3
3.3 k Resistor 0402 5% 0.1 W
RC0402JR-073K3L - Yageo Phycomp
R4
1.0 k Resistor 0402 5% 0.1 W
RC0402JR-071K0L - Yageo Phycomp
U1
Single Cell Li-Ion (or Li-Polymer) Battery Charger IC for USB port and AC Adapter
L6924U - STMicroelectronics
External battery charging application circuit
LISA-U series modules don’t have an on-board charging circuit. An example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell, is provided in Figure 10.
In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse and DC discharge current capabilities and proper DC series resistance, is directly connected to the VCC supply input of LISA-U series module. Battery charging is completely managed by the STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges as a linear charger the battery, in three phases:
Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a
low current, set to 10% of the fast-charge current
Fast-charge constant current: the battery is charged with the maximum current, configured by the value
of an external resistor to a value suitable for USB power source (~500 mA)
Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the L6924U
starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor to ~15 mA or when the charging timer reaches the value configured by an external capacitor to ~9800 s
Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions.
Alternatively the L6924U, providing input voltage range up to 12 V, can charge from an AC wall adapter. When a current-limited adapter is used, it can operate in quasi-pulse mode, reducing power dissipation.
Figure 10: Li-Ion (or Li-Polymer) battery charging application circuit
Table 10: Suggested components for Li-Ion (or Li-Polymer) battery charging application circuit
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Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-130 mA
2500 mA
Peak current
depends on
TX power
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
2.5
2.0
60-130 mA
10-40 mA

1.5.3 Current consumption profiles

During operation, the current drawn by the LISA-U series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in 2G connected mode, to continuous high current drawn in UMTS connected mode, to the low current consumption during power saving in idle-mode.
1.5.3.1 2G connected mode
When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM 900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is in GSM connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than the one in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]).
During a GSM call, current consumption is in the order of 60-130 mA in receiving or in monitor bursts and is about 10-40 mA in the inactive unused bursts (low current period). The more relevant contribution to determine the average current consumption is set by the transmitted power in the transmit slot.
An example of current consumption profile of the data module in GSM talk mode is shown in Figure 11.
Figure 11: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot), with VCC=3.8 V
When a GPRS connection is established there is a different VCC current consumption profile also determined by the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current consumption is not as high as can be in case of a GSM call.
If the module transmits in GPRS class 12 or class 33 connected mode in the GSM 850 or in the E-GSM 900 band at the maximum power control level, the current consumption can reach up to 1600 mA (with unmatched
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Time [ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200mA
60-130mA
Peak current
depends on
TX power
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
2.5
2.0
1600 mA
60-130mA
10-40mA
antenna). This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]).
Figure 12 reports the current consumption profiles in GPRS class 12 connected mode, in the GSM 850 or in the E-GSM 900 band, with 4 slots used to transmit and 1 slot used to receive.
Figure 12: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot), with VCC=3.8 V
In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 12, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well.
LISA-U2 series modules support GPRS and EDGE class 33: up to 4 slots can be used to transmit, as in the class 12 mode, and up to 2 slots can be used to receive in the same frame since up to 6 slots can be used in total. So, the VCC current consumption figures in GPRS and EDGE class 33 connected modes are similar to the current profile in GPRS and EDGE class 12 connected modes, since the same number of transmit slots are used.
1.5.3.2 3G connected mode
During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a maximum rate of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case. In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the order of continuous 500-800 mA (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for detailed values). Even at lowest output RF power (approximately 0.01 µW or -50 dBm), the current still remains in the order of 200 mA due to module baseband processing and transceiver activity.
An example of current consumption profile of the data module in UMTS/HSxPA continuous transmission mode is shown in Figure 13.
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Time
[ms]
3G frame
10 ms
(1 frame = 15 slots)
Current [mA]
Depends
on TX
power
170 mA
1 slot
666 µs
850 mA
0
300
200
100
500
400
600
700
800
Figure 13: VCC current consumption profile versus time during a UMTS/HSPA connection, with VCC=3.8 V
When a packet data connection is established, the actual current profile depends on the amount of transmitted packets; there might be some periods of inactivity between allocated slots where current consumption drops about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher quality signal required by the network to cope with enhanced data speed.
1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled)
The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible.
When power saving is enabled, the module is registered or attached to a network and a voice or data call is not enabled, the module automatically enters idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to GSM system requirements. When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging block. In between, the module switches to idle-mode. This is known as GSM discontinuous reception (DRX).
The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode.
The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell.
In case of 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX = 2, i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX = 9, i.e. width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms).
In case of 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of 26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms = 5120 ms).
An example of a module current consumption profile is shown in Figure 14: the module is registered with the network (2G or 3G), automatically enters idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception.
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