Abstract
This document describes the features and the integration of the
LISA-U1 series HSPA wireless modules.
These modules are a complete and cost efficient 3.75G solution
offering high-speed dual-band HSDPA/HSUPA and quad-band
GSM/GPRS voice and/or data transmission technology in a compact
form factor.
locate, communicate, accelerate
33.2 x 22.4 x 2.7 mm
www.u-blox.com
LISA-U1 series
3.75G UMTS/HSPA
Wireless Modules
System Integration Manual
LISA-U1 series - System Integration Manual
Document Information
Title
LISA-U1 series
Subtitle
3.75G UMTS/HSPA
Wireless Modules
Document type
System Integration Manual
Document number
3G.G2-HW-10002-3
Document status
Preliminary
Document status information
Objective
Specification
This document contains target values. Revised and supplementary data will be published
later.
Advance
Information
This document contains data based on early testing. Revised and supplementary data will
be published later.
Preliminary
This document contains data from product verification. Revised and supplementary data
may be published later.
Released
This document contains the final product specification.
Name
Type number
Firmware version
PCN / IN
LISA-U100
LISA-U100-00S-00
10.72
n.a.
LISA-U110
LISA-U110-00S-00
10.72
n.a.
LISA-U120
LISA-U120-00S-00
10.72
n.a.
LISA-U130
LISA-U130-00S-00
10.72
n.a.
This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They
can be downloaded from www.u-blox.com.
u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make
changes to specifications and product descriptions at any time without notice.
u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without
express permission is strictly prohibited. Copyright © 2011, u-blox AG.
u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries.
This document applies to the following products:
3G.G2-HW-10002-3
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LISA-U1 series - System Integration Manual
Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
AT Commands Manual: This document provides the description of the supported AT commands by the
LISA-U1 series module to verify all implemented functionalities.
System Integration Manual: This Manual provides hardware design instructions and information on how to
set up production and final product tests.
Application Note: document provides general design instructions and information that applies to all u-blox
Wireless modules. See Section Related documents for a list of Application Notes related to your Wireless
Module.
How to use this Manual
The LISA-U1 series System Integration Manual provides the necessary information to successfully design in and
configure these u-blox wireless modules.
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox Wireless Integration, please:
Read this manual carefully.
Contact our information service on the homepage http://www.u-blox.com
Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com
Technical Support
Worldwide Web
Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and
helpful FAQ can be accessed 24h a day.
By E-mail
Contact the nearest of the Technical Support offices by email. Use our service pool email addresses rather than
any personal email address of our staff. This makes sure that your request is processed as soon as possible. You
will find the contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support please have the following information ready:
Module type (e.g. LISA-U100) and firmware version
Module configuration
Clear description of your question or the problem
A short description of the application
Your complete contact details
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Contents
Preface ................................................................................................................................ 3
Contents .............................................................................................................................. 4
1 System description ....................................................................................................... 7
1.1 Overview .............................................................................................................................................. 7
1.2 Architecture .......................................................................................................................................... 8
1.2.1 Functional blocks ........................................................................................................................... 9
1.2.2 Hardware differences between LISA-U1 series modules ............................................................... 10
1.3 Pin-out ............................................................................................................................................... 11
1.4 Operating modes ................................................................................................................................ 15
1.5 Power management ........................................................................................................................... 17
1.5.1 Power supply circuit overview ...................................................................................................... 17
1.5.2 Module supply (VCC) .................................................................................................................. 18
1.5.3 Current consumption profiles ...................................................................................................... 25
1.5.4 RTC Supply (V_BCKP) .................................................................................................................. 29
1.5.5 Interface supply (V_INT) ............................................................................................................... 31
1.6 System functions ................................................................................................................................ 32
1.6.1 Module power on ....................................................................................................................... 32
1.6.2 Module power off ....................................................................................................................... 36
1.6.3 Module reset ............................................................................................................................... 37
1.7 RF connection ..................................................................................................................................... 38
1.8 (U)SIM interface .................................................................................................................................. 39
1.8.1 (U)SIM functionality ..................................................................................................................... 41
1.9 Serial communication ......................................................................................................................... 42
1.9.1 Serial interfaces configuration ..................................................................................................... 42
1.9.2 Asynchronous serial interface (UART)........................................................................................... 43
1.9.3 USB interface............................................................................................................................... 56
1.9.4 SPI interface ................................................................................................................................ 58
1.9.5 MUX Protocol (3GPP 27.010) ...................................................................................................... 63
1.10 DDC (I2C) interface .......................................................................................................................... 63
1.10.1 Overview ..................................................................................................................................... 63
1.10.2 DDC application circuit ................................................................................................................ 64
1.11 Audio Interface (LISA-U120 and LISA-U130 only) ............................................................................ 67
1.11.1 Analog Audio interface ............................................................................................................... 67
1.11.2 Digital Audio interface ................................................................................................................. 74
1.11.3 Voiceband processing system ...................................................................................................... 76
1.12 General Purpose Input/Output (GPIO) ............................................................................................. 78
1.12.1 GPIO functions available in upcoming FW version ........................................................................ 81
1.13 Reserved pins (RSVD) ...................................................................................................................... 83
1.14 Schematic for LISA-U1 series module integration ............................................................................ 84
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1.15 Approvals ........................................................................................................................................ 85
1.15.1 R&TTED and European Conformance CE mark ............................................................................ 85
1.15.2 IC ................................................................................................................................................ 85
1.15.3 Federal communications commission notice ................................................................................ 85
2 Design-In ..................................................................................................................... 88
2.1 Design-in checklist .............................................................................................................................. 88
2.1.1 Schematic checklist ..................................................................................................................... 88
2.1.2 Layout checklist ........................................................................................................................... 88
2.1.3 Antenna checklist ........................................................................................................................ 89
2.2 Design Guidelines for Layout .............................................................................................................. 90
2.2.1 Layout guidelines per pin function ............................................................................................... 90
2.2.2 Footprint and paste mask ............................................................................................................ 99
2.2.3 Placement ................................................................................................................................. 100
2.3 Thermal aspects ................................................................................................................................ 101
2.4 Antenna guidelines ........................................................................................................................... 102
2.4.1 Antenna termination ................................................................................................................. 103
2.4.2 Antenna radiation ..................................................................................................................... 104
2.4.3 Antenna detection functionality ................................................................................................ 105
2.5 ESD immunity test precautions ......................................................................................................... 108
2.5.1 General precautions .................................................................................................................. 109
2.5.2 Antenna interface precautions ................................................................................................... 110
2.5.3 Module interfaces precautions ................................................................................................... 111
3 Features description ................................................................................................. 112
3.1 Firmware (upgrade) Over AT (FOAT) ................................................................................................. 112
3.2 TCP/IP ............................................................................................................................................... 112
3.2.1 Multiple PDP contexts and sockets............................................................................................. 112
3.3 FTP ................................................................................................................................................... 112
3.4 FTPS ................................................................................................................................................. 112
3.5 HTTP ................................................................................................................................................. 112
3.6 HTTPS ............................................................................................................................................... 112
3.7 AssistNow clients and GPS integration .............................................................................................. 113
3.8 Jamming Detection ........................................................................................................................... 113
3.9 In-Band modem (LISA-U130 only) ..................................................................................................... 113
3.10 Smart Temperature Management ................................................................................................. 113
3.10.1 Smart Temperature Supervisor (STS) .......................................................................................... 114
3.10.2 Threshold Definitions ................................................................................................................. 116
4 Handling and soldering ........................................................................................... 117
4.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 117
4.2 Soldering .......................................................................................................................................... 117
4.2.1 Soldering paste.......................................................................................................................... 117
4.2.2 Reflow soldering ....................................................................................................................... 117
4.2.3 Optical inspection ...................................................................................................................... 119
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4.2.4 Cleaning .................................................................................................................................... 119
4.2.5 Repeated reflow soldering ......................................................................................................... 119
4.2.6 Wave soldering.......................................................................................................................... 119
4.2.7 Hand soldering .......................................................................................................................... 119
4.2.8 Rework ...................................................................................................................................... 119
4.2.9 Conformal coating .................................................................................................................... 119
4.2.10 Casting ...................................................................................................................................... 120
4.2.11 Grounding metal covers ............................................................................................................ 120
4.2.12 Use of ultrasonic processes ........................................................................................................ 120
5 Product Testing......................................................................................................... 121
5.1 u-blox in-series production test ......................................................................................................... 121
5.2 Test parameters for OEM manufacturer ............................................................................................ 121
Appendix ........................................................................................................................ 122
A Glossary .................................................................................................................... 122
Related documents......................................................................................................... 124
Revision history .............................................................................................................. 124
Contact ............................................................................................................................ 125
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3G UMTS/HSDPA/HSUPA Characteristics
2G GSM/GPRS/EDGE Characteristics
Class A User Equipment1
Class B Mobile Station2
UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD)
operating mode
Dual-band support:
Band II (1900 MHz) and Band V (850 MHz) for LISA-U100,
LISA-U120
Band I (2100 MHz) and Band VIII (900 MHz) for LISA-U110,
LISA-U130
Quad-band support
GSM 850 MHz, E-GSM 900 MHz,
DCS 1800 MHz and PCS 1900 MHz
WCDMA/HSDPA/HSUPA
Power Class 3 (24 dBm)
GSM/GPRS
Power Class 4 (33 dBm) for GSM/E-GSM bands
Power Class 1 (30 dBm) for DCS/PCS bands
EDGE
Power Class E2 (27 dBm) for GSM/E-GSM bands
Power Class E2 (26 dBm) for DCS/PCS bands
PS
HSUPA category 6, up to 7.2 Mb/s DL, 5.76 Mb/s UL
HSDPA category 8, up to 7.2 Mb/s DL, 384 kb/s UL
WCDMA data up to 384 kb/s DL/UL
PS
EDGE multislot class 12
3
, coding scheme MCS1-MCS9,
up to 236.8 kb/s
GPRS multislot class 12
3
, coding scheme CS1-CS4, up to
85.6 kb/s
WCDMA CS data up to 64 kb/s DL/UL
CS (Circuit Switched) Data calls are supported in transparent/non
transparent mode up to 9.6 kb/s
1
2
3
1 System description
1.1 Overview
LISA-U1 wireless modules integrate full-feature 3G UMTS/HSxPA and 2G GSM/GPRS/EDGE protocol stack with
Assisted GPS support. These SMT modules come in the compact LISA form factor, featuring Leadless Chip
Carrier (LCC) packaging technology.
Table 1: LISA-U1 UMTS/HSDPA/HSUPA and GSM/GPRS/EDGE characteristics
With GSM/GPRS network operation modes I to III are supported, with user-definable preferred service selectable
from GSM to GPRS. Optionally paging messages for GSM calls can be monitored during GPRS data transfer in
not-coordinating NOM II-III.
LISA-U1 series modules implement GPRS/EGPRS class 12 for data transfer. GPRS class determines the number of
timeslots available for upload and download and thus the speed at which data can be transmitted and received,
with higher classes typically allowing faster data transfer rates. Class 12 implies a maximum of 4 slots in
download (reception) and 4 slots in upload (transmission) with 5 slots in total.
The network automatically configures the number of timeslots used for reception or transmission (voice calls
take precedence over GPRS traffic). The network also automatically configures channel encoding (CS1 to MCS9).
The maximum (E)GPRS bit rate of the mobile station depends on the coding scheme and number of time slots.
Direct Link mode is supported for TCP sockets.
Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active
without any interruption in service.
Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. If for
example during data transmission an incoming call occurs, the data connection is suspended to allow the voice communication. Once the
voice call has terminated, the data service is resumed.
GPRS/EDGE multislot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total. GPRS class
determines the number of timeslots available for upload and download and thus the speed at which data can be transmitted and received,
with higher classes typically allowing faster data transfer rates.
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Wireless
Base-band
Processor
Memory
Power Management Unit
RF
Transceiver
26 MHz
32.768 kHz
SAW
Filter
FEM & 2G PA
ANT
LNA
3G PA
LNA
3G PA
DDC (for GPS)
(U)SIM Card
UART
SPI
USB
GPIO(s)
Power On
External Reset
V_BCKP (RTC)
Vcc (Supply)
V_INT (I/O)
Wireless
Base-band
Processor
Memory
Power Management Unit
RF
Transceiver
26 MHz
32.768 kHz
SAW
Filter
FEM & 2G PA
ANT
LNA
3G PA
LNA
3G PA
DDC (for GPS)
(U)SIM Card
UART
SPI
USB
GPIO(s)
Power On
External Reset
V_BCKP (RTC)
Vcc (Supply)
V_INT (I/O)
Digital Audio (I2S)
AnalogAudio
1.2 Architecture
Figure 1: LISA-U100, LISA-U110 block diagram
Figure 2: LISA-U120, LISA-U130 block diagram
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1.2.1 Functional blocks
LISA-U1 series modules consist of the following internal functional blocks: RF high power front-end, RF
transceiver, Baseband section and Power Management Unit.
RF high-power front-end
A separated shielding box includes the RF high-power signal circuitry, namely:
Front-End Module (FEM) with integrated quad-band 2G Power Amplifier and antenna switch multiplexer
Two single-band 3G HSxPA/WCDMA Power Amplifier modules with integrated duplexers
The RF antenna is directly connected to the FEM, which dispatches the RF signals according to the active mode.
For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied to integrated SAW
filters for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the
allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the 2G power
amplifier module and then directed to the antenna through the FEM. The 3G transmitter and receiver are instead
active at the same time due to frequency-domain duplex operation. The switch integrated in the FEM connects
the antenna port to the passive duplexer which separates the TX and RX signal paths. The duplexer itself
provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the
fixed gain linear power amplifier.
RF Transceiver
In the same shielding box that includes the RF high-power signal circuitry there are all the low-level analog RF
components, namely:
Dual-band HSxPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver
Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO)
Low Noise Amplifier (LNA) and SAW RF filters for 2G and 3G receivers
While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the
baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the
downlink path, the external LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally
improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal
levels before delivering to the analog I/Q to baseband for further digital processing.
For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF
quadrature demodulator are used to provide the same I/Q signals to baseband as well. In transmit mode, the
up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on
the modulation to be transmitted.
In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled
oscillator are used to generate the local oscillator signal.
The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the
baseband as a master reference for clock generation circuits while operating in active mode.
Modulation techniques
Modulation techniques related to the radio technologies this module supports, are listed as follows:
GSM GSMK
GPRS GMSK
EDGE GMSK / 8-PSK
WCDMA QPSK
HSDPA QPSK / 16-QAM
HSUPA QPSK / 16-QAM
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Baseband section and power management unit
Another shielding box includes all the digital circuitry and the power supplies, basically the following functional
blocks:
Wireless baseband processor, a mixed signal ASIC which integrates:
Microprocessor for controller functions, 2G & 3G upper layer software
DSP core for 2G Layer 1 and audio processing
3G coprocessor and HW accelerator for 3G Layer 1 control software and routines
Dedicated HW for peripherals control, as UART, USB, SPI etc
Memory system in a Multi-Chip Package (MCP) integrating two devices:
NOR flash non-volatile memory
DDR SRAM volatile memory
Power Management Unit (PMU), used to derive all the system supply voltages from the module supply VCC
32.768 kHz crystal, connected to the Real Time Clock (RTC) oscillator to provide the clock reference in idle or
power off mode
1.2.2 Hardware differences between LISA-U1 series modules
Hardware differences between the LISA-U1 series modules:
3G Dual-band support:
Band II (1900 MHz) and Band V (850 MHz) are supported by LISA-U100, LISA-U120
Band I (2100 MHz) and Band VIII (900 MHz) are supported by LISA-U110, LISA-U130
3G maximum data rate capabilities:
HSUPA category 6, up to 7.2 Mb/s DL, 5.76 Mb/s UL
HSDPA category 8, up to 7.2 Mb/s DL, 384 kb/s UL
Audio support:
One differential analog audio input, one differential analog audio output and one 4-wire digital audio
interface are supported by LISA-U120 and LISA-U130
No analog audio input, no analog audio output and no digital audio interface are supported by
LISA-U100, LISA-U110
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Function
Pin
No
I/O
Description
Remarks
Power
VCC
61, 62, 63
I
Module Supply
Clean and stable supply is required: low ripple and
low voltage drop must be guaranteed.
Voltage provided has to be always above the
minimum limit of the operating range.
Consider that there are large current spikes in
connected mode, when a GSM call is enabled.
VCC pins are internally connected, but all the
available pads must be connected to the external
supply in order to minimize power loss due to
series resistance.
See section 1.5.2
GND
1, 3, 6, 7,
8, 17, 25,
28, 29, 30,
31, 32, 33,
34, 35, 36,
37, 38, 60,
64, 65, 66,
67, 69, 70,
71, 72, 73,
75, 76
N/A
Ground
GND pins are internally connected but a good
(low impedance) external ground connection can
improve RF performance: all GND pins must be
externally connected to ground.
V_BCKP
2
I/O
Real Time Clock supply
input/output
V_BCKP = 2.3 V (typical) generated by the module
when VCC supply voltage is within valid operating
range.
See section 1.5.4
V_INT
4 O Digital I/O Interfaces
supply output
V_INT = 1.8V (typical) generated by the module
when it is switched-on and the RESET_N (external
reset input pin) is not forced to the low level.
See section 1.5.5
VSIM
50 O SIM supply output
VSIM = 1.80 V typical or 2.90 V typical generated
by the module according to the SIM card type.
See section 1.8
RF
ANT
68
I/O
RF antenna interface
50 nominal impedance.
See section 1.7, section 2.4 and section 2.2.1.1
SIM
SIM_IO
48
I/O
SIM data
Internal 4.7 k pull-up to VSIM.
Must meet SIM specifications.
See section 1.8
SIM_CLK
47 O SIM clock
Must meet SIM specifications.
See section 1.8
SIM_RST
49 O SIM reset
Must meet SIM specifications.
See section 1.8
SPI
SPI_MISO
57 O SPI Data Line.
Master Input,
Slave Output
Module Output: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
See section 1.9.4
SPI_MOSI
56 I SPI Data Line.
Master Output,
Slave Input
Module Input: module runs as an SPI slave.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
Internal active pull-up to V_INT (1.8 V) enabled.
See section 1.9.4
SPI_SCLK
55 I SPI Serial Clock.
Master Output,
Slave Input
Module Input: module runs as an SPI slave.
Idle low (CPOL=0).
Internal active pull-down to GND enabled.
See section 1.9.4
1.3 Pin-out
Table 2 lists the pin-out of the LISA-U1 series modules, with pins grouped by function.
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Function
Pin
No
I/O
Description
Remarks
SPI_SRDY
58 O SPI Slave Ready to
transfer control line.
Master Input,
Slave Output
Module Output: module runs as an SPI slave.
Idle low.
See section 1.9.4
SPI_MRDY
59 I SPI Master Ready to
transfer control line.
Master Output,
Slave Input
Module Input: module runs as an SPI slave.
Idle low.
Internal active pull- down to GND enabled.
See section 1.9.4
DDC
SCL
45 O I2C bus clock line
Fixed open drain. External pull-up required.
See section 1.10
SDA
46
I/O
I2C bus data line
Fixed open drain. External pull-up required.
See section 1.10
UART
RxD
16 O UART received data
Circuit 104 (RxD) in ITU-T V.24.
Provide access to the pin for FW update and
debugging if the USB interface is connected to the
application processor.
See section 1.9.2
TxD
15 I UART transmitted data
Circuit 103 (TxD) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
Provide access to the pin for FW update and
debugging if the USB interface is connected to the
application processor.
See section 1.9.2
CTS
14 O UART clear to send
Circuit 106 (CTS) in ITU-T V.24.
Provide access to the pin for debugging if the USB
interface is connected to the application processor.
See section 1.9.2
RTS
13 I UART ready to send
Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
Provide access to the pin for debugging if the USB
interface is connected to the application processor.
See section 1.9.2
DSR 9 O
UART data set ready
Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.2
RI
10 O UART ring indicator
Circuit 125 (RI) in ITU-T V.24.
See section 1.9.2
DTR
12 I UART data terminal
ready
Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
See section 1.9.2
DCD
11 O UART data carrier detect
Circuit 109 (DCD) in ITU-T V.24.
See section 1.9.2
GPIO
GPIO1
20
I/O
GPIO
See section 1.12
GPIO2
21
I/O
GPIO
See section 1.12
GPIO3
23
I/O
GPIO
See section 1.12
GPIO4
24
I/O
GPIO
See section 1.12
GPIO5
51
I/O
GPIO
See section 1.12
USB
VUSB_DET
18 I USB detect input
Input for VBUS (5 V typical) USB supply sense to
enable USB interface.
Provide access to the pin for FW update and
debugging if the USB interface is not connected to
the application processor.
See section 1.9.3
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Function
Pin
No
I/O
Description
Remarks
USB_D-
26
I/O
USB Data Line D-
90 Ω nominal differential impedance
Pull-up or pull-down resistors and external series
resistors as required by the USB 2.0 high-speed
specification [7] are part of the USB pad driver and
need not be provided externally.
Provide access to the pin for FW update and
debugging if the USB interface is not connected to
the application processor.
See section 1.9.3
USB_D+
27
I/O
USB Data Line D+
90 Ω nominal differential impedance
Pull-up or pull-down resistors and external series
resistors as required by the USB 2.0 high-speed
specification [7] are part of the USB pad driver and
need not be provided externally.
Provide access to the pin for FW update and
debugging if the USB interface is not connected to
the application processor.
See section 1.9.3
System
PWR_ON
19 I Power-on input
PWR_ON pin has high input impedance.
Do not keep floating in noisy environment:
external pull-up required.
See section 1.6.1
RESET_N
22 I External reset input
Internal 10 kΩ pull-up to V_BCKP (2.3 V).
See section 1.6.3
Audio
(LISA-U120,
LISA-U130
versions only)
I2S_CLK
43 O I2S clock
Check device specifications to ensure compatibility
to module supported modes.
See section 1.11.2.
I2S_RXD
44 I I2S receive data
Internal active pull-up to V_INT (1.8 V) enabled.
Check device specifications to ensure compatibility
to module supported modes.
See section 1.11.2.
I2S_TXD
42 O I2S transmit data
Check device specifications to ensure compatibility
to module supported modes.
See section 1.11.2.
I2S_WA
41 O I2S word alignment
Check device specifications to ensure compatibility
to module supported modes.
See section 1.11.2.
MIC_N
39 I Differential analog
audio input (negative)
Differential analog input shared for all analog path
modes: handset, headset, hands-free mode.
Internal DC blocking capacitor.
See section 1.11.1
MIC_P
40 I Differential analog
audio input (positive)
Differential analog input shared for all analog path
modes: handset, headset, hands-free mode.
Internal DC blocking capacitor.
See section 1.11.1
SPK_P
53 O Differential analog
audio output (positive)
Differential analog audio output shared for all
analog path modes: earpiece, headset and
loudspeaker mode.
See section 1.11.1
SPK_N
54 O Differential analog
audio output (negative)
Differential analog audio output shared for all
analog path modes: earpiece, headset and
loudspeaker mode.
See section 1.11.1
Reserved
RSVD
5
N/A
RESERVED pin
This pin must be connected to ground
See section 1.13
RSVD
52
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
74
N/A
RESERVED pin
Do not connect
See section 1.13
3G.G2-HW-10002-3 Preliminary System description
Page 13 of 125
LISA-U1 series - System Integration Manual
Function
Pin
No
I/O
Description
Remarks
Reserved
(LISA-U100,
LISA-U110
versions only)
RSVD
43
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
44
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
42
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
41
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
39
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
40
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
53
N/A
RESERVED pin
Do not connect
See section 1.13
RSVD
54
N/A
RESERVED pin
Do not connect
See section 1.13
Table 2: LISA-U1 series modules pin-out
3G.G2-HW-10002-3 Preliminary System description
Page 14 of 125
LISA-U1 series - System Integration Manual
Operating Mode
Description
Features / Remarks
Transition condition
General Status: Power-down
Not-Powered
Mode
VCC supply not present or
below operating range.
Microprocessor switched off
(not operating).
RTC only operates if supplied
through V_BCKP pin.
Module is switched off.
Application interfaces are not
accessible.
Internal RTC timer operates only if a
valid voltage is applied to V_BCKP pin.
Module cannot be switched on by a
falling edge provided on the PWR_ON
input, or by a preset RTC alarm or by a
rising edge provided on the RESET_N
input.
Module can be switched on applying
VCC supply.
Power-Off Mode
VCC supply within operating
range.
Microprocessor switched off
(not operating).
Only RTC runs.
Module is switched off: normal
shutdown after sending the
AT+CPWROFF command (refer to
u-blox AT Commands Manual [2]).
Application interfaces are not
accessible.
Only the internal RTC timer in
operation.
Module can be switched on by a falling
edge on the PWR_ON input, or by a
rising edge on the RESET_N input, or by
a preset RTC alarm.
General Status: Normal Operation
Idle-Mode
Microprocessor runs with
32 kHz as reference oscillator.
Module does not accept data
signals from an external
device.
If power saving is enabled, the module
automatically enters idle mode whenever
possible.
Application interfaces are disabled.
If hardware flow control is enabled, the
CTS line to ON state indicates that the
module is in active mode and the UART
interface is enabled: the line is driven in
the OFF state when the module is not
prepared to accept data by the UART
interface.
If hardware flow control is disabled, the
CTS line is fixed to ON state.
Module by default is not set to
automatically enter idle mode whenever
possible, unless power saving
configuration is enabled by appropriate
AT command (refer to u-blox AT
Commands Manual [2], AT+UPSV).
Module enters automatically idle mode
when power saving is enabled and there
is no activity for the defined time
interval:
Module registered with the
network and power saving
enabled. Periodically wakes up to
active mode to monitor the paging
channel for the paging block
reception according to network
indication
Module not registered with the
network and power saving is
enabled. Periodically wakes up to
monitor external activity
Module wakes up from idle-mode to
active-mode in the following events:
Incoming voice or data call
RTC alarm occurs
Data received on UART interface
(refer to 1.9.2)
RTS input line set to the ON state
by the DTE if the AT+UPSV=2
command is sent to the module
(refer to 1.9.2)
USB detection, applying 5 V (typ.)
to the VUSB_DET pin
The connected USB host forces a
remote wakeup of the module as
USB device (refer to 1.9.3)
The connected SPI master indicates
to the module that it is ready for
transmission or reception, by the
IPC SPI_MRDY signal (refer to
1.9.4)
1.4 Operating modes
LISA-U1 series modules have several operating modes. Table 3 summarizes the various operating modes and
provides general guidelines for operation.
3G.G2-HW-10002-3 Preliminary System description
Page 15 of 125
LISA-U1 series - System Integration Manual
Operating Mode
Description
Features / Remarks
Transition condition
Active-Mode
Microprocessor runs with
26 MHz as reference
oscillator.
The module is prepared to
accept data signals from an
external device.
Module is switched on and is fully active.
The application interfaces are enabled,
unless power saving configuration is
enabled by the AT+UPSV command
(refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2
and u-blox AT Commands Manual [2]).
Power saving is not enabled by default: it
can be enabled by the AT+UPSV
command (see u-blox AT Commands
Manual [2])
If power saving is enabled, the module
automatically enters idle mode and
application interfaces are disabled
whenever possible (refer to sections
1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT
Commands Manual [2], AT+UPSV).
Connected-Mode
Voice or data call enabled.
Microprocessor runs with
26 MHz as reference
oscillator.
The module is prepared to
accept data signals from an
external device.
The module is switched on and a voice
call or a data call (2G/3G) is in progress.
Module is fully active.
The application interfaces are enabled,
unless power saving configuration is
enabled by the AT+UPSV command (see
section 1.9.2.3, 1.9.3.2, 1.9.4.2 and the
u-blox AT Commands Manual [2]).
When call terminates, the module
returns to the active operating mode.
Switch ON:
•Apply VCC
If power saving is enabled
and there is no activity for
a defined time interval
Any wake up event described
in the module operating
modes summary table above
AT+CPWROFF
(no HW pin)
Incoming/outgoing call or
other dedicated device
network communication
Call terminated,
communication dropped
Remove VCC
Switch ON:
•PWR_ON
•RESET_N
•RTC Alarm
Not
powered
Power off
ActiveConnected Idle
Table 3: Module operating modes summary
Transition between the different modes is described in Figure 3.
Figure 3: Operating modes transition
3G.G2-HW-10002-3 Preliminary System description
Page 16 of 125
LISA-U1 series - System Integration Manual
Baseband Processor
2G Power Amplifier
Switching
Step-Down
LISA-U1 series
5 x 10 µF
61
VCC
62
VCC
63
VCC
50
VSIM
2
V_BCKP
4
V_INT
2 x 3G Power Amplifier(s)
Linear
LDO
Linear
LDO
Switching
Step-Down
Linear
LDO
Linear
LDO
Linear
LDO
I/O
EBU
CORE
Analog
SIM
RTC
NOR Flash
DDR SRAM
RF Transceiver
Memory
Power Management Unit
22 µF 10 µF 220 nF
1.5 Power management
1.5.1 Power supply circuit overview
LISA-U1 series modules feature a power management concept optimized for the most efficient use of supplied
power. This is achieved by hardware design utilizing a power efficient circuit topology (Figure 4), and by power
management software controlling the module’s power saving mode.
Figure 4: Power management simplified block diagram
Pins with supply function are reported in Table 4, Table 8 and Table 10.
LISA-U1 series modules must be supplied via the VCC pins. There is only one main power supply input, available
on the three VCC pins that must be all connected to the external power supply
The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit
(PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by
integrated voltage regulators.
3G.G2-HW-10002-3 Preliminary System description
Page 17 of 125
LISA-U1 series - System Integration Manual
Name
Description
Remarks
VCC
Module power supply input
VCC pins are internally connected, but all the available pads
must be connected to the external supply in order to
minimize the power loss due to series resistance.
Clean and stable supply is required: low ripple and low
voltage drop must be guaranteed.
Voltage provided must always be above the minimum limit of
the operating range.
Consider that during a GSM call there are large current spikes
in connected mode.
GND
Ground
GND pins are internally connected but a good (low
impedance) external ground can improve RF performance: all
available pads must be connected to ground.
V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the
internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If
the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time
Clock can be externally supplied via the V_BCKP pin (see section 1.5.4).
When a 1.8 V or a 3 V SIM card type is connected, LISA-U1 series modules automatically supply the SIM card via
the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is
implemented, in accordance to the ISO-IEC 7816-3 specifications.
The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to
allow more economical and efficient integration of the LISA-U1 series modules in the final application.
The integrated Power Management Unit also provides the control state machine for system start up and system
reset control.
1.5.2 Module supply (VCC)
The LISA-U1 series modules must be supplied through the VCC pins by a DC power supply. Voltages must be
stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to
surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system
power supply circuit is able to support peak power (refer to LISA-U1 series Data Sheet [1] for specification).
Table 4: Module supply pins
VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level can be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin.
The voltage provided to the VCC pins must be within the normal operating range limits as specified in the
LISA-U1 series Data Sheet [1]. Complete functionality of the module is only guaranteed within the specified
minimum and maximum VCC voltage operating range.
Ensure that the input voltage at the VCC pins never drops below the minimum limit of the operating
range when the module is switched on. This is the case even during a GSM transmit burst, where the
current consumption can rise up to minimum peaks of 2.5 A in case of a mismatched antenna load.
Operation above the operating range maximum limit is not recommended and extended
exposure beyond it may affect device reliability.
3G.G2-HW-10002-3 Preliminary System description
Page 18 of 125
LISA-U1 series - System Integration Manual
Time
undershoot
overshoot
ripple
ripple
drop
Voltage
3.8 V
(typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
Stress beyond the VCC absolute maximum ratings can cause permanent damage to the
module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted
to values within the specified limits by using appropriate protection.
When designing the power supply for the application, pay specific attention to power losses and
transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the
following characteristics:
Voltage drop during transmit slots must be lower than 400 mV
No undershoot or overshoot at the start and at the end of transmit slots
Voltage ripple during transmit slots must be minimized:
lower than 70 mVpp if f
lower than 10 mVpp if 200 kHz < f
lower than 2 mVpp if f
≤ 200 kHz
ripple
> 400 kHz
ripple
≤ 400 kHz
ripple
Figure 5: Description of the VCC voltage profile versus time during a GSM call
Any degradation in power supply performance (due to losses, noise or transients) will directly affect the
RF performance of the module since the single external DC power source indirectly supplies all the
digital and analog interfaces, and also directly supplies the RF power amplifier (PA).
The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms. This VCC slope allows a proper
switch on of the module, that is switched on when the voltage rises to the VCC operating range starting
from a voltage value lower than 2.25 V.
1.5.2.1 VCC application circuits
LISA-U1 series modules must be supplied through the VCC pins by one (and only one) proper DC power supply
that must be one of the following:
Switching regulator
Low Drop-Out (LDO) linear regulator
Rechargeable Li-Ion battery
Primary (disposable) battery
3G.G2-HW-10002-3 Preliminary System description
Page 19 of 125
LISA-U1 series - System Integration Manual
Main Supply
Available?
Battery
Li-Ion 3.7 V
Linear LDO
Regulator
Main Supply
Voltage
>5 V?
Switching
Step-Down
Regulator
No, portable device
No, less than 5 V
Yes, greater than 5 V
Yes, always available
Figure 6: VCC supply concept selection
The switching step-down regulator is the typical choice when the available primary supply source has a nominal
voltage much higher (e.g. greater than 5 V) than the LISA-U1 series modules operating supply voltage. The use
of switching step-down provides the best power efficiency for the overall application and minimizes current
drawn from the main supply source.
The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g.
less than 5 V). In this case the typical 90% efficiency of the switching regulator will diminish the benefit of
voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear
regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of
energy in thermal power.
If LISA-U1 series modules are deployed in a mobile unit where no permanent primary supply source is available,
then a battery will be required to provide VCC. A standard 3-cell Lithium-Ion battery pack directly connected to
VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically
reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided.
The use of primary (not rechargeable) battery is uncommon, since the most cells available are seldom capable of
delivering the burst peak current for a GSM call due to high internal resistance.
Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in
LISA-U1 series modules). The charger circuit should be designed in order to prevent over-voltage on VCC beyond
the upper limit of the absolute maximum rating.
The following sections highlight some design aspects for each of the supplies listed above.
Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements:
Power capability: the switching regulator with its output circuit must be capable of providing a voltage
Low output ripple: the switching regulator together with its output circuit must be capable of providing a
High switching frequency: for best performance and for smaller applications select a switching frequency
3G.G2-HW-10002-3 Preliminary System description
Page 20 of 125
value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current
pulses with 1/8 duty cycle to the VCC pins
clean (low noise) VCC voltage profile
≥ 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching
regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be
carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact
GSM modulation spectrum performance. An additional L-C low-pass filter between the switching regulator
LISA-U1 series - System Integration Manual
LISA-U1 series
12V
C6
R3
C5
R2
C3C2
C1
R1
VIN
RUN
VC
RT
PG
SYNC
BD
BOOST
SW
FB
GND
6
7
10
9
5
C7
1
2
3
8
11
4
C8 C9
L2
D1
R4
R5
L1
C4
U1
62
VCC
63
VCC
61
VCC
GND
output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive
losses on series inductors
PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in
active mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to
reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM
mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the
GSM module changes status from idle mode (current consumption approximately 1 mA) to active mode
(current consumption approximately 100 mA): it is permissible to use a regulator that switches from the
PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA)
Output voltage slope: the use of the soft start function provided by some voltage regulator must be
carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a
proper switch-on of the module
Figure 7 and the components listed in Table 5 show an example of a high reliability power supply circuit, where
the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with
low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a
switching regulator is suggested when the difference from the available supply rail to the VCC value is high:
switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC
supply.
Figure 7: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator
3G.G2-HW-10002-3 Preliminary System description
Page 21 of 125
LISA-U1 series - System Integration Manual
Reference
Description
Part Number - Manufacturer
C1
47 µF Capacitor Aluminum 0810 50 V
MAL215371479E3 - Vishay
C2
10 µF Capacitor Ceramic X7R 5750 15% 50 V
C5750X7R1H106MB - TDK
C3
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C4
680 pF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71H681KA01 - Murata
C5
22 pF Capacitor Ceramic COG 0402 5% 25 V
GRM1555C1H220JZ01 - Murata
C6
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C7
470 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E474KA12 - Murata
C8
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 - Murata
C37
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 mΩ
T520D337M006ATE045 - KEMET
D1
Schottky Diode 40 V 3 A
MBRA340T3G - ON Semiconductor
L1
10 µH Inductor 744066100 30% 3.6 A
744066100 - Wurth Electronics
L2
1 µH Inductor 7445601 20% 8.6 A
7445601 - Wurth Electronics
R1
470 kΩ Resistor 0402 5% 0.1 W
2322-705-87474-L - Yageo
R2
15 kΩ Resistor 0402 5% 0.1 W
2322-705-87153-L - Yageo
R3
22 kΩ Resistor 0402 5% 0.1 W
2322-705-87223-L - Yageo
R4
390 kΩ Resistor 0402 1% 0.063 W
RC0402FR-07390KL - Yageo
R5
100 kΩ Resistor 0402 5% 0.1 W
2322-705-70104-L - Yageo
U1
Step Down Regulator MSOP10 3.5 A 2.4 MHz
LT3972IMSE#PBF - Linear Technology
Table 5: Suggested components for the VCC voltage supply application circuit using a step-down regulator
Low Drop-Out (LDO) linear regulator
The characteristics of the LDO linear regulator connected to the VCC pins should meet the following
requirements:
Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper
voltage value to the VCC pins and of delivering 2.5 A current pulses with 1/8 duty cycle
Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its
junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input
voltage to the min output voltage to evaluate the power dissipation of the regulator)
Output voltage slope: the use of the soft start function provided by some voltage regulators must be
carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a
proper switch-on of the module
Figure 8 and the components listed in Table 6 show an example of a power supply circuit, where the VCC
module supply is provided by an LDO linear regulator capable of delivering 2.5 A current pulses, with proper
power handling capability. The use of a linear regulator is suggested when the difference from the available
supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to
the 3.8 V typical value of the VCC supply.
3G.G2-HW-10002-3 Preliminary System description
Page 22 of 125
LISA-U1 series - System Integration Manual
5V
C1 R1
IN OUT
ADJ
GND
1
2
4
5
3
C2R2
R3
U1
SHDN
LISA-U1 series
62
VCC
63
VCC
61
VCC
GND
Reference
Description
Part Number - Manufacturer
C1
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
C2
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
R1
47 kΩ Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
R2
4.7 kΩ Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
R3
2.2 kΩ Resistor 0402 5% 0.1 W
RC0402JR-072K2L - Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LT1764AEQ#PBF - Linear Technology
Figure 8: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator
Table 6: Suggested components for VCC voltage supply application circuit using an LDO linear regulator
Rechargeable Li-Ion battery Rechargeable Li-Ion batteries connected to the VCC pins should meet the following requirements:
Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be
capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of
delivering a DC current greater than the module maximum average current consumption to VCC pins. The
maximum pulse discharge current and the maximum DC discharge current are not always reported in
battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity
in Amp-hours divided by 1 hour
DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a
VCC voltage drop greater than 400 mV during transmit bursts
Primary (disposable) battery
The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following
requirements:
Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be
capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of
delivering a DC current greater than the module maximum average current consumption at the VCC pins.
The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets,
but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours
divided by 1 hour
DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a
VCC voltage drop greater than 400 mV during transmit bursts
3G.G2-HW-10002-3 Preliminary System description
Page 23 of 125
LISA-U1 series - System Integration Manual
3V8
C1 C4
GND
C3C2
C5
LISA-U1 series
62
VCC
63
VCC
61
VCC
+
Reference
Description
Part Number - Manufacturer
C1
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 mΩ
T520D337M006ATE045 - KEMET
C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C3
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C4
39 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E390JA01 - Murata
C5
10 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E100JA01 - Murata
Additional recommendations for the VCC supply application circuits
To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines
(connected to the VCC and GND pins of the module) on the application board and battery pack should also be
considered and minimized: cabling and routing must be as short as possible in order to minimize power losses.
Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. Even if all the
VCC pins and all the GND pins are internally connected within the module, it is recommended to properly
connect all of them to supply the module in order to minimize series resistance losses.
To avoid undershoot and overshoot on voltage drops at the start and end of a transmit burst during a GSM call
(when current consumption on the VCC supply can rise up to 2.5 A in the worst case), place a 330 µF low ESR
capacitor (e.g. KEMET T520D337M006ATE045) near the VCC pins.
The use of very large capacitors (i.e. greater then 1000 µF) on the VCC line and the use of the soft start function
provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp
from 2.5 V to 3.2 V within 1 ms to allow a proper switch on of the module.
To reduce voltage ripple and noise, place the following near the VCC pins:
100 nF capacitor (e.g Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources
10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources
10 pF capacitor (e.g. Murata GRM1555C1E100J) to filter EMI in the 1800 / 1900 / 2100 MHz bands
39 pF capacitor (e.g. Murata GRM1555C1E390J) to filter EMI in the 850 / 900 MHz bands
Figure 9 shows the complete configuration but the mounting of each single component depends on the
application design.
Figure 9: Suggested schematic design to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops
Table 7: Suggested components to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops
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Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
~125 mA
2500 mA
Peak current
depends on
TX power
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
2.5
2.0
~125 mA
~25 mA
1.5.3 Current consumption profiles
During operation, the current drawn by the LISA-U1 series modules through the VCC pins can vary by several
orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at
maximum power level in 2G connected mode, to continuous high current drawn in UMTS connected mode, to
the low current consumption during power saving in idle mode.
1.5.3.1 2G connected mode
When a GSM call is established, the VCC consumption is determined by the current consumption profile typical
of the GSM transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which
is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM
900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit
slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 µs
(width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8
duty cycle according to GSM TDMA (Time Division Multiple Access).
During a GSM call, current consumption is in the order of 100-200 mA in receiving or in monitor bursts and is
about 30-50 mA in the inactive unused bursts (low current period). The more relevant contribution to determine
the average current consumption is set by the transmitted power in the transmit slot.
An example of current consumption profile of the data module in GSM talk mode is shown in Figure 10.
Figure 10: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot), with VCC=3.8 V
When a GPRS connection is established there is a different VCC current consumption profile also determined by
the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot
can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on
network conditions, which set the peak current consumption, but following the GPRS specifications the
maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak o f
current consumption is not as high as can be in case of a GSM call.
If the module transmits in GPRS class 12 connected mode in the GSM 850 or in the E-GSM 900 band at the
maximum power control level (27 dBm typical transmitted power in the transmit slot/burst), the current
consumption can reach up to 1400 mA (with unmatched antenna). This happens for 2.307 ms (width of the 4
transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle,
according to GSM TDMA.
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Time [ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200mA
~125mA
Peak current
depends on
TX power
~125mA
GSM frame
4.615 ms
(1 frame = 8 slots)
1.5
1.0
0.5
0.0
2.5
2.0
~25mA
1600 mA
Figure 11 reports the current consumption profiles in GPRS mode with 4 slots used to transmit.
Figure 11: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot), with VCC=3.8 V
In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so
the image shown in Figure 11 is valid for EDGE as well.
1.5.3.2 3G connected mode
During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex
(FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption
depends again on output RF power, which is always regulated by network commands. These power control
commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a maximum rate
of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are
continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in
the 2G case. In the worst scenario, corresponding to a continuous transmission and reception at maximum
output power (approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the
order of continuous 600-700 mA. Even at lowest output RF power (approximately 0.01 µW or -50 dBm), the
current still remains in the order of 200 mA due to module baseband processing and transceiver activity.
An example of current consumption profile of the data module in UMTS continuous transmission mode is shown
in Figure 12.
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Time
[ms]
3G frame
10 ms
(1 frame = 15 slots)
Current [mA]
170 mA
Depends
on TX
power
1 slot
666 µs
670 mA
300
200
100
0
500
400
600
700
Figure 12: VCC current consumption profile versus time during a UMTS connection, with VCC=3.8 V
When a packet data connection is established, the actual current profile depends on the amount of transmitted
packets; there might be some periods of inactivity between allocated slots where current consumption drops
about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher
quality signal required by the network to cope with enhanced data speed.
1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled)
The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command
(refer to u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module
automatically enters idle-mode whenever possible.
When power saving is enabled, the module is registered or attached to a network and a voice or data call is not
enabled, the module automatically enters idle-mode whenever possible, but it must periodically monitor the
paging channel of the current base station (paging block reception), in accordance to GSM system requirements.
When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging
block. In between, the module switches to idle-mode. This is known as GSM discontinuous reception (DRX).
The module processor core is activated during the paging block reception, and automatically switches its
reference clock frequency from 32 kHz to the 26 MHz used in active-mode.
The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging
period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell.
In case of 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX = 2,
i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX = 9, i.e.
width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms).
In case of 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of
26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms =
5120 ms).
An example of a module current consumption profile is shown in Figure 13: the module is registered with the
network (2G or 3G), automatically enters idle mode and periodically wakes up to active mode to monitor the
paging channel for paging block reception.
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~30 ms
IDLE MODE ACTIVE MODE IDLE MODE
500-700 µA
Active Mode
Enabled
Idle Mode
Enabled
500-700 µA
2G case: ~125 mA
3G case: ~85 mA
2G case: 0.44-2.09 s
3G case: 0.61-5.09 s
IDLE MODE
2G or 3G case: ~30 ms
ACTIVE MODE
Time [s]
Current [mA]
150
100
50
0
Time [ms]
Current [mA]
150
100
50
0
5-10 mA
20-25 mA
2G case: ~125 mA
3G case: ~85 mA
PLL
Enabled
RX
Enabled
35-40 mA
DSP
Enabled
Figure 13: Description of VCC current consumption profile versus time when the module is registered with 2G or 3G networks:
the module is in idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception
1.5.3.4 2G and 3G fixed active mode (power saving disabled)
Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (refer
to u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module doesn’t
automatically enter idle-mode whenever possible: the module remains in active mode.
The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used.
An example of the current consumption profile of the data module when power saving is disabled is shown in
Figure 14: the module is registered with the network, active-mode is maintained, and the receiver and the DSP
are periodically activated to monitor the paging channel for paging block reception.
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ACTIVE MODE
20-25 mA
20-25 mA
2G case: 0.47-2.12 s
3G case: 0.64-5.12 s
Paging period
Time [s]
Current [mA]
150
100
50
0
Time [ms]
Current [mA]
150
100
50
0
20-25 mA
RX
Enabled
DSP
Enabled
35-40 mA
2G case: ~125 mA
3G case: ~110 mA
2G case: ~125 mA
3G case: ~110 mA
Name
Description
Remarks
V_BCKP
Real Time Clock supply
V_BCKP = 2.3 V (typical) generated by the module to supply
Real Time Clock when VCC supply voltage is within valid
operating range.
Figure 14: Description of the VCC current consumption profile versus time when power saving is disabled: active-mode is
always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception
1.5.4 RTC Supply (V_BCKP)
The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power On / Reset internal logic. This
supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The
output of this linear regulator is always enabled when the main voltage supply provided to the module through
VCC is within the valid operating range, with the module switched-off or powered-on.
Table 8: Real Time Clock supply pin
The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin.
The RTC provides the time reference (date and time) of the module, also in power off mode, when the V_BCKP
voltage is within its valid range (specified in u-blox LISA-U1 series Data Sheet [1]). The RTC timing is normally
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LISA-U1 series
C1
(a)
2
V_BCKP
R2
LISA-U1 series
C2
(superCap)
(b)
2
V_BCKP
D3
LISA-U1 series
2.3 V
(c)
2
V_BCKP
used to set the wake-up interval during idle-mode periods between network paging, but is able to provide
programmable alarm functions by means of the internal 32.768 kHz clock.
The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply
is not provided to the module through VCC. This lets the time reference (date and time) run even when the main
supply is not provided to the module. Consider that the module cannot switch on if a valid voltage is not present
on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch-on the
module).
The RTC has very low power consumption, but is highly temperature dependent. For example at 25°C and a
V_BCKP voltage of 2.3 V the power consumption is approximately 2 µA, whereas at 70°C and an equal voltage
the power consumption increases to 5-10 µA.
The internal regulator for V_BCKP is optimized for low leakage current and very light loads. It is not
recommended to use V_BCKP to supply external loads.
If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied
from the 10 µF capacitor mounted inside the module. However, this capacitor is not able to provide a long
buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). At this
time the internal RTC will stop counting and the date and time setting will be lost. This has no impact on
wireless connectivity, as all the functionalities of the module do not rely on the date and time setting.
Leave V_BCKP unconnected if the RTC is not required when the VCC supply is removed. The date and
time will not be updated when VCC is disconnected. If VCC is always supplied, then the internal
regulator is supplied from the main supply and there is no need for an external component on V_BCKP.
If RTC is required to run for a time interval of T [s] at 25°C when VCC supply is removed, place a capacitor with a
nominal capacitance of C [µF] at the V_BCKP pin. Choose the capacitor using the following formula:
C [µF] = (Current_Consumption [µA] x T [s]) / Voltage_Drop [V] = 1.538 x T [s]
The RTC current consumption is approximately 2 µA at 25°C, and the voltage drop is equal to 1.3 V (from the
V_BCKP typical value of 2.3 V to the valid range minimum limit of 1.0 V).
For example, a 100 µF capacitor (such as the Murata GRM43SR60J107M) can be placed at V_BCKP to provide a
long buffering time. This capacitor will hold V_BCKP voltage within its valid range for around 50 s at 25°C, after
the VCC supply is removed. If a very long buffering time is required, a 70 mF super-capacitor (e.g. Seiko
Instruments XH414H-IV01E) can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage
within its valid range for approximately 10 hours at 25°C, after the VCC supply is removed. The purpose of the
series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a
fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors will
allow the time reference to run during battery disconnection.
Figure 15: Real time clock supply (V_BCKP) application circuits : (a) using a 100 µF capacitor to let the RTC run for ~50 s at 25°C;
(b) using a 70 mF capacitor to let the RTC run for ~10 hours at 25°C when the VCC supply is removed; (c) using non-rechargeable
battery
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