UBX-16010573 - R21
C1-Public www.u-blox.com
LARA-R2 series
Size-optimized LTE Cat 1 modules in single and multimode configurations
System integration manual
Abstract
This document describes the features and the system integration of LARA-R2 series multi-mode
cellular modules. These modules are a complete, cost efficient and performance optimized LTE
Cat 1 / 3G / 2G multi-mode solution covering up to 5 LTE bands, up to 2 UMTS/HSPA bands and up
to 2 GSM/EGPRS bands in the very small and compact LARA form factor.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Document information Page 2 of 163
C1-Public
Document information
Title
LARA-R2 series
Subtitle
Size-optimized LTE Cat 1 modules in single and multi-mode configurations
Document type
System integration manual
Document number
UBX-16010573
Revision and date
R21
30-Mar-2021
Disclosure restriction
C1-Public
Product status
Corresponding content status
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development /
Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production /
End of life
Production information
Document contains the final product specification.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Document information Page 3 of 163
C1-Public
This document applies to the following products:
Product name
Type number
Modem version
Application version
PCN reference
Product status
LARA-R202
LARA-R202-02B-00
30.42
A01.00
UBX-17057959
Obsolete
LARA-R202-02B-01
30.42
A01.01
UBX-18018067
Obsolete
LARA-R202-02B-02
30.42
A01.02
UBX-18057549
Obsolete
LARA-R202-02B-03
30.44
A01.02
UBX-19011731
Mass production
LARA-R202-82B-00
30.53
A01.03
UBX-19043497
Mass production
LARA-R202-03B-00
30.55
A01.00
UBX-20027523
Mass production
LARA-R203
LARA-R203-02B-00
30.39
A01.00
UBX-17048311
Obsolete
LARA-R203-02B-01
30.39
A01.02
UBX-18018067
Obsolete
LARA-R203-02B-02
30.39
A01.03
UBX-18057549
Obsolete
LARA-R203-02B-03
30.41
A01.03
UBX-19011731
Mass production
LARA-R203-02B-34
30.54
A01.00
UBX-19056532
Mass production
LARA-R203-03B-00
30.55
A01.00
UBX-20027523
Mass production
LARA-R204
LARA-R204-02B-00
31.34
A01.00
UBX-17012269
Obsolete
LARA-R204-02B-01
31.35
A01.03
UBX-18013471
Obsolete
LARA-R204-02B-02
31.40
A01.00
UBX-18046834
Mass production
LARA-R211
LARA-R211-02B-00
30.31
A01.00
UBX-17012270
Obsolete
LARA-R211-02B-01
30.49
A01.01
UBX-17054295
Obsolete
LARA-R211-02B-02
30.49
A01.02
UBX-18057549
End of life
LARA-R211-02B-03
30.49
A01.05
UBX-20012865
Mass production
LARA-R220
LARA-R220-62B-00
30.44
A01.03
UBX-17061668
Obsolete
LARA-R220-62B-01
30.44
A01.04
UBX-18050698
Obsolete
LARA-R220-62B-02
30.44
A01.05
UBX-18057549
Obsolete
LARA-R220-62B-03
30.44
A01.07
UBX-19029271
Mass production
LARA-R280
LARA-R280-02B-00
30.43
A01.01
UBX-17063950
Obsolete
LARA-R280-02B-01
30.43
A01.02
UBX-18018067
Obsolete
LARA-R280-02B-02
30.43
A01.03
UBX-18052020
Obsolete
LARA-R280-02B-03
30.43
A01.04
UBX-18057549
End of life
LARA-R280-02B-04
30.43
A01.06
UBX-19029271
Mass production
LARA-R281
LARA-R281-02B-00
30.49
A01.06
UBX-20035136
Mass production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document.
Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the
express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents,
visit www.u-blox.com.
Copyright © u-blox AG.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Contents Page 4 of 163
C1-Public
Contents
Document information ................................................................................................................................ 2
Contents .......................................................................................................................................................... 4
1 System description ............................................................................................................................... 8
1.1 Overview ........................................................................................................................................................ 8
1.2 Architecture ...............................................................................................................................................11
1.3 Pin-out .........................................................................................................................................................12
1.4 Operating modes .......................................................................................................................................17
1.5 Supply interfaces ......................................................................................................................................19
1.5.1 Module supply input (VCC) .........................................................................................................19
1.5.2 RTC supply input/output (V_BCKP) ..........................................................................................27
1.5.3 Generic digital interfaces supply output (V_INT) ...................................................................28
1.6 System function interfaces ....................................................................................................................29
1.6.1 Module power-on ...........................................................................................................................29
1.6.2 Module power-off ..........................................................................................................................31
1.6.3 Module reset ..................................................................................................................................34
1.6.4 Module / host configuration selection ......................................................................................34
1.7 Antenna interface .....................................................................................................................................35
1.7.1 Antenna RF interfaces (ANT1 / ANT2) .....................................................................................35
1.7.2 Antenna detection interface (ANT_DET) .................................................................................37
1.8 SIM interface ..............................................................................................................................................37
1.8.1 SIM card interface ........................................................................................................................37
1.8.2 SIM card detection interface (SIM_DET) .................................................................................37
1.9 Data communication interfaces ............................................................................................................38
1.9.1 Main UART interface ....................................................................................................................38
1.9.2 Auxiliary UART interface .............................................................................................................50
1.9.3 USB interface .................................................................................................................................51
1.9.4 HSIC interface................................................................................................................................54
1.9.5 DDC (I2C) interface .......................................................................................................................54
1.9.6 SDIO interface ...............................................................................................................................56
1.10 Audio interface ..........................................................................................................................................57
1.10.1 Digital audio interface ..................................................................................................................57
1.11 Clock output ...............................................................................................................................................58
1.12 General Purpose Input/Output (GPIO) ..................................................................................................58
1.13 Reserved pins (RSVD) ..............................................................................................................................58
1.14 System features ........................................................................................................................................59
1.14.1 Network indication ........................................................................................................................59
1.14.2 Antenna detection ........................................................................................................................59
1.14.3 Dual stack IPv4/IPv6 .....................................................................................................................59
1.14.4 PPP ...................................................................................................................................................59
1.14.5 TCP/IP and UDP/IP ........................................................................................................................59
LARA-R2 series - System integration manual
UBX-16010573 - R21 Contents Page 5 of 163
C1-Public
1.14.6 FTP ...................................................................................................................................................59
1.14.7 HTTP ................................................................................................................................................60
1.14.8 SSL/TLS ..........................................................................................................................................60
1.14.9 Bearer Independent Protocol ......................................................................................................62
1.14.10 AssistNow clients and GNSS integration ................................................................................62
1.14.11 Hybrid positioning and CellLocate® ...........................................................................................62
1.14.12 Wi-Fi integration ...........................................................................................................................65
1.14.13 Firmware upgrade Over AT (FOAT) ...........................................................................................65
1.14.14 Firmware update Over The Air (FOTA) .....................................................................................65
1.14.15 Smart temperature management ............................................................................................66
1.14.16 Power saving ..................................................................................................................................68
2 Design-in ................................................................................................................................................ 69
2.1 Overview ......................................................................................................................................................69
2.2 Supply interfaces ......................................................................................................................................70
2.2.1 Module supply (VCC) ....................................................................................................................70
2.2.2 RTC supply (V_BCKP) ...................................................................................................................84
2.2.3 Interface supply (V_INT) ..............................................................................................................85
2.3 System functions interfaces ..................................................................................................................87
2.3.1 Module power-on (PWR_ON) ......................................................................................................87
2.3.2 Module reset (RESET_N) .............................................................................................................88
2.3.3 Module / host configuration selection ......................................................................................89
2.4 Antenna interface .....................................................................................................................................90
2.4.1 Antenna RF interface (ANT1 / ANT2) .......................................................................................90
2.4.2 Antenna detection interface (ANT_DET) .................................................................................98
2.5 SIM interface ........................................................................................................................................... 100
2.6 Data communication interfaces ......................................................................................................... 106
2.6.1 Main UART interface ................................................................................................................. 106
2.6.2 Auxiliary UART interface .......................................................................................................... 111
2.6.3 USB interface .............................................................................................................................. 112
2.6.4 HSIC interface............................................................................................................................. 114
2.6.5 DDC (I2C) interface .................................................................................................................... 116
2.6.6 SDIO interface ............................................................................................................................ 120
2.7 Audio interface ....................................................................................................................................... 121
2.7.1 Digital audio interface ............................................................................................................... 121
2.8 General Purpose Input/Output (GPIO) ............................................................................................... 125
2.9 Reserved pins (RSVD) ........................................................................................................................... 126
2.10 Module placement ................................................................................................................................. 126
2.11 Module footprint and paste mask ...................................................................................................... 127
2.12 Thermal guidelines ................................................................................................................................ 128
2.13 ESD guidelines ........................................................................................................................................ 129
2.13.1 ESD immunity test overview ................................................................................................... 129
2.13.2 ESD immunity test of u-blox LARA-R2 series reference designs .................................... 129
2.13.3 ESD application circuits ........................................................................................................... 130
LARA-R2 series - System integration manual
UBX-16010573 - R21 Contents Page 6 of 163
C1-Public
2.14 Schematic for LARA-R2 series module integration ........................................................................ 133
2.15 Design-in checklist ................................................................................................................................. 134
2.15.1 Schematic checklist .................................................................................................................. 134
2.15.2 Layout checklist ......................................................................................................................... 134
2.15.3 Antenna checklist ...................................................................................................................... 135
3 Handling and soldering ................................................................................................................... 136
3.1 Packaging, shipping, storage and moisture preconditioning ....................................................... 136
3.2 Handling ................................................................................................................................................... 136
3.3 Soldering .................................................................................................................................................. 137
3.3.1 Soldering paste .......................................................................................................................... 137
3.3.2 Reflow soldering ......................................................................................................................... 137
3.3.3 Optical inspection ...................................................................................................................... 138
3.3.4 Cleaning ....................................................................................................................................... 138
3.3.5 Repeated reflow soldering ....................................................................................................... 139
3.3.6 Wave soldering ........................................................................................................................... 139
3.3.7 Hand soldering ............................................................................................................................ 139
3.3.8 Rework .......................................................................................................................................... 139
3.3.9 Conformal coating ..................................................................................................................... 139
3.3.10 Casting ......................................................................................................................................... 139
3.3.11 Grounding metal covers............................................................................................................ 140
3.3.12 Use of ultrasonic processes ..................................................................................................... 140
4 Approvals ............................................................................................................................................. 141
4.1 Product certification approval overview ............................................................................................ 141
4.2 US Federal Communications Commission notice ........................................................................... 142
4.2.1 Safety warnings review the structure ................................................................................... 142
4.2.2 Declaration of conformity ........................................................................................................ 142
4.2.3 Modifications .............................................................................................................................. 143
4.3 Innovation, Science, Economic Development Canada notice ....................................................... 144
4.3.1 Declaration of Conformity ........................................................................................................ 144
4.3.2 Modifications .............................................................................................................................. 145
4.4 European Conformance CE mark ....................................................................................................... 147
5 Product testing ................................................................................................................................. 148
5.1 u-blox in-series production test .......................................................................................................... 148
5.2 Test parameters for OEM manufacturers ........................................................................................ 149
5.2.1 “Go/No go” tests for integrated devices ............................................................................... 149
5.2.2 Functional tests providing RF operation .............................................................................. 149
Appendix ..................................................................................................................................................... 151
A Migration between SARA-U2 and LARA-R2 ............................................................................ 151
A.1 Overview ................................................................................................................................................... 151
A.2 Pin-out comparison between SARA-U2 and LARA-R2 .................................................................. 154
A.3 Schematic for SARA-U2 and LARA-R2 integration ........................................................................ 157
B Glossary ............................................................................................................................................... 158
LARA-R2 series - System integration manual
UBX-16010573 - R21 Contents Page 7 of 163
C1-Public
Related documentation ......................................................................................................................... 161
Revision history ........................................................................................................................................ 162
Contact ........................................................................................................................................................ 163
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 8 of 163
C1-Public
1 System description
1.1 Overview
The LARA-R2 series comprises LTE Cat 1 / 3G / 2G multi-mode modules in the very small LARA LGA
form-factor (26.0 x 24.0 mm, 100-pin) that are easy to integrate in compact designs.
LARA-R2 series modules support multi-band LTE-FDD Cat 1 radio access technology with seven
regional variants. Each variant is designed for specific regional market requirements to allow
development of cost efficient yet feature-rich products. The variants with 2G or 3G fallback provide
connectivity in cases where LTE coverage is not yet available. This allows seamless operation during
technology transition:
• LARA-R202 is designed mainly for operation in America (on LTE and 3G networks)
• LARA-R203 is designed mainly for operation in America (on LTE network)
• LARA-R204 is designed mainly for operation in North America (on the Verizon network)
• LARA-R211 is designed mainly for operation in EMEA (on LTE and 2G networks)
• LARA-R220 is designed mainly for operation in Japan (on the NTT DoCoMo LTE network)
• LARA-R280 is designed mainly for operation in APAC (on LTE and 3G networks)
• LARA-R281 is designed mainly for operation in EMEA (on LTE and 3G networks)
LARA-R2 series modules are form-factor compatible with the u-blox SARA, LISA and TOBY cellular
module families: this facilitates easy migration from u-blox GSM/GPRS, CDMA, UMTS/HSPA, and LTE
high data rate modules, maximizes the investments of customers, simplifies logistics, and enables
very short time-to-market. The modules are ideal for applications that are transitioning to LTE from
2G and 3G, due to the long term availability and scalability of LTE networks.
With a range of interface options and an integrated IP stack, the modules are designed to support a
wide range of data-centric applications. The unique combination of performance and flexibility make
these modules ideally suited for medium speed M2M applications, such as smart energy gateways,
remote access video cameras, digital signage, telehealth and telematics.
LARA-R2 series modules include product versions supporting Voice over LTE (VoLTE) and voice over
3G or 2G (CSFB) for applications that require voice, such as security and surveillance systems.
Thanks to the u-blox's CellLocate® technology, LARA-R2 series modules offer cost-effective location
estimation based on information from surrounding cellular base stations. A positioning solution with
CellLocate® and a u-blox GNSS module provides redundancy and accuracy that can be beneficial for
numerous applications.
The temperature range of –40 °C to +85 °C guarantees operation in harsh environments and in very
compact designs.
LARA-R2 modules are manufactured in ISO/TS 16949 certified sites, with the highest production
standards and the highest quality and reliability. Each module is fully tested and inspected during
production. Modules are qualified according to ISO 16750 – for systems installed in vehicles.
USB drivers and RIL software for Android are free of charge.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 9 of 163
C1-Public
Table 1 summarizes the main features and interfaces of the LARA-R2 series modules.
Model
Region
Radio Access
Technology
Positioning
Interfaces
Audio
Features
Grade
LTE bands
1
UMTS bands GSM bands GNSS via modem AssistNow Software CellLocate® UART
USB 2.0 HISC * SDIO * DDC (I
2C)
GPIOs Analog audio Digital audio Network indication VoLTE Antenna supervisor Embedded TCP/UDP stack Embedded HTTP,FTP,TSL
1.2
FW update via serial FOTA client Rx Diversity Dual stack IPv4 / IPv6 Standard Professional Automotive
LARA-R202
North
America
2,4
5,12
850
1900
● ● ●
22 1 1 1 1 9
● ● ●3 ● ● ● ● ● ●
● ●
LARA-R203
North
America
2,4,12
● ● ●
22 1 1 1 1 9
● ● ●3 ● ● ● ● ● ●
● ●
LARA-R204
North
America
4,13 1 1 1 1 1 9
●
● ● ● ● ● ● ● ●
LARA-R211
Europe
3,7,20
900
1800
●4
●4
●4
25 1 1 1 1 9
● ● ● ● ● ● ● ● ●
● ●
LARA-R220
Japan
1,19
● ● ●
1 1 1 1 1 9
●
● ● ● ● ● ● ● ●
LARA-R280
APAC
3,8,28
2100
● ● ●
1 1 1 1 1 9
● ● ■ ● ● ● ● ● ●
● ●
LARA-R281
EMEA
1,3,8
20,28
2100
● ● ●
1 1 1 1 1 9
● ● ■ ● ● ● ● ● ●
● ●
●= Available in any firmware
■ = CSFB only
* = HW ready
Table 1: LARA-R2 series main features summary
1
LTE band 12 is a superset including band 17: LTE band 12 is supported along with Multi-Frequency Band Indicator feature
2
Not supported by LARA-R202-02B, LARA-R202-82B, or LARA-R203-02B product versions
3
AT&T certified with VoLTE
4
External GNSS control via modem, AssistNow Software and CellLocate® are not supported by LARA-R211-02B-00
5
Second UART is not supported by LARA-R211-02B-00, LARA-R211-02B-01, LARA-R211-02B-02 product versions
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 10 of 163
C1-Public
Table 2 summarizes cellular radio access technology characteristics of LARA-R2 series modules.
4G LTE
3G UMTS/HSDPA/HSUPA
2G GSM/GPRS/EDGE
3GPP Release 9
Long Term Evolution (LTE)
Evolved UTRA (E-UTRA)
Frequency Division Duplex (FDD)
DL Rx diversity
3GPP Release 9
High Speed Packet Access (HSPA)
UMTS Terrestrial Radio Access (UTRA)
Frequency Division Duplex (FDD)
DL Rx Diversity
3GPP Release 9
Enhanced Data rate GSM Evolution (EDGE)
GSM EGPRS Radio Access (GERA)
Time Division Multiple Access (TDMA)
DL Advanced Rx Performance Phase 1
Band support6:
• LARA-R202:
• Band 12 (700 MHz)7
• Band 5 (850 MHz)
• Band 4 (1700 MHz)
• Band 2 (1900 MHz)
Band support:
• LARA-R202:
• Band 5 (850 MHz)
• Band 2 (1900 MHz)
Band support:
• LARA-R203:
• Band 12 (700 MHz)7
• Band 4 (1700 MHz)
• Band 2 (1900 MHz)
• LARA-R204:
• Band 13 (700 MHz)
• Band 4 (1700 MHz)
• LARA-R211:
• Band 20 (800 MHz)
• Band 3 (1800 MHz)
• Band 7 (2600 MHz)
• LARA-R211:
• E-GSM 900 MHz
• DCS 1800 MHz
• LARA-R220:
• Band 19 (850 MHz)
• Band 1 (2100 MHz)
• LARA-R280:
• Band 28 (700 MHz)
• Band 8 (900 MHz)
• Band 3 (1800 MHz)
• LARA-R280:
• Band 1 (2100 MHz)
• LARA-R281:
• Band 28 (700 MHz)
• Band 20 (800 MHz)
• Band 8 (900 MHz)
• Band 3 (1800 MHz)
• Band 1 (2100 MHz)
• LARA-R281:
• Band 1 (2100 MHz)
LTE Power Class
• Power Class 3 (23 dBm)
UMTS/HSDPA/HSUPA Power Class
• Class 3 (24 dBm)
GSM/GPRS (GMSK) Power Class
• Power Class 4 (33 dBm) for E-GSM band
• Power Class 1 (30 dBm) for DCS band
EDGE (8-PSK) Power Class
• Power Class E2 (27 dBm) for E-GSM band
• Power Class E2 (26 dBm) for DCS band
Data rate
• LTE category 1:
up to 10.3 Mb/s DL, 5.2 Mb/s UL
Data rate
• HSDPA category 8:
up to 7.2 Mb/s DL
• HSUPA category 6:
up to 5.76 Mb/s UL
Data Rate8
• GPRS multi-slot class 339, CS1-CS4,
up to 107 kb/s DL, up to 85.6 kb/s UL
• EDGE multi-slot class 339, MCS1-MCS9,
up to 296 kb/s DL, up to 236.8 kb/s UL
Table 2: LARA-R2 series LTE, 3G and 2G characteristics
6
LARA-R2 series modules support all the E-UTRA channel bandwidths for each operating band as per 3GPP TS 36.521-1 [13].
7
LTE band 12 is a superset including the band 17: LTE band 12 is supported along with Multi-Frequency Band Indicator feature
8
GPRS/EDGE multislot class determines the number of timeslots available for upload and download and thus the speed at
which data can be transmitted and received, with higher classes typically allowing faster data transfer rates.
9
GPRS/EDGE multislot class 33 implies a maximum of 5 slots in DL (reception), 4 slots in UL (transmission) with 6 slots in total.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 11 of 163
C1-Public
1.2 Architecture
Figure 1 summarizes the internal architecture of the LARA-R2 series modules.
Cellular
Base-band
processor
Memory
Power Management Unit
26 MHz
32.768 kHz
ANT1
RF
transceiver
ANT2
V_INT (I/O)
V_BCKP (RTC)
VCC (Supply)
SIM
USB
HSIC
Power On
External Reset
PAs
LNAsFilters
Filter
s
Duplexer
Filters
PAs
LNAsFilter
s
Filter
s
Duplexer
Filters
LNAsFilter
s
Filters
LNAsFiltersFilter
s
Switch
Switch
DDC(I2C)
SDIO
UART
ANT_DET
Host Select
GPIO
Digital audio (I2S)
Figure 1: LARA-R2 series modules simplified block diagram
LARA-R2 series modules internally consist of the RF, Baseband and Power Management sections
described herein with more details than the simplified block diagrams of Figure 1.
RF section
The RF section is composed of an RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and
RF switches.
The Tx signal is pre-amplified by the RF transceiver, then output to the primary antenna input/output
port (ANT1) of the module via power amplifier (PA), SAW band pass filters band, specific duplexer and
antenna switch.
Dual receiving paths are implemented according to LTE Receiver Diversity radio technology supported
by the modules as LTE category 1 User Equipment: the incoming signal is received through the
primary (ANT1) and the secondary (ANT2) antenna input ports, which are connected to the RF
transceiver via specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.
• RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx,
down-conversion and demodulation of the dual RF signals for Rx. The RF transceiver contains:
o Single chain high linearity receivers with integrated LNAs for multi-band multi-mode
operation,
o Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM,
o RF synthesizer,
o VCO.
• Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
• RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx
path
• SAW duplexers and band pass filters separate the Tx and Rx signal paths and provide RF filtering
• 26 MHz voltage-controlled temperature-controlled crystal oscillator generates the clock reference
in active mode or connected mode.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 12 of 163
C1-Public
Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
• A mixed signal ASIC, which integrates
o Microprocessor for control functions
o DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths
o Memory interface controller
o Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces
o Interfaces to RF transceiver ASIC
• Memory system, which includes NAND flash and LPDDR2 RAM
• Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
• Voltage sources for external use: V_BCKP and V_INT
• Hardware power on
• Hardware reset
• Low power idle mode support
• 32.768 kHz crystal oscillator to provide the clock reference in the low power idle mode, which can
be set by enable power saving configuration using the +UPSV AT command.
1.3 Pin-out
Table 3 lists the pin-out of the LARA-R2 series modules, with pins grouped by function.
Function
Pin name
Pin no.
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply input
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for description and requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14,
20, 22, 30,
32, 43, 50,
54, 55, 57,
58, 60, 61,
63-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_BCKP
2
I/O
RTC supply
input/output
V_BCKP = 1.8 V (typical) generated by internal regulator
when valid VCC supply is present.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
V_INT
4
O
Generic Digital
Interfaces supply
output
V_INT = 1.8 V (typical), generated by internal DC/DC
regulator when the module is switched on.
Test-Point for diagnostic access is recommended.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.
System
PWR_ON
15 I Power-on input
Internal 10 k pull-up resistor to V_BCKP.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
18 I External reset input
Internal 10 k pull-up resistor to V_BCKP.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
HOST_SELECT
21
I/O
Selection of module
/ host configuration
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
Pin available to select, enable, connect, disconnect and
subsequently re-connect the HSIC interface.
Test-Point for diagnostic access is recommended.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 13 of 163
C1-Public
Function
Pin name
Pin no.
I/O
Description
Remarks
Antenna
ANT1
56
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT2
62 I Secondary antenna
Rx only for Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT_DET
59
I
Input for antenna
detection
ADC for antenna presence detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
SIM
VSIM
41 O SIM supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38 O SIM clock
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40 O SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UART
RXD
13 O UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW
update by u-blox EasyFlash tool and diagnostic.
Test-Point and series 0 for diagnostic recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12 I UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW
update by u-blox EasyFlash tool and diagnostic.
Internal active pull-up to V_INT.
Test-Point and series 0 for diagnostic recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART ready to send
input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR 6 O
UART data set ready
output
1.8 V output, Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI 7 O
UART ring indicator
output
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 14 of 163
C1-Public
Function
Pin name
Pin no.
I/O
Description
Remarks
DTR 9 I
UART data terminal
ready input
1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT.
Test-Point and series 0 for diagnostic recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD 8 O
UART data carrier
detect output
1.8 V input, Circuit 109 (DCD) in ITU-T V.24.
Test-Point and series 0 for diagnostic recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
AUX
UART10
SCL
27
O
AUX UART data
output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands and diagnostic.
Auxiliary UART interface is disabled by default, and it can
be enabled by +USIO AT command alternatively to I2C.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
SDA
26
I
AUX UART data
input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands and diagnostic.
Internal active pull-up to V_INT.
Auxiliary UART interface is disabled by default, and it can
be enabled by +USIO AT command alternatively to I2C.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB
VUSB_DET
17 I USB detect input
VBUS (5 V typical) must be connected to this input pin to
enable the USB interface.
If the USB interface is not used by the Application
Processor, Test-Point for diagnostic / FW update access
recommended.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
USB_D-
28
I/O
USB Data Line D-
USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool, diagnostic
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors
as required by the USB 2.0 specifications [9] are part of
the USB pin driver and need not be provided externally.
If the USB interface is not used by the Host Processor,
Test-Point for diagnostic / FW update is recommended.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
USB_D+
29
I/O
USB Data Line D+
USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors
as required by the USB 2.0 specifications [9] are part of
the USB pin driver and need not be provided externally.
If the USB interface is not used by the Host Processor,
Test-Point for diagnostic / FW update is recommended
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
10
The auxiliary UART interface is not supported by the ‘02B’, ‘62B’ and ‘82B’ versions of LARA-R202, LARA-R203, LARA-R204,
LARA-R220, LARA-R280, and LARA-R281 modules, and by ‘02B-00’, ‘02B-01’ and ‘02B-02’ versions of LARA-R211 modules
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 15 of 163
C1-Public
Function
Pin name
Pin no.
I/O
Description
Remarks
HSIC
HSIC_DATA
99
I/O
HSIC USB data line
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
USB High-Speed Inter-Chip compliant interface for AT
commands, data communication, FOAT, FW update by
u-blox EasyFlash tool and diagnostic.
50 nominal characteristic impedance.
Test-Point for diagnostic / FW update is recommended.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
HSIC_STRB
100
I/O
HSIC USB strobe
line
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
HSIC interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.
50 nominal characteristic impedance.
Test-Point for diagnostic / FW update is recommended.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
DDC
SCL
27 O I2C bus clock line
1.8 V open drain, for communication with I2C-local devices
External pull-up required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDA
26
I/O
I2C bus data line
1.8 V open drain, for communication with I2C- local
devices
External pull-up required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO
SDIO_D0
47
I/O
SDIO serial data [0]
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
SDIO_D1
49
I/O
SDIO serial data [1]
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
SDIO_D2
44
I/O
SDIO serial data [2]
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
SDIO_D3
48
I/O
SDIO serial data [3]
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
SDIO_CLK
45 O SDIO serial clock
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
SDIO_CMD
46
I/O
SDIO command
Not supported by ‘02B’, ‘62B’, ‘82B’, ‘03B’ product versions.
SDIO for communication with u-blox Wi-Fi module
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
Audio
I2S_TXD
35
O / I/O
I2S transmit data /
GPIO
I2S transmit data out, alternatively configurable as GPIO.
I2S not supported by LARA-R204-02B / LARA-R220-62B.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_RXD
37
I / I/O
I2S receive data /
GPIO
I2S receive data input, alternatively configurable as GPIO.
I2S not supported by LARA-R204-02B / LARA-R220-62B.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 16 of 163
C1-Public
Function
Pin name
Pin no.
I/O
Description
Remarks
I2S_CLK
36
I/O /
I/O
I2S clock /
GPIO
I2S serial clock, alternatively configurable as GPIO.
I2S not supported by LARA-R204-02B / LARA-R220-62B.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_WA
34
I/O /
I/O
I2S word alignment /
GPIO
I2S word alignment, alternatively configurable as GPIO.
I2S not supported by LARA-R204-02B / LARA-R220-62B.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
Clock
output
GPIO6
19 O Clock output
1.8 V configurable clock output.
See section 1.11 for functional description.
See section 2.7 for external circuit design-in.
GPIO
GPIO1
16
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
33
N/A
RESERVED pin
This pin must be connected to ground.
See sections 1.13 and 2.9
RSVD
31, 97, 98
N/A
RESERVED pin
Internally not connected. Leave unconnected.
See sections 1.13 and 2.9
Table 3: LARA-R2 series modules pin definition, grouped by function
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 17 of 163
C1-Public
1.4 Operating modes
LARA-R2 series modules have several operating modes. The operating modes defined in Table 4 and
described in detail in Table 5 provide general guidelines for operation.
General status
Operating mode
Definition
Power-down
Not-powered Mode
VCC supply not present or below operating range: module is switched off.
Power-off Mode
VCC supply within operating range and module is switched off.
Normal operation
Idle mode
Module processor core runs with 32 kHz reference generated by the internal oscillator.
Active mode
Module processor core runs with 26 MHz reference generated by the internal oscillator.
Connected mode
RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.
Table 4: Module operating modes definition
Mode
Description
Transition between operating modes
Not-powered
Module is switched off.
Application interfaces are not
accessible.
When VCC supply is removed, the module enters not-powered mode.
When in not-powered mode, the modules cannot be switched on by
PWR_ON, RESET_N or RTC alarm.
When in not-powered mode, the modules can be switched on applying
VCC supply (see 1.6.1) so that the module switches from not-
powered to active mode.
Power-off
Module is switched off: normal
shutdown by an appropriate power-off
event (see 1.6.2).
Application interfaces are not accessible.
When the module is switched off by an appropriate switch-off event
(see 1.6.2), the module enters power-off mode from active mode.
When in power-off mode, the modules can be switched on by
PWR_ON, RESET_N or RTC alarm (see 1.6.1): the module switches
from power-off to active mode.
When in power-off mode, the modules enter not-powered mode by
removing the VCC supply.
Idle
Module is switched on with application
interfaces temporarily disabled or
suspended: the module is temporarily
not ready to communicate with an
external device by means of the
application interfaces as configured to
reduce the current consumption.
The module enters the low power idle
mode whenever possible if power saving
is enabled by AT+UPSV (see u-blox AT
commands manual [2]) reducing power
consumption (see 1.5.1.5).
The CTS output line indicates when the
UART interface is disabled/enabled due
to the module idle/active mode
according to power saving and HW flow
control settings (see 1.9.1.3, 1.9.1.4).
Power saving configuration is not
enabled by default: it can be enabled by
AT+UPSV (see the u-blox AT commands
manual [2]).
The module automatically switches from active mode to idle mode
whenever possible if power saving is enabled (see sections 1.5.1.5,
1.9.1.4, 1.9.3.4 and to the u-blox AT commands manual [2], AT+UPSV
command).
The module wakes up from idle to active mode in the following
events:
• Automatic periodic monitoring of the paging channel for the
paging block reception according to network conditions
(see 1.5.1.4, 1.9.1.4)
• Automatic periodic enable of the UART interface to receive and
send data, if AT+UPSV=1 power saving is set (see 1.9.1.4)
• Data received on UART interface, according to HW flow control
(AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)
• RTS input set ON by the host DTE, with HW flow control disabled
and AT+UPSV=2 (see 1.9.1.4)
• DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4)
• USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.3)
• The connected USB host forces a remote wakeup of the module as
USB device (see 1.9.3.4)
• The connected u-blox GNSS receiver forces a wakeup of the
cellular module using the GNSS Tx data ready function over the
GPIO3 pin (see 1.9.5)
• The connected SDIO device forces a wakeup of the module as
SDIO host (see 1.9.6)
• RTC alarm occurs (see u-blox AT commands manual [2], +CALA)
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 18 of 163
C1-Public
Mode
Description
Transition between operating modes
Active
The module is ready to communicate
with an external device by means of the
application interfaces unless power
saving configuration is enabled by the
AT+UPSV command (see sections
1.5.1.4, 1.9.1.4 and to the u-blox AT
commands manual [2]).
When the module is switched on by an appropriate power-on event
(see 2.3.1), the module enters active mode from not-powered or
power-off mode.
If power saving configuration is enabled by the AT+UPSV command,
the module automatically switches from active to idle mode
whenever possible and the module wakes up from idle to active mode
in the events listed above (see idle to active transition description).
When a voice call or a data call is initiated, the module switches from
active mode to connected mode.
Connected
A voice call or a data call is in progress.
The module is ready to communicate
with an external device by means of the
application interfaces unless power
saving configuration is enabled by the
AT+UPSV command (see sections
1.5.1.4, 1.9.1.4 and the u-blox AT
commands manual [2]).
When a data or voice connection is initiated, the module enters
connected mode from active mode.
Connected mode is suspended if Tx/Rx data is not in progress, due to
connected discontinuous reception and fast dormancy capabilities of
the module and according to network environment settings and
scenario. In such case, the module automatically switches from
connected to active mode and then, if power saving configuration is
enabled by the AT+UPSV command, the module automatically
switches to idle mode whenever possible. Vice-versa, the module
wakes up from idle to active mode and then connected mode if RF
Tx/Rx is necessary.
When a data connection is terminated, the module returns to the
active mode.
Table 5: Module operating modes descriptions
Figure 2 describes the transition between the different operating modes.
Switch ON:
• Apply VCC
If power saving is enabled
and there is no activity for
a defined time interval
Any wake up event described
in the module operating
modes summary table above
Incoming/outgoing call or
other dedicated device
network communication
No RF Tx/Rx in progress,
Call terminated,
Communication dropped
Remove VCC
Switch ON:
• PWR_ON
• RTC alarm
• RESET_N
Not
powered
Power off
ActiveConnected Idle
Switch OFF:
• AT+CPWROFF
• PWR_ON
Figure 2: Operating modes transition
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 19 of 163
C1-Public
1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via the three VCC pins that represent the module power supply input.
The VCC pins are internally connected to the RF power amplifier and to the integrated Power
Management Unit: all supply voltages needed by the module are generated from the VCC supply by
integrated voltage regulators, including the V_BCKP Real Time Clock supply, V_INT digital interfaces
supply and VSIM SIM card supply.
During operation, the current drawn by the LARA-R2 series modules through the VCC pins can vary
by several orders of magnitude. This ranges from the pulse of current consumption during GSM
transmitting bursts at maximum power level in connected mode (as described in section 1.5.1.2) to
the low current consumption during low power idle mode with power saving enabled (as described in
section 1.5.1.5).
LARA-R211 modules provide separate supply inputs over the three VCC pins:
• VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding
most of the total current drawn of the module when RF transmission is enabled during a
voice/data call
• VCC pin #51 represents the supply input for the internal baseband Power Management Unit and
the internal transceiver, demanding minor part of the total current drawn of the module when RF
transmission is enabled during a voice/data call
Figure 3 provides a simplified block diagram of LARA-R2 series modules internal VCC supply routing.
53
VCC
52
VCC
51
VCC
LARA-R2 series
(except LARA-R211)
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
RF PMU
LTE PA
53
VCC
52
VCC
51
VCC
LARA-R211
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
RF PMU
LTE / 2G PAs
Figure 3: LARA-R2 series modules internal VCC supply routing simplified block diagram
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 20 of 163
C1-Public
1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the
suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6.
⚠ VCC supply circuit affects the RF compliance of the device integrating LARA-R2 series modules
with applicable required certification schemes as well as antenna circuit design. Compliance is
met by fulfilling the requirements for the VCC supply summarized in Table 6.
Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
3.30 V min. / 4.40 V max.
RF performance is guaranteed when VCC PA voltage
is inside the normal operating range limits.
RF performance may be affected when VCC PA
voltage is outside the normal operating range limits,
though the module is still fully functional until the
VCC voltage is inside the extended operating range
limits.
VCC voltage during
normal operation
Within VCC extended operating range:
3.00 V min. / 4.50 V max.
VCC voltage must be above the extended operating
range minimum limit to switch-on the module.
The module may switch-off when the VCC voltage
drops below the extended operating range minimum
limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.
VCC average current
Support with adequate margin the highest
averaged VCC current consumption value in
connected mode conditions specified in
LARA-R2 series data sheet [1]
The highest averaged VCC current consumption can
be greater than the specified value according to the
actual antenna mismatching, temperature and VCC
voltage.
See 1.5.1.2, 1.5.1.4 for connected mode current
profiles.
VCC peak current
Support with margin the highest peak VCC
current consumption value in connected mode
conditions specified in LARA-R2 series data
sheet [1]
The specified highest peak of VCC current
consumption occurs during GSM single transmit slot
in 850/900 MHz connected mode, in case of a
mismatched antenna.
See 1.5.1.2 for 2G connected mode current profiles.
VCC voltage drop
during 2G Tx slots
Lower than 400 mV
VCC voltage drop directly affects the RF compliance
with applicable certification schemes.
Figure 5 describes VCC voltage drop during Tx slots.
VCC voltage ripple
during 2G/3G/LTE Tx
Noise in the supply must be minimized
VCC voltage ripple directly affects the RF
compliance with applicable certification schemes.
Figure 5 describes VCC voltage ripple during Tx slots.
VCC under/over-shoot
at start/end of Tx
slots
Absent or at least minimized
VCC under/over-shoot directly affects the RF
compliance with applicable certification schemes.
Figure 5 describes VCC voltage under/over-shoot.
Table 6: Summary of VCC supply requirements
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 21 of 163
C1-Public
1.5.1.2 VCC consumption in 2G connected mode
When a GSM call is established, the VCC consumption is determined by the current consumption
profile typical of the GSM transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted
power, which is regulated by the network. The transmitted power in the transmit slot is also the more
relevant factor for determining the average current consumption.
If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz
bands, at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the
current consumption can reach an high peak / pulse (see LARA-R2 series data sheet [1]) for 576.9 µs
(width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so
with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).
If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current
consumption figures are quite less high than the one in the low bands, due to the 3GPP transmitter
output power specifications.
During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts
and it is low in the bursts unused to transmit / receive.
Figure 4 shows an example of the module current consumption profile versus time in GSM talk mode.
Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-120 mA
1900 mA
Peak current depends
on TX power and actual
antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
60-120 mA
10 -40 mA
0.0
1.5
1.0
0.5
2.0
Figure 4: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)
Figure 5 illustrates VCC voltage profile versus time during a GSM call, according to the related VCC
current consumption profile described in Figure 4.
Time
undershoot
overshoot
ripple
drop
Voltage
3.8 V
(typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
Figure 5: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot)
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 22 of 163
C1-Public
When a GPRS connection is established, more than one slot can be used to transmit and/or more than
one slot can be used to receive. The transmitted power depends on network conditions, which set the
peak current consumption, but following the 3GPP specifications the maximum Tx RF power is
reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as
can be the case with a 2G single-slot call.
The multi-slot transmission power can be further reduced by configuring the actual Multi-Slot Power
Reduction profile with the dedicated AT command, AT+UDCONF=40 (see the u-blox AT commands
manual [2]).
If the module transmits in GPRS class 12 in the 850 or 900 MHz bands, at the maximum RF power
control level, the current consumption can reach a quite high peak but lower than the one achievable
in 2G single-slot mode. This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a
periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to 2G
TDMA.
If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, the current consumption
figures are quite less high than the one in the low bands, due to 3GPP transmitter output power
specifications.
Figure 6 reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or
900 MHz bands, with 4 slots used to transmit and 1 slot used to receive.
Time [ms]
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
RX
slot
unused
slot
TX
slot
TX
slot
TX
slot
TX
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200mA
60-130mA
Peak current depends
on TX power and
actual antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
1600 mA
0.0
1.5
1.0
0.5
2.0
Figure 6: VCC current consumption profile versus time during a 2G GPRS/EDGE multi-slot connection (4 TX slots, 1 RX slot)
For EDGE connections, the VCC current consumption profile is very similar to the GPRS current
profile, so the image shown in Figure 6, representing the current consumption profile in GPRS class
12 connected mode, is valid for the EDGE class 12 connected mode as well.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 23 of 163
C1-Public
1.5.1.3 VCC consumption in 3G connected mode
During a 3G connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA).
The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 666 µs, so the rate of power change can reach a maximum
rate of 1.5 kHz.
There are no high current peaks as in the 2G connection, since transmission and reception are
continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA
implemented in the 2G case.
In the worst case scenario, corresponding to a continuous transmission and reception at maximum
output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the
VCC pins is considerable (see the “Current consumption” section in LARA-R2 series data sheet [1]).
At the lowest output RF power (approximately 0.01 µW or –50 dBm), the current drawn by the internal
power amplifier is strongly reduced. The total current drawn by the module at the VCC pins is due to
baseband processing and transceiver activity.
Figure 7 shows an example of the current consumption profile of the module in 3G WCDMA/HSPA
continuous transmission mode.
Time
[ms]
3G frame
10 ms
(1 frame = 15 slots)
Current [mA]
Current consumption value
depends on TX power and
actual antenna load
170
mA
1 slot
666 µs
850
mA
0
300
200
100
500
400
600
700
Figure 7: VCC current consumption profile versus time during a 3G connection (TX and RX continuously enabled)
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 24 of 163
C1-Public
1.5.1.4 VCC consumption in LTE connected mode
During an LTE connection, the module can transmit and receive continuously due to the Frequency
Division Duplex (FDD) mode of operation used in LTE radio access technology.
The current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate
of power change can reach a maximum rate of 2 kHz.
The current consumption profile is similar to that in 3G radio access technology. Unlike the 2G
connection mode, which uses the TDMA mode of operation, there are no high current peaks since
transmission and reception are continuously enabled in FDD.
In the worst case scenario, corresponding to a continuous transmission and reception at maximum
output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the
VCC pins is considerable (see the “Current consumption” section in LARA-R2 series data sheet [1]).
At the lowest output RF power (approximately 0.1 µW or –40 dBm), the current drawn by the internal
power amplifier is strongly reduced and the total current drawn by the module at the VCC pins is due
to baseband processing and transceiver activity.
Figure 8 shows an example of the module current consumption profile versus time in LTE connected
mode. Detailed current consumption values can be found in LARA-R2 series data sheet [1].
Time
[ms]
Current [mA]
Current consumption value
depends on TX power and
actual antenna load
1 Slot
1 Resource Block
(0.5 ms)
1 LTE Radio Frame
(10 ms)
0
300
200
100
500
400
600
700
Figure 8: VCC current consumption profile versus time during LTE connection (TX and RX continuously enabled)
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 25 of 163
C1-Public
1.5.1.5 VCC consumption in cyclic idle/active mode (power saving enabled)
The power saving configuration is disabled by default, but it can be enabled using the appropriate AT
command (see u-blox AT commands manual [2], AT+UPSV command). When power saving is enabled,
the module automatically enters low power idle mode whenever possible, reducing current
consumption.
When the power saving configuration is enabled and the module is registered or attached to a
network, the module automatically enters the low power idle mode whenever possible, but it must
periodically monitor the paging channel of the current base station (paging block reception), in
accordance to the 2G / 3G / LTE system requirements, even if connected mode is not enabled by the
application. When the module monitors the paging channel, it wakes up to the active mode to enable
the reception of the paging block. In between, the module switches to low power idle mode. This is
known as discontinuous reception (DRX).
The module processor core is activated during the paging block reception, and automatically switches
its reference clock frequency from 32 kHz to the 26 MHz used in active mode.
The time period between two paging block receptions is defined by the network. This is the paging
period parameter, fixed by the base station through broadcast channel sent to all users on the same
serving cell:
• For 2G RAT, the paging period can vary from 470.8 ms (DRX = 2, length of 2 x 51 2G frames =
2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms)
• For 3G radio access technology, the paging period can vary from 640 ms (DRX = 6, i.e. length of 2
6
3G frames = 64 x 10 ms) up to 5120 ms (DRX = 9, length of 29 3G frames = 512 x 10 ms).
• For LTE radio access technology, the paging period can vary from 320 ms (DRX = 5, i.e. length of
25 LTE frames = 32 x 10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms).
Figure 9 illustrates a typical example of the module current consumption profile when power saving is
enabled. The module is registered with the network, automatically enters the low power idle mode and
periodically wakes up to active mode to monitor the paging channel for the paging block reception.
Detailed current consumption values can be found in the LARA-R2 series data sheet [1]).
~50 ms
IDLE MODE ACTIVE MODE IDLE MODE
Active Mode
Enabled
Idle Mode
Enabled
2G case: 0.44-2.09 s
3G case: 0.61-5.09 s
LTE case: 0.27-2.51 s
IDLE MODE
~50 ms
ACTIVE MODE
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
Figure 9: VCC current consumption profile with power saving enabled and module registered with the network: the module
is in low-power idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 26 of 163
C1-Public
1.5.1.6 VCC consumption in fixed active mode (power saving disabled)
Power saving configuration is disabled by default, or it can be disabled using the appropriate AT
command (see the u-blox AT commands manual [2], AT+UPSV command). When power saving is
disabled, the module does not automatically enter idle mode whenever possible: the module remains
in active mode.
The module processor core is activated during active mode, and the 26 MHz reference clock frequency
is used.
Figure 10 illustrates a typical example of the module current consumption profile when power saving
is disabled. In such case, the module is registered with the network and while active mode is
maintained, the receiver is periodically activated to monitor the paging channel for paging block
reception. Detailed current consumption values can be found in the LARA-R2 series data sheet [1].
ACTIVE MODE
2G case: 0.44-2.09 s
3G case: 0.61-5.09 s
LTE case: 0.32-2.56 s
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
Figure 10: VCC current consumption profile with power saving disabled and module registered with the network: active mode
is always held and the receiver is periodically activated to monitor the paging channel for paging block reception
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 27 of 163
C1-Public
1.5.2 RTC supply input/output (V_BCKP)
The V_BCKP pin of LARA-R2 series modules connects the supply for the Real Time Clock (RTC) and
Power-On internal logic. This supply domain is internally generated by a linear LDO regulator
integrated in the Power Management Unit, as described in Figure 11. The output of this linear
regulator is always enabled when the main voltage supply provided to the module through the VCC
pins is within the valid operating range, with the module switched off or switched on.
Baseband
Processor
51
VCC
52
VCC
53
VCC
2
V_BCKP
Linear
LDO
RTC
Power
Management
LARA-R2 series
32 kHz
Figure 11: RTC supply input/output (V_BCKP) and 32 kHz RTC timing reference clock simplified block diagram
The RTC provides the module time reference (date and time) that is used to set the wake-up interval
during the low power idle mode periods, and is able to make the programmable alarm functions
available.
The RTC functions are also available in power-down mode when the V_BCKP voltage is within its valid
range (specified in the “Input characteristics of Supply/Power pins” table in LARA-R2 series data
sheet [1]). The RTC can be supplied from an external back-up battery through the V_BCKP, when the
main module voltage supply is not applied to the VCC pins. This lets the time reference (date and time)
run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to
the module.
Consider that the module cannot switch on if a valid voltage is not present on VCC, even when the
RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).
The RTC has a very low current consumption, but is highly temperature dependent. For example,
V_BCKP current consumption at the maximum operating temperature can be higher than the typical
value at +25 °C specified in the “Input characteristics of Supply/Power pins” table in the LARA-R2
series data sheet [1].
If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is
supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to
provide a long buffering time: within a few milliseconds, the voltage on V_BCKP will drop below the
valid range. This has no impact on cellular connectivity, as all the module functionalities do not rely on
date and time settings.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 28 of 163
C1-Public
1.5.3 Generic digital interfaces supply output (V_INT)
The V_INT output pin of the LARA-R2 series modules is connected to an internal 1.8 V supply with a
current capability specified in the LARA-R2 series data sheet [1]. This supply is internally generated
by a switching step-down regulator integrated in the Power Management Unit and it is internally used
to source the generic digital I/O interfaces of the cellular module, as described in Figure 12. The output
of this regulator is enabled when the module is switched on and it is disabled when the module is
switched off.
Baseband
Processor
51
VCC
52
VCC
53
VCC
4
V_INT
Switching
Step-Down
Digital I/O
Interfaces
Power
Management
LARA-R2 series
Figure 12: LARA-R2 series interfaces supply output (V_INT) simplified block diagram
The switching regulator operates in Pulse Width Modulation (PWM) mode for greater efficiency at
high output loads and it automatically switches to Pulse Frequency Modulation (PFM) power save
mode for greater efficiency at low output loads. The V_INT output voltage ripple is specified in the
LARA-R2 series data sheet [1].
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 29 of 163
C1-Public
1.6 System function interfaces
1.6.1 Module power-on
When the LARA-R2 series modules are in the not-powered mode (switched off, i.e. the VCC module
supply is not applied), they can be switched on as following:
• Rising edge on the VCC input to a valid voltage for module supply, i.e. applying module supply: the
modules switch on if the VCC supply is applied, starting from a voltage value of less than 2.1 V,
with a rise time from 2.3 V to 2.8 V of less than 4 ms, reaching a proper nominal voltage value
within the VCC operating range.
Alternately, in case for example the fast rise time on VCC rising edge cannot be guaranteed by the
application, LARA-R2 series modules can be switched on from not-powered mode as following:
• RESET_N input pin is held low by the external application during the VCC rising edge, so that the
modules will switch on when the external application releases the RESET_N input pin from the low
logic level after the VCC supply voltage stabilizes at its proper nominal value within the operating
range
• PWR_ON input pin is held low by the external application during the VCC rising edge, so that the
modules will switch on when the external application releases the PWR_ON input pin from the low
logic level after the VCC supply voltage stabilizes at its proper nominal value within the operating
range
When the LARA-R2 series modules are in the power-off mode (i.e. properly switched off as described
in section 1.6.2, with valid VCC module supply applied), they can be switched on as following:
• Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time
period: the modules start the internal switch-on sequence when the external application releases
the PWR_ON pin from the low logic level after that it has been set low for an appropriate time
period
• Rising edge on the RESET_N pin, i.e. releasing the pin from the low level, as that the pin is normally
set high by an internal pull-up: the modules start the internal switch-on sequence when the
external application releases the RESET_N pin from the low logic level
• RTC alarm, i.e. pre-programmed alarm by AT+CALA command (see the u-blox AT commands
manual [2]).
As described in Figure 13, the LARA-R2 series PWR_ON input is equipped with an internal active
pull-up resistor to the V_BCKP supply: the PWR_ON input voltage thresholds are different from the
other generic digital interfaces. Detailed electrical characteristics are described in the LARA-R2 series
data sheet [1].
Baseband
Processor
15
PWR_ON
LARA-R2 series
2
V_BCKP
Power-on
Power
Management
Power-on
10k
Figure 13: LARA-R2 series PWR_ON input description
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 30 of 163
C1-Public
Figure 14 shows the module switch-on sequence from the not-powered mode, describing the
following phases:
• The external supply is applied to the VCC module supply inputs, representing the start-up event.
• The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage
value.
• The PWR_ON and the RESET_N pins suddenly rise to high logic level due to internal pull-ups.
• All the generic digital pins of the module are tri-stated until the switch-on of their supply source
(V_INT).
• The internal reset signal is held low: the baseband core and all the digital pins are held in the reset
state. The reset state of all the digital pins is reported in the pin description table of LARA-R2
series data sheet [1].
• When the internal reset signal is released, any digital pin is set in a proper sequence from the reset
state to the default operational configured state. The duration of this pins’ configuration phase
differs within generic digital interfaces and the USB interface due to host / device enumeration
timings (see section 1.9.3).
• The module is fully ready to operate after all interfaces are configured.
VCC
V_BCKP
PWR_ON
RESET_N
V_INT
Internal Reset
System State
BB Pads State
Internal Reset → Operational
Operational
Tristate / Floating
Internal Reset
OFF
ON
Start of interface
configuration
Module interfaces
are configured
Start-up
event
Figure 14: LARA-R2 series switch-on sequence description
The greeting text can be activated by means of the +CSGT AT command (see u-blox AT commands
manual [2]) to notify the external application that the module is ready to operate (i.e. ready to reply to
AT commands) and the first AT command can be sent to the module, given that autobauding must
be disabled on the UART to let the module sending the greeting text: the UART must be configured
at a fixed baud rate (the baud rate of the application processor) instead of the default autobauding,
otherwise the module does not know the baud rate to be used for sending the greeting text (or any
other URC) at the end of the internal boot sequence.
☞ The Internal Reset signal is not available on a module pin, but the host application can monitor the
V_INT pin to sense the start of the LARA-R2 series module switch-on sequence.
☞ Before the switch-on of the generic digital interface supply source (V_INT) of the module, no
voltage driven by an external application should be applied to any generic digital interface of the
module.
☞ Before the LARA-R2 series module is fully ready to operate, the host application processor should
not send any AT command over the AT communication interfaces (USB, UART) of the module.
☞ The duration of the LARA-R2 series modules’ switch-on routine can vary depending on the
application / network settings and any concurrent module activities.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 31 of 163
C1-Public
1.6.2 Module power-off
LARA-R2 series can be properly switched off by:
• AT+CPWROFF command (see u-blox AT commands manual [2]). The current parameter settings
are saved in the module’s non-volatile memory and a proper network detach is performed.
• Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time
period (see the LARA-R2 series data sheet [1]): the modules start the internal switch-off sequence
when the external application releases the PWR_ON line from the low logic level, after that it has
been set low for an appropriate time period.
An abrupt under-voltage shutdown occurs on LARA-R2 series modules when the VCC module supply
is removed. If this occurs, it is not possible to perform the storing of the current parameter settings
in the module’s non-volatile memory or to perform a proper network detach.
☞ It is highly recommended to avoid an abrupt removal of the VCC supply during LARA-R2 series
modules normal operations: the switch-off procedure must be started by the AT+CPWROFF
command, waiting for the command response for an appropriate time period (see the u-blox AT
commands manual [2]), and then a proper VCC supply must be held at least until the end of the
modules’ internal switch-off sequence, which occurs when the generic digital interfaces supply
output (V_INT) is switched off by the module.
An abrupt hardware shutdown occurs on LARA-R2 series modules when a low level is applied on the
RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile
memory and a proper network detach is not performed.
☞ It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low
level on the RESET_N input pin during module normal operation: the RESET_N line should be set
low only if a reset or shutdown via AT commands fails or if the module does not reply to a specific
AT command after a time period longer than the one defined in the u-blox AT commands
manual [2].
An over-temperature or an under-temperature shutdown occurs on LARA-R2 series modules when
the temperature measured within the cellular module reaches the dangerous area, if the optional
Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For
more details, see section 1.14.15 and u-blox AT commands manual [2], +USTS AT command.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 32 of 163
C1-Public
Figure 15 illustrates the LARA-R2 series modules switch-off sequence started by means of the
AT+CPWROFF command, allowing storage of the current parameter settings in the module’s
non-volatile memory and a proper network detach, with the following phases:
• When the +CPWROFF AT command is sent, the module starts the switch-off routine.
• The module replies OK on the AT interface: the switch-off routine is in progress.
• At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).
• Then the module remains in power-off mode as long as a -on event does not occur (e.g. applying a
proper low level to the PWR_ON input, or applying a proper low level to the RESET_N input), and
enters not-powered mode if the supply is removed from the VCC pins.
VCC
V_BCKP
PWR_ON
RESET_N
V_INT
Internal reset
System state
BB pads state Operational
OFF
Tristate / Floating
ON
Operational →
Tristate
AT+CPWROFF
sent to the module
OK
replied by the module
VCC
can be removed
Figure 15: LARA-R2 series switch-off sequence by means of AT+CPWROFF command
☞ The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT pin to sense the end of the LARA-R2 series switch-off sequence.
☞ The VCC supply can be removed only after the end of the module internal switch-off routine, i.e.
only after that the V_INT voltage level has gone low.
☞ The duration of each phase in the LARA-R2 series modules’ switch-off routines can largely vary
depending on the application / network settings and the concurrent module activities.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 33 of 163
C1-Public
Figure 16 illustrates the LARA-R2 series modules’ switch-off sequence started by means of the
PWR_ON input pin, allowing storage of current parameter settings in the module’s non-volatile
memory and a proper network detach, with the following phases:
• A low pulse with appropriate time duration (see LARA-R2 series data sheet [1]) is applied at the
PWR_ON input pin, which is normally set high by an internal pull-up: the module starts the switchoff routine when the PWR_ON signal is released from the low logical level.
• At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage
regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC
supply (V_BCKP).
• Then the module remains in power-off mode as long as a switch-on event does not occur
(e.g. applying a proper low level to the PWR_ON input, or applying a proper low level to the
RESET_N input), and enters not-powered mode if the supply is removed from the VCC pins.
VCC
V_BCKP
PWR_ON
RESET_N
V_INT
Internal Reset
System state
BB pads state
OFF
Tristate / Floating
ON
Operational -> Tristate
Operational
The module starts
the switch-off
VCC
can be removed
Figure 16: LARA-R2 series switch-off sequence by means of PWR_ON pin
☞ The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT pin to sense the end of the switch-off sequence.
☞ The VCC supply can be removed only after the end of the module internal switch-off routine,
i.e. only after that the V_INT voltage level has gone low.
☞ The duration of each phase in the LARA-R2 series modules’ switch-off routines can largely vary
depending on the application / network settings and the concurrent module activities.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 34 of 163
C1-Public
1.6.3 Module reset
LARA-R2 series modules can be properly reset (rebooted) by:
• AT+CFUN command (see the u-blox AT commands manual [2] for more details).
This command causes an “internal” or “software” reset of the module, which is an asynchronous reset
of the module baseband processor. The current parameter settings are saved in the module’s
non-volatile memory and a proper network detach is performed: this is the correct way to reset the
modules.
An abrupt hardware reset occurs on LARA-R2 series modules when a low level is applied on the
RESET_N input pin for a specific time period. In this case, the current parameter settings are not
saved in the module’s non-volatile memory and a proper network detach is not performed.
☞ It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on
the RESET_N input during modules normal operation: the RESET_N line should be set low only if
reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT
command after a time period longer than the one defined in the u-blox AT commands manual [2].
As described in Figure 17, the RESET_N input pins are equipped with an internal pull-up to the
V_BCKP supply.
Baseband
Processor
18
RESET_N
LARA-R2 series
2
V_BCKP
Reset
Power
Management
Reset
10k
Figure 17: LARA-R2 series RESET_N input equivalent circuit description
☞ For more electrical characteristics details, see the LARA-R2 series data sheet [1].
1.6.4 Module / host configuration selection
☞ The HOST_SELECT pin functionality is not supported by the "02B", "62B", "82B", and "03B"
product versions.
The modules include one pin (HOST_SELECT) to select the module / host application processor
configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect
the HSIC interface.
The LARA-R2 series data sheet [1] describes the detailed electrical characteristics of the
HOST_SELECT pin.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 35 of 163
C1-Public
1.7 Antenna interface
1.7.1 Antenna RF interfaces (ANT1 / ANT2)
LARA-R2 series modules provide two RF interfaces for connecting the external antennas:
• ANT1 represents the primary RF input/output for transmission and reception of RF signals.
• ANT1 pin has a nominal characteristic impedance of 50 and must be connected to the primary
Tx / Rx antenna through a 50 transmission line to allow proper RF transmission and reception.
• ANT2 represents the secondary RF input for the reception of the LTE / 3G RF signals for the Down-
Link Rx diversity radio technology supported by LARA-R2 modules as a required feature for LTE
category 1 UEs.
• ANT2 pin has a nominal characteristic impedance of 50 and must be connected to the
secondary Rx antenna through a 50 transmission line to allow proper RF reception.
1.7.1.1 Antenna RF interface requirements
Table 7, Table 8 and Table 9 summarize the requirements for the RF interfaces (ANT1 / ANT2). See
section 2.4.1 for suggestions to properly design the circuits compliant with these requirements.
⚠ The antenna circuits affect the RF compliance of the host end-device integrating the LARA-R2
series modules with applicable required certification schemes (for more details see section 4).
Compliance is met by fulfilling the requirements for the antenna RF interfaces (ANT1 / ANT2)
summarized in Table 7, Table 8 and Table 9.
Item
Requirement
Remark
Impedance
50 nominal characteristic
impedance
The impedance of the antenna RF connection must match the 50
impedance of the ANT1 port.
Frequency Range
See the LARA-R2 series data
sheet [1]
The required frequency range of the antenna connected to the ANT1 port
depends on the operating bands of the used cellular module and the used
mobile network.
Return Loss
S11 < -10 dB (VSWR < 2:1)
recommended
S11 < -6 dB (VSWR < 3:1)
acceptable
The Return loss or the S11, as the VSWR, refers to the amount of
reflected power, measuring how well the antenna RF connection matches
the 50 characteristic impedance of the ANT1 port.
The impedance of the antenna termination must match as much as
possible the 50 nominal impedance of the ANT1 port over the
operating frequency range, reducing as much as possible the reflected
power.
Efficiency
> -1.5 dB ( > 70% ) recommended
> -3.0 dB ( > 50% ) acceptable
The radiation efficiency is the ratio of the radiated power to the power
delivered to the antenna input: the efficiency is a measure of how well an
antenna receives or transmits.
The radiation efficiency of the antenna connected to the ANT1 port
needs to be enough high over the operating frequency range to comply
with the Over-The-Air (OTA) radiated performance requirements, as the
Total Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS),
specified by the applicable related certification schemes.
Maximum Gain
According to radiation exposure
limits
The power gain of an antenna is the radiation efficiency multiplied by the
directivity: the gain describes how much power is transmitted in the
direction of peak radiation to that of an isotropic source.
The maximum gain of the antenna connected to the ANT1 port must not
exceed the herein stated value to comply with regulatory agencies
radiation exposure limits.
For additional info, see sections 4.2.2, 4.3.1 and/or 4.4.
Input Power
> 33 dBm (> 2 W ) for LARA-R211
> 24 dBm (> 250 mW ) for other
LARA-R2
The antenna connected to the ANT1 port must support the maximum
power transmitted by the modules with an adequate margin.
Table 7: Summary of primary Tx/Rx antenna RF interface (ANT1) requirements
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 36 of 163
C1-Public
Item
Requirement
Remark
Impedance
50 nominal characteristic
impedance
The impedance of the antenna RF connection must match the 50
impedance of the ANT2 port.
Frequency
Range
See the LARA-R2 series data
sheet [1]
The required frequency range of the antennas connected to the ANT2 port
depends on the operating bands of the used cellular module and the used
mobile network.
Return Loss
S11 < -10 dB (VSWR < 2:1)
recommended
S11 < -6 dB (VSWR < 3:1)
acceptable
The Return loss or the S11, as the VSWR, refers to the amount of reflected
power, measuring how well the antenna RF connection matches the 50
characteristic impedance of the ANT2 port.
The impedance of the antenna termination must match as much as possible
the 50 nominal impedance of the ANT2 port over the operating frequency
range, reducing as much as possible the amount of reflected power.
Efficiency
> -1.5 dB ( > 70% ) recommended
> -3.0 dB ( > 50% ) acceptable
The radiation efficiency is the ratio of the radiated power to the power
delivered to antenna input: the efficiency is a measure of how well an antenna
receives or transmits.
The radiation efficiency of the antenna connected to the ANT2 port needs to
be enough high over the operating frequency range to comply with the OverThe-Air (OTA) radiated performance requirements, as the TIS, specified by
applicable related certification schemes.
Table 8: Summary of secondary Rx antenna RF interface (ANT2) requirements
Item
Requirement
Remark
Efficiency
imbalance
< 0.5 dB recommended
< 1.0 dB acceptable
The radiation efficiency imbalance is the ratio of the primary (ANT1) antenna
efficiency to the secondary (ANT2) antenna efficiency: the efficiency
imbalance is a measure of how much better an antenna receives or transmits
compared to the other antenna.
The radiation efficiency of the secondary antenna needs to be roughly the
same of the radiation efficiency of the primary antenna for good RF
performance.
Envelope
Correlation
Coefficient
< 0.4 recommended
< 0.5 acceptable
The Envelope Correlation Coefficient (ECC) between the primary (ANT1) and
the secondary (ANT2) antennas is an indicator of the 3D radiation pattern
similarity between the two antennas: low ECC arises from antenna patterns
with radiation lobes in different directions.
The ECC between primary and secondary antennas needs to be sufficiently
low to comply with radiated performance requirements specified by the
related certification schemes.
Isolation
> 15 dB recommended
> 10 dB acceptable
The antenna to antenna isolation is the loss between the primary (ANT1) and
the secondary (ANT2) antennas: high isolation arises from weakly coupled
antennas. The isolation between primary and secondary antenna needs to be
high for good RF performance.
Table 9: Summary of the primary (ANT1) and secondary (ANT2) antennas relationship requirements
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 37 of 163
C1-Public
1.7.2 Antenna detection interface (ANT_DET)
The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital
Converter (ADC) provided to sense the antenna presence.
The antenna detection function provided by the ANT_DET pin is an optional feature that can be
implemented if the application requires it. The antenna detection is forced by the +UANTR AT
command. See the u-blox AT commands manual [2] for more details on this feature.
The ANT_DET pin generates a DC current (for detailed characteristics, see the LARA-R2 series data
sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna
connector provided on the application board to GND. The requirements to achieve antenna detection
functionality are the following:
• an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
• an antenna detection circuit must be implemented on the application board
See section 2.4.2 for the antenna detection circuit on the application board and the diagnostic circuit
on the antenna assembly design-in guidelines.
1.8 SIM interface
1.8.1 SIM card interface
LARA-R2 series modules provide a high-speed SIM/ME interface, including automatic detection and
configuration of the voltage required by the connected SIM card or chip.
Both 1.8 V and 3 V SIM types are supported: activation and deactivation with an automatic voltage
switch from 1.8 V to 3 V is implemented, according to the ISO-IEC 7816-3 specifications. The VSIM
supply output pin provides internal short circuit protection to limit the start-up current and protect
the device in short circuit situations.
The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate
selection, according to the values determined by the SIM Card.
1.8.2 SIM card detection interface (SIM_DET)
The GPIO5 pin is configured by default to detect the external SIM card mechanical / physical presence.
The pin is configured as input, and it can sense SIM card presence as intended to be properly
connected to the mechanical switch of a SIM card holder as described in section 2.5:
• Low logic level at GPIO5 input pin is recognized as SIM card not present
• High logic level at GPIO5 input pin is recognized as SIM card present
The SIM card detection function provided by the GPIO5 pin is an optional feature that can be
implemented / used or not according to the application requirements: an Unsolicited Result Code
(URC) is generated each time that there is a change of status (for more details, see the u-blox AT
commands manual [2], +UGPIOC, +CIND, +CMER).
The optional function “SIM card hot insertion/removal” can be additionally configured on the GPIO5
pin by the specific AT command (see the u-blox AT commands manual [2], +UDCONF=50), in order to
enable / disable the SIM interface upon detection of the external SIM card physical insertion / removal.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 38 of 163
C1-Public
1.9 Data communication interfaces
LARA-R2 series modules provide the following serial communication interfaces:
• Main UART interface: Universal Asynchronous Receiver/Transmitter serial interface available for
the communication with a host application processor (AT commands, data communication, FW
update by means of FOAT), for FW update by means of the u-blox EasyFlash tool and for
diagnostics (see section 1.9.1).
• Auxiliary UART interface: Universal Asynchronous Receiver/Transmitter serial interface available
for AT commands communication with a host application processor, and for diagnostics (see
section 1.9.2).
• USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with
a host application processor (AT commands, data communication, FW update by means of the
FOAT feature), for FW update by means of the u-blox EasyFlash tool and for diagnostics (see
section 1.9.3).
• HSIC interface: High-Speed Inter-Chip USB compliant interface available for the communication
with a host application processor (AT commands, data communication, FW update by means of
the FOAT feature), for FW update by means of the u-blox EasyFlash tool and for diagnostics (see
section 1.9.4).
• DDC interface: I2C bus compatible interface available for the communication with u-blox GNSS
positioning chips or modules and with external I2C devices as an audio codec (see section 1.9.5).
• SDIO interface: Secure Digital Input Output interface available for the communication with
compatible u-blox short range radio communication Wi-Fi modules (see section 1.9.6).
1.9.1 Main UART interface
1.9.1.1 UART features
The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the
LARA-R2 series modules, supporting:
• AT command mode
11
• Data mode and Online command mode
11
• Multiplexer protocol functionality (see 1.9.1.5)
• FW upgrades by means of the FOAT feature (see 1.14.13 and the FW update application note [23])
• FW upgrades by means of the u-blox EasyFlash tool (see the FW update application note [23])
• Trace log capture (diagnostic purposes)
The UART interface provides RS-232 functionality conforming to ITU-T V.24 Recommendation [5],
with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF
state (for detailed electrical characteristics, see the LARA-R2 series data sheet [1]), providing:
• data lines (RXD as output, TXD as input),
• hardware flow control lines (CTS as output, RTS as input),
• modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output).
The modules are designed to operate as cellular modems, i.e. as the data circuit-terminating
equipment (DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor
connected to the module through the UART interface represents the data terminal equipment (DTE).
☞ UART signal names of the modules conform to the ITU-T V.24 [5]: e.g. TXD line represents data
transmitted by the DTE (host processor output) and received by the DCE (module input).
11
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 39 of 163
C1-Public
LARA-R2 series modules’ UART interface is configured by default in AT command mode: the module
waits for AT command instructions and interprets all the characters received as commands to
execute.
All the functionalities supported by LARA-R2 series modules can be set and configured by AT
commands:
• AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]
• u-blox AT commands (for the complete list and syntax, see the u-blox AT commands manual [2])
All flow control handshakes are supported by the UART interface and can be set by appropriate AT
commands (see u-blox AT commands manual [2], &K, +IFC, \Q AT commands): hardware, software, or
none flow control.
☞ Hardware flow control is enabled by default.
The one-shot autobauding is supported: the automatic baud rate detection is performed only once, at
module start-up. After the detection, the module works at the detected baud rate and the baud rate
can only be changed by an AT command (see the u-blox AT commands manual [2], +IPR command).
☞ One-shot automatic baud rate recognition (autobauding) is enabled by default.
The following baud rates can be configured by AT command (see u-blox AT commands manual [2],
+IPR):
• 9,600 bit/s
• 19,200 bit/s
• 38,400 bit/s
• 57,600 bit/s
• 115,200 bit/s – this is the default value when one-shot autobauding is disabled
• 230,400 bit/s
• 460,800 bit/s
• 921,600 bit/s
• 3,000,000 bit/s
• 3,250,000 bit/s
• 6,000,000 bit/s
• 6,500,000 bit/s
☞ Baud rates higher than 460,800 bit/s cannot be automatically detected by LARA-R2 series
modules.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 40 of 163
C1-Public
The modules support one-shot automatic frame recognition in conjunction with one-shot
autobauding. The following frame formats can be configured by an AT command (see the u-blox AT
commands manual [2], +ICF):
• 8N1 (8 data bits, no parity, 1 stop bit), default frame configuration with a fixed baud rate, see
Figure 18
• 8E1 (8 data bits, even parity, 1 stop bit)
• 8O1 (8 data bits, odd parity, 1 stop bit)
• 8N2 (8 data bits, no parity, 2 stop bits)
• 7E1 (7 data bits, even parity, 1 stop bit)
• 7O1 (7 data bits, odd parity, 1 stop bit)
D0 D1 D2 D3 D4 D5 D6 D7
Start of 1-Byte
transfer
Start Bit
(Always 0)
Possible Start of
next transfer
Stop Bit
(Always 1)
t
bit
= 1/(Baudrate)
Normal Transfer, 8N1
Figure 18: Description of the UART 8N1 frame format (8 data bits, no parity, 1 stop bit)
1.9.1.2 UART AT interface configuration
The UART interface of LARA-R2 series modules is available as the AT command interface with the
default configuration described in Table 10 (for more details and information about further settings,
see the u-blox AT commands manual [2]).
Interface
AT Settings
Comments
UART interface
AT interface: enabled
AT command interface is enabled by default on the UART physical interface
AT+IPR=0
One-shot autobauding enabled by default on the modules
AT+ICF=3,1
8N1 frame format enabled by default
AT&K3
HW flow control enabled by default
AT&S1
DSR line (Circuit 107 in ITU-T V.24) set ON in data mode12 and set OFF in
command mode12
AT&D1
Upon an ON-to-OFF transition of the DTR line (Circuit 108/2 in ITU-T V.24), the
module (DCE) enters online command mode12 and issues an OK result code
AT&C1
DCD line (Circuit 109 in ITU-T V.24) changes in accordance with the Carrier
detect status; ON if the Carrier is detected, OFF otherwise
MUX protocol: disabled
Multiplexing mode is disabled by default and it can be enabled by the AT+CMUX
command. For more details, see the Mux implementation application note [21].
The following virtual channels are defined:
• Channel 0: control channel
• Channel 1 – 5: AT commands / data connection
• Channel 6: GNSS tunneling13
Table 10: Default UART AT interface configuration
12
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode
13
Not supported by LARA-R204-02B and LARA-R211-02B-00 product versions.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 41 of 163
C1-Public
1.9.1.3 UART signal behavior
At the module switch-on, before the UART interface initialization (as described in the power-on
sequence reported in Figure 14), each pin is first tri-stated and then is set to its related internal reset
state14. At the end of the boot sequence, the UART interface is initialized, the module is by default in
active mode, and the UART interface is enabled as an AT commands interface.
The configuration and the behavior of the UART signals after the boot sequence are described below.
See section 1.4 for the definition and description of the module operating modes referred to in this
section.
RXD signal behavior
The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization.
The module holds RXD in the OFF state until the module does not transmit any data.
TXD signal behavior
The module data input line (TXD) is set by default to the OFF state (high level) at UART initialization.
The TXD line is then held by the module in the OFF state if the line is not activated by the DTE: an
active pull-up is enabled inside the module on the TXD input.
CTS signal behavior
The module hardware flow control output (CTS line) is set to the ON state (low level) at UART
initialization.
If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART
interface is enabled (data can be sent and received). The module drives the CTS line to the ON state
or to the OFF state when it is either able or not able to accept data from the DTE over the UART
(see 1.9.1.4 for more details).
☞ If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean
that the module is in low power idle mode, but only that the UART is not enabled, as the module
could be forced to stay in active mode for other activities, e.g. related to the network or related to
other interfaces.
☞ When the multiplexer protocol is active, the CTS line state is mapped to FCon / FCoff MUX
command for flow control issues outside the power saving configuration while the physical CTS
line is still used as a power state indicator. For more details, see Mux implementation application
note [21].
The CTS hardware flow control setting can be changed by using AT commands (for more details, see
the u-blox AT commands manual [2], AT&K, AT\Q, AT+IFC, AT+UCTS AT command).
☞ When the power saving configuration is enabled by the AT+UPSV command and the hardware
flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the
first character sent when the module is in low power idle mode will not be a valid communication
character (see section 1.9.1.4 and in particular the sub-section “Wake-up via data reception” for
further details).
14
Refer to the pin description table in the LARA-R2 series data sheet [1].
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 42 of 163
C1-Public
RTS signal behavior
The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART
initialization. The module then holds the RTS line in the OFF state if the line is not activated by the
DTE: an active pull-up is enabled inside the module on the RTS input.
If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect
permission from the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any ongoing data transmission from the module is interrupted until the subsequent RTS line changes to the
ON state.
☞ The DTE must still be able to accept a certain number of characters after the RTS line is set to the
OFF state: the module guarantees the transmission interruption within two characters from RTS
state change.
Module behavior according to RTS hardware flow control status can be configured by using AT
commands (for more details, see the u-blox AT commands manual [2], AT&K, AT\Q, AT+IFC command
descriptions).
If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage
the power saving configuration (for more details, see section 1.9.1.4 and the u-blox AT commands
manual [2], AT+UPSV):
• When an OFF-to-ON transition occurs on the RTS input, the UART is enabled and the module is
forced to active mode. After ~20 ms, the switch is completed and data can be received without
loss. The module cannot enter low power idle mode and the UART is enabled as long as the RTS is
in the ON state.
• If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power
mode) and the module automatically enters low power idle mode whenever possible.
DSR signal behavior
If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high
level) at UART initialization. The DSR line is then set to the OFF state when the module is in command
mode15 or in online command mode15 and is set to the ON state when the module is in data mode15.
If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART
initialization and is then always held in the ON state.
DTR signal behavior
The DTR module input line is set by default to the OFF state (high level) at UART initialization. The
module then holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up
is enabled inside the module on the DTR input.
Module behavior according to DTR status can be changed by AT command (for more details, see the
u-blox AT commands manual [2], AT&D command description).
If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving
configuration (for more details, see section 1.9.1.4 and the u-blox AT commands manual [2],
AT+UPSV command):
• When an OFF-to-ON transition occurs on the DTR input, the UART is enabled and the module is
forced to active mode. After ~20 ms, the switch is completed and data can be received without
15
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 43 of 163
C1-Public
loss. The module cannot enter low power idle mode and the UART is enabled as long as the DTR is
in the ON state
• If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power
mode) and the module automatically enters low power idle mode whenever possible
DCD signal behavior
If AT&C1 is set, as it is by default, the DCD module output line is set by default to the OFF state (high
level) at UART initialization. The module then sets the DCD line according to the carrier detect status:
ON if the carrier is detected, OFF otherwise.
For voice calls, DCD is set to the ON state when the call is established.
For data calls, there are the following scenarios regarding the DCD signal behavior:
• Packet Switched Data call: Before activating the PPP protocol (data mode) a dial-up application
must provide the ATD*99***<context_number># to the module: with this command the module
switches from command mode to data mode and can accept PPP packets. The module sets the
DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The
DCD ON is not related to the context activation but with the data mode.
• Circuit Switched Data call: To establish a data call, the DTE can send the ATD<number>
command to the module which sets an outgoing data call to a remote modem (or another data
module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol).
When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT
<communication baudrate> string is returned by the module. At this stage, the DTE can send
characters through the serial line to the data module which sends them through the network to
the remote DCE attached to a remote DTE
☞ The DCD is set to ON during the execution of the +CMGS, +CMGW, +USOWR, +USODL AT
commands requiring input data from the DTE: the DCD line is set to the ON state as soon as the
switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as
soon as the input mode is interrupted or completed (for more details see the u-blox AT commands
manual [2]).
☞ The DCD line is kept in the ON state, even during the online command mode
16
, to indicate that the
data call is still established even if suspended, while if the module enters command mode16, the
DSR line is set to the OFF state. For more details, see DSR signal behavior description.
☞ For scenarios when the DCD line setting is requested for different reasons (e.g. SMS texting
during online command mode16), the DCD line changes to guarantee the correct behavior for all
the scenarios. For example, for SMS texting in online command mode16, if the data call is released,
DCD is kept ON until the SMS command execution is completed (even if the data call release would
request DCD set OFF).
If AT&C0 is set, the DCD module output line is set by default to the ON state (low level) at UART
initialization and is then always held in the ON state.
16
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 44 of 163
C1-Public
RI signal behavior
The RI module output line is set by default to the OFF state (high level) at UART initialization. Then,
during an incoming call, the RI line is switched from the OFF state to the ON state with a 4:1 duty cycle
and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 19), until the DTE attached to the module sends
the ATA string and the module accepts the incoming data call. The RING string sent by the module
(DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the
ON state.
Figure 19: RI behavior during an incoming call
The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for
1 s (see Figure 20), if the feature is enabled by the AT+CNMI command (see the u-blox AT commands
manual [2]).
Figure 20: RI behavior at SMS arrival
This behavior allows the DTE to stay in power saving mode until the DCE related event requests
service.
For SMS arrival, if several events occur coincidently or in quick succession, each event independently
triggers the RI line, although the line will not be deactivated between each event. As a result, the RI
line may stay at ON for more than 1 s.
If an incoming call is answered within less than 1 s (with ATA or if auto-answering is set to ATS0=1),
then the RI line is set to OFF earlier.
As a result:
☞ RI line monitoring cannot be used by the DTE to determine the number of received SMSes.
☞ For multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate
the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with
proper commands.
The RI line can additionally notify all the URCs and all the incoming data in PPP and Direct Link
connections, if the feature is enabled by the AT+URING command (for more details, see the u-blox AT
commands manual [2]): the RI line is asserted when one of the configured events occur and it remains
asserted for 1 s unless another configured event will happen, with the same behavior described in
Figure 20.
1s
time [s]
151050
RI ON
RI OFF
Call incomes
1s
time [s]
151050
RI ON
RI OFF
Call incomes
RI OFF
RI ON
Call incomes
1 s
Time [s]
SMS arrives
time [s]
0
RI ON
RI OFF
1s
SMS
time [s]
0
RI ON
RI OFF
1s
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 45 of 163
C1-Public
1.9.1.4 UART and power-saving
The power saving configuration is controlled by the AT+UPSV command (for the complete
description, see the u-blox AT commands manual [2]). When power saving is enabled, the module
automatically enters low power idle mode whenever possible, and otherwise the active mode is
maintained by the module (see section 1.4 for the definition and description of module operating
modes referred to in this section).
The AT+UPSV command configures both the module power saving and also the UART behavior in
relation to power saving. The conditions for the module entering low power idle mode also depend on
the UART power saving configuration, as the module does not enter the low power idle mode
according to any required activity related to the network (within or outside an active call) or any other
required concurrent activity related to the functions and interfaces of the module, including the UART
interface.
Three different power saving configurations can be set by the AT+UPSV command:
• AT+UPSV=0, power saving disabled (default configuration)
• AT+UPSV=1, power saving enabled cyclically
• AT+UPSV=2, power saving enabled and controlled by the UART RTS input line
• AT+UPSV=3, power saving enabled and controlled by the UART DTR input line
The various power saving configurations that can be set by the +UPSV AT command are described in
detail in the following subsections. Table 11 summarizes the UART interface communication process
in the various power saving configurations, in relation with HW flow control settings and RTS input
line status. For more details on the +UPSV AT command description, refer to the u-blox AT commands
manual [2].
AT+UPSV
HW flow control
RTS line
DTR line
Communication during idle mode and wake up
0
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE are correctly received by the module.
Data sent by the module is correctly received by the DTE.
0
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE are correctly received by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
0
Disabled (AT&K0)
ON or OFF
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
1
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE is buffered by the DTE and will be correctly received
by the module when it is ready to receive data (when UART is enabled).
Data sent by the module is correctly received by the DTE.
1
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE is buffered by the DTE and will be correctly received
by the module when it is ready to receive data (when UART is enabled).
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be
ON).
1
Disabled (AT&K0)
ON or OFF
ON or OFF
The first character sent by the DTE is lost by the module, but after ~20 ms
the UART and the module are woken up: recognition of subsequent
characters is guaranteed only after the UART / module complete wake-up
(after ~20 ms).
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise the data is lost.
2
Enabled (AT&K3)
ON or OFF
ON or OFF
Not Applicable: HW flow control cannot be enabled with AT+UPSV=2.
2
Disabled (AT&K0)
ON
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 46 of 163
C1-Public
AT+UPSV
HW flow control
RTS line
DTR line
Communication during idle mode and wake up
2
Disabled (AT&K0)
OFF
ON or OFF
Data sent by the DTE is lost by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data is lost.
3
Enabled (AT&K3)
ON
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
ON
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is correctly received by the DTE.
3
Enabled (AT&K3)
OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Enabled (AT&K3)
OFF
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e. RTS line will be ON).
3
Disabled (AT&K0)
ON or OFF
ON
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data are lost.
3
Disabled (AT&K0)
ON or OFF
OFF
Data sent by the DTE is lost by the module.
Data sent by the module is correctly received by the DTE if it is ready to
receive data, otherwise data are lost.
Table 11: UART and power-saving summary
AT+UPSV=0: power saving disabled, fixed active mode
The module does not enter low power idle mode and the UART interface is enabled (data can be sent
and received): the CTS line is always held in the ON state after UART initialization. This is the default
configuration.
AT+UPSV=1: power saving enabled, cyclic idle/active mode
When the AT+UPSV=1 command is issued by the DTE, the UART will be normally disabled, and then
periodically or upon necessity enabled as following:
• During the periodic UART wake-up to receive or send data, also according to the module wake up
for the paging reception (see section 1.5.1.5) or other activities
• If the module needs to transmit some data (e.g. URC), the UART is temporarily enabled to send
data
• If the DTE sends data with HW flow control disabled, the first character sent causes the UART and
module wake-up after ~20 ms: recognition of subsequent characters is guaranteed only after the
complete wake-up (see the following subsection “wake up via data reception”)
The module automatically enters the low power idle mode whenever possible, but it wakes up to active
mode according to the UART periodic wake-up so that the module cyclically enters the low power idle
mode and the active mode. Additionally, the module wakes up to active mode according to any
required activity related to the network (e.g. for the periodic paging reception described in section
1.5.1.5, or for any other required RF Tx / Rx) or any other required activity related to module
functions / interfaces (including the UART itself).
The time period of the UART enable/disable cycle is configured differently when the module is
registered with a 2G network compared to when the module is registered with a 3G or LTE network:
• 2G: UART is enabled synchronously with some paging receptions: UART is enabled concurrently
to a paging reception, and then, as data has not been received or sent, UART is disabled until the
first paging reception that occurs after a timeout of 2.0 s, and so the interface is then enabled
again
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 47 of 163
C1-Public
• 3G or LTE: UART is asynchronously enabled to paging receptions, as UART is enabled for ~20 ms,
and then, if data are not received or sent, UART is disabled for 2.5 s, and afterwards the interface
is enabled again
• Not registered: when a module is not registered with a network, UART is enabled for ~20 ms, and
then, if data has not been received or sent, UART is disabled for 2.5 s, and afterwards the interface
is enabled again
When the UART interface is enabled, data can be received. When a character is received, it forces the
UART interface to stay enabled for a longer time and it forces the module to stay in the active mode
for a longer time, according to the timeout configured by the second parameter of the +UPSV AT
command. The timeout can be set from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65,000
2G-frames (i.e. 65,000 x 4.615 ms = 300 s). Default value is 2,000 2G-frames
(i.e. 2,000 x 4.615 ms = 9.2 s). Every subsequent character received during the active mode, resets
and restarts the timer; hence the active mode duration can be extended indefinitely.
The CTS output line is driven to the ON or OFF state when the module is either able or not able to
accept data from the DTE over the UART: Figure 21 illustrates the CTS output line toggling due to
paging reception and data received over the UART, with the AT+UPSV=1 configuration.
time [s]
~9.2 s (default)
Data input
CTS ON
CTS OFF
Figure 21: CTS output indicates when module’s UART is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level)
AT+UPSV=2: power saving enabled and controlled by the RTS line
This configuration can only be enabled with the module hardware flow control disabled (i.e. AT&K0).
The UART interface is disabled after the DTE sets the RTS line to OFF.
Afterwards, UART is enabled again, and the module does not enter low power idle mode, as following:
• If an OFF-to-ON transition occurs on the RTS input, this causes the UART / module wake-up after
~20 ms: recognition of subsequent characters is guaranteed only after the complete wake-up, and
the UART is kept enabled as long as the RTS input line is set to ON.
• If the module needs to transmit some data (e.g. URC), UART is temporarily enabled to send data
The module automatically enters the low power idle mode whenever possible but it wakes up to active
mode according to any required activity related to the network (e.g. for the periodic paging reception
described in section 1.5.1.5, or for any other required RF transmission / reception) or any other
required activity related to the module functions / interfaces (including the UART itself).
AT+UPSV=3: power saving enabled and controlled by the DTR line
The UART interface is disabled after the DTE sets the DTR line to OFF.
Afterwards, the UART is enabled again, and the module does not enter low power idle mode, as
following:
• If an OFF-to-ON transition occurs on the DTR input, this causes the UART / module wake-up after
~20 ms: recognition of subsequent characters is guaranteed only after the complete wake-up, and
the UART is kept enabled as long as the DTR input line is set to ON.
• If the module needs to transmit data (e.g. URC), the UART is temporarily enabled to send data.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 48 of 163
C1-Public
The module automatically enters the low power idle mode whenever possible, but it wakes up to active
mode according to any required activity related to the network (e.g. for the periodic paging reception
described in section 1.5.1.5, or for any other required RF signal transmission or reception) or any other
required activity related to the functions / interfaces of the module.
The AT+UPSV=3 configuration can be enabled regardless of the flow control setting on the UART. In
particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on the UART during this
configuration. In both cases, with the AT+UPSV=3 configuration, the CTS line indicates when the
module is either able or not able to accept data from the DTE over the UART.
When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to
control the module behavior according to the AT&D command configuration (see the u-blox AT
commands manual [2]).
Wake-up via data reception
The UART wake-up via data reception consists of a special configuration of the module TXD input line
that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In
particular, the UART is enabled and the module switches from the low power idle mode to active mode
within ~20 ms from the first character received: this is the system “wake-up time”.
As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake up
character) is not a valid communication character, even if the wake up via data reception
configuration is active, because it cannot be recognized, and the recognition of the subsequent
characters is guaranteed only after the complete system wake-up (i.e. after ~20 ms).
The UART wake-up via data reception configuration is active in the following cases:
• AT+UPSV=1 is set with HW flow control disabled
Figure 22 and Figure 23 show examples of common scenarios and timing constraints:
• AT+UPSV=1 power saving configuration is active and the timeout from last data received to idle
mode start is set to 2000 frames (AT+UPSV=1,2000)
• Hardware flow control is disabled
Figure 22 shows the case where the UART module is disabled and only a wake-up is forced. In this
scenario, the only character sent by the DTE is the wake-up character; as a consequence, the DCE
module UART is disabled when the timeout from last data received expires (2000 frames without data
reception, as the default case).
Wake up character
Not recognized by DCE
OFF
ON
DCE UART is enabled for 2000 GSM frames (~9.2 s)
time
Wake up time: ~20 ms
time
TXD input
UART
OFF
ON
Figure 22: Wake-up via data reception without further communication
Figure 23 shows the case where in addition to the wake-up character, further (valid) characters are
sent. The wake-up character wakes up the UART module. The other characters must be sent after
the “wake up time” of ~20 ms. If this condition is satisfied, the module (DCE) recognizes characters.
The module will disable the UART after 2000 GSM frames from the latest data reception.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 49 of 163
C1-Public
Wake up character
Not recognized by DCE
Valid characters
Recognized by DCE
DCE UART is enabled for 2000 GSM frames (~9.2s)
after the last data received
time
Wake up time: ~20 ms
time
OFF
ON
TXD input
UART
OFF
ON
Figure 23: Wake-up via data reception with further communication
☞ The “wake-up via data reception” feature cannot be disabled.
☞ In command mode
17
, with “wake-up via data reception” enabled and autobauding enabled, the DTE
should always send a dummy character to the module before the “AT” prefix set at the beginning
of each command line: the first dummy character is ignored if the module is in active mode, or it
represents the wake-up character if the module is in low power idle mode.
☞ In command mode
17
, with “wake-up via data reception” enabled and autobauding disabled, the
DTE should always send a dummy “AT” to the module before each command line: the first dummy
“AT” is not ignored if the module is in active mode (i.e. the module replies “OK”), or it represents
the wake-up character if the module is in low power idle mode (i.e. the module does not reply).
Additional considerations
If the USB is connected and not suspended, the module is kept ready to communicate over USB
regardless of the AT+UPSV settings, which have effect instead on the UART behavior, as they
configure the UART power saving, so that UART is enabled / disabled according to the AT+UPSV
settings.
To set the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 configuration over the USB interface, the
autobauding must be previously disabled on the UART by the +IPR AT command over the used USB
AT interface, and this +IPR AT command configuration must be saved in the module’s non-volatile
memory (see the u-blox AT commands manual [2]). Then after the subsequent module re-boot,
AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 can be issued over the used AT interface (the USB): all the
AT profiles are updated accordingly.
1.9.1.5 Multiplexer protocol (3GPP TS 27.010)
LARA-R2 series modules include multiplexer functionality on the UART physical link as per 3GPP TS
27.010 [8].
This is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and
the application processor (DTE) and allows a number of simultaneous sessions over the used physical
link (UART): the user can concurrently use AT interface on one MUX channel and data communication
on another MUX channel.
These virtual channels are defined (for more details, see Mux implementation application note [21]):
• Channel 0: Multiplexer control
• Channels 1 – 5: AT commands / data connection
• Channel 6: GNSS data tunneling
☞ GNSS data tunneling is not supported by LARA-R204-02B and LARA-R211-02B-00 product
versions.
17
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 50 of 163
C1-Public
1.9.2 Auxiliary UART interface
☞ The auxiliary UART interface is not supported by the "02B", "62B" and "82B" product versions of
the LARA-R202, LARA-R203, LARA-R204, LARA-R220, LARA-R280, and LARA-R281 modules,
and by the "02B-00", "02B-01" and "02B-02" product versions of the LARA-R211 modules .
LARA-R2 series modules include a 3-wire unbalanced auxiliary secondary Universal Asynchronous
Receiver/Transmitter serial interface (AUX UART), supporting:
• AT command mode
18
• Trace log capture (diagnostic purposes)
The auxiliary secondary UART interface is disabled by default, and it can be enabled by dedicated AT
command (see the u-blox AT commands manual [2], +USIO) as alternative function of the DDC (I2C)
interface’ pins, in mutually exclusive way with the DDC (I2C) interface.
AUX UART features are:
• 3-wire serial port with RS-232 functionality conforming to ITU-T V.24 recommendation [5], with
CMOS compatible signal levels (0 V for low data bit / ON state, 1.8 V for high data bit / OFF state)
• Data lines (SCL pin as AUX UART data output, SDA pin as AUX UART data input)
• Software flow control, or none flow control (default value) are supported
• The following baud rates are supported: 9’600, 19’200, 38’400, 57’600, 115’200 (default baud rate
when autobauding is disabled), 230’400, 460’800, 921’600, 3’000’000, 3’250’000, 6’000’000 and
6’500’000 bit/s
• One-shot autobauding is supported and it is enabled by default: automatic baud rate detection is
performed only once, at module start up. After the detection, the module works at the fixed baud
rate (the detected one) and the baud rate can only be changed via AT command (see the u-blox AT
commands manual [2], +IPR).
• The following frame formats are supported: 8N2, 8N1 (default format when automatic frame
recognition is disabled), 8E1, 8O1, 7E1 and 7O1.
• One-shot automatic frame recognition is supported and it is enabled by default in conjunction with
automatic baud rate detection (autobauding): the detection is performed only once, at module
start up. After the detection, the module works at the detected frame format and it can only be
changed via AT command (see u-blox AT commands manual [2], +ICF).
• The Data Terminal Ready physical line is not available, but the logical Data Terminal Ready line is
always to ON state
CSD, PSD, and the multiplexer protocol is not supported over the auxiliary secondary UART.
The auxiliary secondary UART serial interface can be conveniently configured through AT commands:
see the u-blox AT commands manual [2] (+IPR, +ICF, +IFC, &K, \Q, +UPSV, +USIO AT commands).
18
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 51 of 163
C1-Public
1.9.3 USB interface
1.9.3.1 USB features
LARA-R2 series modules include a High-Speed USB 2.0 compliant interface with a 480 Mbit/s
maximum data rate, representing the main interface for transferring high speed data with a host
application processor, supporting:
• AT command mode
19
• Data mode and Online command mode
19
• FW upgrades by means of the FOAT feature (see 1.14.13 and the FW update application note [23])
• FW upgrades by means of the u-blox EasyFlash tool (see the FW update application note [23])
• Trace log capture (diagnostic purposes)
The module itself acts as a USB device and can be connected to a USB host such as a Personal
Computer or an embedded application microprocessor equipped with compatible drivers.
The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial
Bus Revision 2.0 specification [9], while the VUSB_DET input pin senses the VBUS USB supply
presence (nominally 5 V at the source) to detect the host connection and enable the interface.
The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input
(see the LARA-R2 series data sheet [1]). Neither the USB interface, nor the whole module is supplied
by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs only a few
microamperes.
The USB interface is controlled and operated with:
• AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]
• u-blox AT commands (for the complete list and syntax, see the u-blox AT commands manual [2])
The USB interface of LARA-R2 series modules, according to the configured USB profile, can provide
several USB functions with various capabilities and purposes, such as:
• CDC-ACM for AT commands and data communication
• CDC-ACM for GNSS tunneling
• CDC-ACM for SAP (SIM Access Profile)
• CDC-ACM for Diagnostic logs
• CDC-NCM for Ethernet-over-USB
☞ CDC-ACM for GNSS tunneling is not supported by the LARA-R204-02B and LARA-R211-02B-00
product versions.
☞ CDC-ACM for SAP and CDC-NCM for Ethernet-over-USB are not supported by the "02B", "62B",
"82B", and "03B" versions.
☞ The RI virtual signal is not supported over USB CDC-ACM by the "02B", "62B", "82B", "03B" versions
The USB profile of LARA-R2 series modules identifies itself by its VID (Vendor ID) and PID (Product ID)
combination, included in the USB device descriptor according to the USB 2.0 specification [9].
If the USB is connected to the host before the module is switched on, or if the module is reset
(rebooted) with the USB connected to the host, the VID and PID are automatically updated during the
boot of the module. First, VID and PID are the following:
• VID = 0x8087
• PID = 0x0716
19
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 52 of 163
C1-Public
This VID and PID combination identifies a USB profile where no USB function described above is
available: AT commands must not be sent to the module over the USB profile identified by this VID
and PID combination.
Then, after a time period (which depends on the host / device enumeration timings), the VID and PID
are updated to the ones related to the default USB profile providing the following set of USB functions:
• 6 CDC-ACM modem COM ports enumerated as follows:
o USB1: AT and data
o USB2: AT and data
o USB3: AT and data
o USB4: GNSS tunneling
o USB5: SAP (SIM Access Profile)
o USB6: Primary Log (diagnostic purpose)
VID and PID of this USB profile with the set of functions described above (6 CDC-ACM) are:
• VID = 0x1546
• PID = 0x110A
Figure 24 summarizes the USB endpoints available with the default USB profile.
Default profile configuration
Interface 0 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 1 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function AT and Data
Interface 2 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 3 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function AT and Data
Interface 4 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 5 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function AT and Data
Interface 6 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 7 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function GNSS tunneling
Interface 8 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 9 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function SAP
Interface 10 Abstract Control Model
EndPoint Transfer: Interrupt
Interface 11 Data
EndPoint Transfer: Bulk
EndPoint Transfer: Bulk
Function Primary Log
Figure 24: LARA-R2 series USB Endpoints summary for the default USB profile configuration
1.9.3.2 USB in Windows
USB drivers are provided for Windows operating system platforms and should be properly
installed / enabled by following the step-by-step instructions available in the EVK-R2 user guide [3] or
in the Windows Embedded OS USB driver installation application note [4].
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 53 of 163
C1-Public
USB drivers are available for the following operating system platforms:
• Windows 7
• Windows 8
• Windows 8.1
• Windows 10
• Windows Embedded CE 6.0
• Windows Embedded Compact 7
• Windows Embedded Compact 2013
• Windows 10 IoT
The module firmware can be upgraded over the USB interface by means of the FOAT feature, or using
the u-blox EasyFlash tool (for more details, see the FW update application note [23].
1.9.3.3 USB in Linux/Android
It is not required to install a specific driver for each Linux-based or Android-based operating system
(OS) to use the USB module interface, which is compatible with standard Linux/Android USB kernel
drivers.
The full capability and configuration of the USB module interface can be reported by running “lsusb -v”
or an equivalent command available in the host operating system when the module is connected.
1.9.3.4 USB and power saving
The modules automatically enter the USB suspended state when the device has observed no bus
traffic for a specific time period according to the USB 2.0 specifications [9]. In the suspended state,
the module maintains any USB internal status as device. In addition, the module enters the suspended
state when the hub port it is attached to is disabled. This is referred to as a USB selective suspend.
If the USB is suspended and a power saving configuration is enabled by the AT+UPSV command, the
module automatically enters the low power idle mode whenever possible, but it wakes up to active
mode according to any required activity related to the network (e.g. the periodic paging reception
described in section 1.5.1.5) or any other required activity related to the functions / interfaces of the
module.
The USB exits suspend mode when there is bus activity. If the USB is connected and not suspended,
the module is kept ready to communicate over USB regardless of the AT+UPSV settings, therefore
the AT+UPSV settings are overruled but they do have effect on the power saving configuration of the
other interfaces (see 1.9.1.4).
The modules are capable of USB remote wake-up signaling: i.e. it may request the host to exit suspend
mode or selective suspend by using electrical signaling to indicate remote wake-up, for example due
to an incoming call, URCs, data reception on a socket. The remote wake-up signaling notifies the host
that it should resume from its suspended mode, if necessary, and service the external event. Remote
wake-up is accomplished using electrical signaling described in the USB 2.0 specifications [9].
For the module current consumption description with power saving enabled and USB suspended, or
with power saving disabled and USB not suspended, see sections 1.5.1.5, 1.5.1.6 and the LARA-R2
series data sheet [1].
The additional VUSB_DET input pin available on the LARA-R2 series modules provides the complete
bus detach functionality: the modules disable the USB interface when a low logic level is sensed after
a high-to-low logic level transition on the VUSB_DET input pin. This allows a further reduction of the
module current consumption, in particular as compared to the USB suspended status during
low-power idle mode with power saving enabled.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 54 of 163
C1-Public
1.9.4 HSIC interface
☞ The HSIC interface is not supported by the "02B", "62B", "82B", and "03B" product versions, except
for diagnostic purposes.
1.9.4.1 HSIC features
LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with a maximum
480 Mb/s data rate according to the High-Speed Inter-Chip USB Electrical Specification Version
1.0 [10] and the USB Specification Revision 2.0 [9]. The module itself acts as a device and can be
connected to any compatible host.
The HSIC interface provides:
• AT command mode
20
• Data mode and Online command mode
20
• FW upgrades by means of the FOAT feature (see 1.14.13 and the FW update application note [23])
• FW upgrades by means of the u-blox EasyFlash tool (see the FW update application note [23])
• Trace log capture (diagnostic purpose)
The HSIC interface consists of a bi-directional DDR data line (HSIC_DATA) for transmitting and
receiving data synchronously with the bi-directional strobe line (HSIC_STRB).
The modules also include the HOST_SELECT pin to select the module / host application processor
configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect
the HSIC interface.
The USB interface is controlled and operated with:
• AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]
• u-blox AT commands (for the complete list and syntax, see the u-blox AT commands manual [2])
1.9.5 DDC (I2C) interface
☞ Communication with u-blox GNSS receivers over the I2C bus compatible Display Data Channel
interface, AssistNow embedded GNSS positioning aiding, CellLocate® positioning through cellular
info, and custom functions over GPIOs for the integration with u-blox positioning chips / modules
are not supported by the LARA-R204-02B and LARA-R211-02B-00 product versions.
The SDA and SCL pins21 represent an I2C bus compatible Display Data Channel (DDC) interface
available for
• communication with u-blox GNSS chips / modules,
• communication with other external I2C devices as audio codecs.
The AT command interface is not available on the DDC (I2C) interface.
DDC (I2C) local device-mode operation is not supported: the LARA-R2 series module can act as the
I2C host that can communicate with more I2C local devices in accordance to the I2C bus
specifications [11].
The DDC (I2C) interface pins of the module, serial data (SDA) and serial clock (SCL), are open drain
outputs conforming to the I2C bus specifications [11].
20
See the u-blox AT commands manual [2] for the definition of the command mode, data mode, and online command mode.
21
SDA and SCL pins can be alternatively configured, in a mutually exclusive way, as auxiliary UART interface (AUX UART) on
LARA-R2 series modules, except the "02B", "62B" and "82B" versions of the LARA-R202, LARA-R203, LARA-R204, LARA-R220,
LARA-R280 and LARA-R281 modules, and the "02B-00", "02B-01" and "02B-02" versions of LARA-R211 modules.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 55 of 163
C1-Public
u-blox has implemented special features to ease the design effort required for the integration of a
u-blox cellular module with a u-blox GNSS receiver.
Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access
to the positioning receiver directly via the cellular module: it relays control messages to the GNSS
receiver via a dedicated DDC (I2C) interface. A second interface connected to the positioning receiver
is not necessary: AT commands via the UART or USB serial interface of the cellular module allow for
full control of the GNSS receiver from any host processor.
The modules feature embedded GNSS aiding, that is, a set of specific features developed by u-blox to
enhance GNSS performance, decreasing the Time-To-First-Fix (TTFF), thus allowing the calculation
of the position in a shorter time with higher accuracy.
These GNSS aiding types are available:
• Local aiding
• AssistNow Online
• AssistNow Offline
• AssistNow Autonomous
The embedded GNSS aiding features can be used only if the DDC (I2C) interface of the cellular module
is connected to the u-blox GNSS receivers.
The cellular modules provide additional custom functions over GPIO pins to improve the integration
with u-blox positioning chips and modules. GPIO pins can handle:
• GNSS receiver power-on/off: the “GNSS supply enable” function provided by GPIO2 improves the
positioning receiver power consumption. When the GNSS functionality is not required, the
positioning receiver can be completely switched off by the cellular module that is controlled by AT
commands.
• The wake-up from idle mode when the GNSS receiver is ready to send data: “GNSS Tx data ready”
function provided by GPIO3 improves the cellular module power consumption. When power saving
is enabled in the cellular module by the AT+UPSV command and the GNSS receiver does not send
data by the DDC (I2C) interface, the module automatically enters idle mode whenever possible.
With the “GNSS Tx data ready” function, the GNSS receiver can indicate to the cellular module
that it is ready to send data by the DDC (I2C) interface: the positioning receiver can wake up the
cellular module if it is in idle mode, so the cellular module does not lose the data sent by the GNSS
receiver even if power saving is enabled.
• The RTC synchronization signal to the GNSS receiver: “GNSS RTC sharing” function provided by
GPIO4 improves GNSS receiver performance, decreasing the Time-To-First-Fix (TTFF), and thus
allowing the calculation of the position in a shorter time with higher accuracy. When GPS local
aiding is enabled, the cellular module automatically uploads data such as position, time,
ephemeris, almanac, health and ionospheric parameters from the positioning receiver into its local
memory, and restores this to the GNSS receiver at the next power-up of the positioning receiver.
☞ The “GNSS RTC sharing” function is not supported by "02B", "62B", "82B", "03B" product versions.
☞ For more details regarding the handling of the DDC (I2C) interface, the GNSS aiding features and
the GNSS related functions over GPIOs, see section 1.12, the u-blox AT commands manual [2]
(+UGPS, +UGPRF, +UGPIOC AT commands) and the GNSS implementation application note [22].
☞ “GNSS Tx data ready” and “GNSS RTC sharing” functions are not supported by all u-blox GNSS
receivers HW or ROM/FW versions. See the GNSS implementation application note [22] or the
Hardware Integration Manual of the u-blox GNSS receivers for the supported features.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 56 of 163
C1-Public
As an additional improvement for the GNSS receiver performance, the V_BCKP supply output of the
cellular modules can be connected to the V_BCKP supply input pin of u-blox positioning chips and
modules to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of
the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled.
This enables the u-blox positioning receiver to recover from a power breakdown with either a hot start
or a warm start (depending on the duration of the GNSS receiver VCC outage) and to maintain the
configuration settings saved in the backup RAM.
1.9.6 SDIO interface
☞ The Secure Digital Input Output interface is not supported by the "02B", "62B", "82B", and "03B"
product versions.
LARA-R2 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1,
SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with an external u-blox short
range Wi-Fi module: the cellular module acts as an SDIO host controller which can communicate over
the SDIO bus with a compatible u-blox short range radio communication Wi-Fi module acting as an
SDIO device.
The SDIO interface is the only interface of LARA-R2 series modules dedicated for communication
between the u-blox cellular module and the u-blox short range Wi-Fi module.
The AT command interface is not available on the SDIO interface of the LARA-R2 series modules.
Combining a u-blox cellular module with a u-blox short range communication module gives designers
full access to the Wi-Fi module directly via the cellular module, so that a second interface connected
to the Wi-Fi module is not necessary. AT commands via the AT interfaces of the cellular module allow
for full control of the Wi-Fi module from any host processor, because Wi-Fi control messages are
relayed to the Wi-Fi module via the dedicated SDIO interface.
u-blox has implemented special features in the cellular modules to ease the design effort for the
integration of a u-blox cellular module with a u-blox short range Wi-Fi module to provide router
functionality.
Additional custom function over GPIO pins is designed to improve the integration with u-blox Wi-Fi
modules:
• Wi-Fi enable Switch-on / switch-off the Wi-Fi
☞ Wi-Fi enable function over GPIO is not supported by "02B", "62B", "82B", "03B" product versions.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 57 of 163
C1-Public
1.10 Audio interface
☞ Audio is not supported by the LARA-R204-02B and LARA-R220-62B versions.
1.10.1 Digital audio interface
LARA-R2 series modules include a 4-wire I2S digital audio interface (I2S_TXD data output, I2S_RXD
data input, I2S_CLK clock input/output, I2S_WA world alignment / synchronization signal
input/output), which can be configured by AT commands for digital audio communication with
external digital audio devices as an audio codec (for more details, see the u-blox AT commands
manual [2], +UI2S AT command).
The I2S interface can be alternatively set in different modes by the <I2S_mode> parameter of the
AT+UI2S command:
• PCM mode (short synchronization signal): I2S word alignment signal is set high for 1 or 2 clock
cycles for the synchronization, and then is set low for 16 clock cycles according to the 17 or 18
clock cycle frame length.
• Normal I2S mode (long synchronization signal): the I2S word alignment is set high / low with a 50%
duty cycle (high for 16 clock cycles / low for 16 clock cycles, according to the 32 clock cycle frame
length).
The I2S interface can be alternatively set in different roles by the <I2S_host_localdevice> parameter
of AT+UI2S:
• Host mode
• Local device mode
The sample rate of transmitted/received words, which corresponds to the I2S word
alignment / synchronization signal frequency, can be alternatively set by the <I2S_sample_rate>
parameter of AT+UI2S to:
• 8 kHz
• 11.025 kHz
• 12 kHz
• 16 kHz
• 22.05 kHz
• 24 kHz
• 32 kHz
• 44.1 kHz
• 48 kHz
The modules support I2S transmit and I2S receive data 16-bit words long, linear, mono (or also dual
mono in Normal I2S mode). Data is transmitted and read in 2’s complement notation. MSB is
transmitted and read first.
I2S clock signal frequency depends on the frame length, the sample rate and the selected mode of
operation:
• 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate> in PCM mode (short synchronization signal)
• 16 x 2 x <I2S_sample_rate> in normal I2S mode (long synchronization signal)
☞ For the complete description of the possible configurations and settings of the I2S digital audio
interface for PCM and Normal I2S modes, refer to the u-blox AT commands manual [2], +UI2S AT
command.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 58 of 163
C1-Public
1.11 Clock output
LARA-R2 series modules provide the digital clock output function on the GPIO6 pin, which can be
configured to provide a 13 MHz or 26 MHz square wave. This is mainly designed to feed the clock input
of an external audio codec, as the clock output can be configured in “Audio dependent” mode
(generating the square wave only when the audio path is active), or in “Continuous” mode.
For more details, see the u-blox AT commands manual [2], +UMCLK AT command.
1.12 General Purpose Input/Output (GPIO)
LARA-R2 series modules include 9 pins (GPIO1-GPIO5, I2S_TXD, I2S_RXD, I2S_CLK, I2S_WA) which
can be configured as General Purpose Input/Output or to provide custom functions via u-blox AT
commands (for more details, see the u-blox AT commands manual [2], +UGPIOC, +UGPIOR, +UGPIOW
AT commands), as summarized in Table 12.
Function
Description
Default GPIO
Configurable GPIOs
Network status
indication
Network status: registered home network, registered
roaming, data transmission, no service
--
GPIO1-GPIO4
GNSS supply enable22
Enable/disable the supply of u-blox GNSS receiver
connected to the cellular module
GPIO2
GPIO1-GPIO4
GNSS data ready22
Sense when u-blox GNSS receiver connected to the
module is ready for sending data by the DDC (I2C)
GPIO3
GPIO3
GNSS RTC sharing23
RTC synchronization signal to the u-blox GNSS
receiver connected to the cellular module
--
GPIO4
SIM card detection
External SIM card physical presence detection
GPIO5
GPIO5
SIM card hot
insertion/removal
Enable / disable SIM interface upon detection of
external SIM card physical insertion / removal
--
GPIO5
I2S digital audio
interface
I2S digital audio interface
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
Wi-Fi control23
Control of an external Wi-Fi chip or module
--
--
General purpose input
Input to sense high or low digital level
--
All
General purpose output
Output to set the high or the low digital level
GPIO4
All
Pin disabled
Tri-state with an internal active pull-down enabled
GPIO1
All
Table 12: LARA-R2 series GPIO custom functions configuration
1.13 Reserved pins (RSVD)
LARA-R2 series modules have pins reserved for future use, named RSVD: they can all be left
unconnected on the application board, except
• the RSVD pin number 33 that must be externally connected to ground
22
Not supported by LARA-R204-02B and LARA-R211-02B-00 product versions: GPIO2 and GPIO3 pins are by default disabled
23
Not supported by the "02B", "62B", "82B", and "03B" product versions
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 59 of 163
C1-Public
1.14 System features
1.14.1 Network indication
GPIOs can be configured by the AT command to indicate network status (for further details, see
section 1.12 and the u-blox AT commands manual [2], GPIO commands):
• No service (no network coverage or not registered)
• Registered 2G / 3G / LTE home network
• Registered 2G / 3G / LTE visitor network (roaming)
• Call enabled (RF data transmission / reception)
1.14.2 Antenna detection
The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as
an optional feature that can be implemented if the application requires it. The antenna supervisor is
forced by the +UANTR AT command (see the u-blox AT commands manual [2] for more details).
The requirements to achieve antenna detection functionality are the following:
• an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used
• an antenna detection circuit must be implemented on the application board
See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2
for detection circuit on the application board and diagnostic circuit on antenna assembly design-in
guidelines.
1.14.3 Dual stack IPv4/IPv6
LARA-R2 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel.
For more details about dual stack IPv4/IPv6, see the u-blox AT commands manual [2].
1.14.4 PPP
LARA-R2 series support a Point-to-Point Protocol in order to establish a connection with the external
application via a serial interface (UART, MUX, or CDC-ACM): IPv4/IPv6 packets are relayed through
the cellular protocol stack with the external application.
1.14.5 TCP/IP and UDP/IP
LARA-R2 series modules provide an embedded TCP/IP and UDP/IP protocol stack: a PDP context can
be configured, established and handled via the data connection management packet switched data
commands.
LARA-R2 series modules provide a Direct Link mode to establish a transparent end-to-end
communication with an already connected TCP or UDP socket via serial interfaces. In Direct Link
mode, data sent to the serial interface from an external application processor is forwarded to the
network and vice-versa.
For more details about embedded TCP/IP and UDP/IP functionalities, see the u-blox AT commands
manual [2]
1.14.6 FTP
LARA-R2 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in
the local file system of the module.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 60 of 163
C1-Public
FTP files can also be transferred using FTP Direct Link:
• FTP download: data coming from the FTP server is forwarded to the host processor via serial
interfaces (for FTP without Direct Link mode the data is always stored in the module’s Flash File
System)
• FTP upload: data coming from the host processor via serial interfaces is forwarded to the FTP
server (for FTP without Direct Link mode the data is read from the module’s Flash File System)
When Direct Link is used for a FTP file transfer, only the file content pass through USB / UART serial
interface, whereas all the FTP commands handling is managed internally by the FTP application.
For more details about embedded FTP functionalities, see the u-blox AT commands manual [2].
1.14.7 HTTP
LARA-R2 series modules provide the embedded Hyper-Text Transfer Protocol (HTTP) services via AT
commands for sending requests to a remote HTTP server, receiving the server response and
transparently storing it in the module’s Flash File System (FFS).
For more details about embedded HTTP functionalities, see the u-blox AT commands manual [2].
1.14.8 SSL/TLS
LARA-R2 series modules support the Secure Sockets Layer (SSL) / Transport Layer Security (TLS)
with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols.
The SSL/TLS support provides different connection security aspects:
• Server authentication: use of the server certificate verification against a specific trusted
certificate or a trusted certificates list
• Client authentication: use of the client certificate and the corresponding private key
• Data security and integrity: data encryption and Hash Message Authentication Code (HMAC)
generation
The security aspects used during a connection depend on the SSL/TLS configuration and features
supported.
Table 13 contains the settings of the default SSL/TLS profile and Table 14 to Table 18 report the
main SSL/TLS supported capabilities of the products. For a complete list of supported configurations
and settings, see the u-blox AT commands manual [2].
Settings
Value
Meaning
Certificates validation level
Level 0
The server certificate will not be checked or verified
Minimum SSL/TLS version
Any
The server can use any of the TLS1.0/TLS1.1/TLS1.2 versions for
the connection
Cipher suite
Automatic
The cipher suite will be negotiated in the handshake process
Trusted root certificate internal name
None
No certificate will be used for the server authentication
Expected server host-name
None
No server host-name is expected
Client certificate internal name
None
No client certificate will be used
Client private key internal name
None
No client private key will be used
Client private key password
None
No client private key password will be used
Pre-shared key
None
No pre-shared key password will be used
Table 13: Default SSL/TLS profile
SSL/TLS Version
SSL 2.0
NO
SSL 3.0
YES
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 61 of 163
C1-Public
SSL/TLS Version
TLS 1.0
YES
TLS 1.1
YES
TLS 1.2
YES
Table 14: SSL/TLS version support
Algorithm
RSA YES
PSK YES
Table 15: Authentication
Algorithm
RC4 NO
DES YES
3DES
YES
AES128
YES
AES256
YES
Table 16: Encryption
Algorithm
MD5
NO
SHA/SHA1
YES
SHA256
YES
SHA384
YES
Table 17: Message digest
Description
Registry value
TLS_RSA_WITH_AES_128_CBC_SHA
0x00,0x2F
YES
TLS_RSA_WITH_AES_128_CBC_SHA256
0x00,0x3C
YES
TLS_RSA_WITH_AES_256_CBC_SHA
0x00,0x35
YES
TLS_RSA_WITH_AES_256_CBC_SHA256
0x00,0x3D
YES
TLS_RSA_WITH_3DES_EDE_CBC_SHA
0x00,0x0A
YES
TLS_RSA_WITH_RC4_128_MD5
0x00,0x04
NO
TLS_RSA_WITH_RC4_128_SHA
0x00,0x05
NO
TLS_PSK_WITH_AES_128_CBC_SHA
0x00,0x8C
YES
TLS_PSK_WITH_AES_256_CBC_SHA
0x00,0x8D
YES
TLS_PSK_WITH_3DES_EDE_CBC_SHA
0x00,0x8B
YES
TLS_RSA_PSK_WITH_AES_128_CBC_SHA
0x00,0x94
YES
TLS_RSA_PSK_WITH_AES_256_CBC_SHA
0x00,0x95
YES
TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
0x00,0x93
YES
TLS_PSK_WITH_AES_128_CBC_SHA256
0x00,0xAE
YES
TLS_PSK_WITH_AES_256_CBC_SHA384
0x00,0xAF
YES
TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
0x00,0xB6
YES
TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
0x00,0xB7
YES
Table 18: TLS cipher suite registry
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 62 of 163
C1-Public
1.14.9 Bearer Independent Protocol
The Bearer Independent Protocol (BIP) is a mechanism by which a cellular module provides a SIM with
access to the data bearers supported by the network. With the BIP for Over-the-Air SIM provisioning,
the data transfer from and to the SIM uses either an already active PDP context or a new PDP context
established with the APN provided by the SIM card. For more details, see the u-blox AT commands
manual [2].
1.14.10 AssistNow clients and GNSS integration
☞ AssistNow clients and u-blox GNSS receiver integration are not supported by the LARA-R204-02B
and LARA-R211-02B-00 product versions.
For customers using u-blox GNSS receivers, the LARA-R2 series cellular modules feature embedded
AssistNow clients. AssistNow A-GPS provides better GNSS performance and faster
Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT
commands manual [2]).
LARA-R2 series cellular modules act as a stand-alone AssistNow client, making AssistNow available
with no additional requirements for resources or software integration on an external host micro
controller. Full access to u-blox positioning receivers is available via the cellular modules, through a
dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning chipset / module
power-on/off. This means that the cellular module and the GNSS receiver can be controlled through a
single serial port from any host processor.
1.14.11 Hybrid positioning and CellLocate
®
☞ Hybrid positioning and CellLocate
®
are not supported by LARA-R204-02B and LARA-R211-02B-00
product versions.
Although GNSS is a widespread technology, its reliance on the visibility of extremely weak GNSS
satellite signals means that positioning is not always possible. Especially difficult environments for
GNSS are indoors, in enclosed or underground parking garages, as well as in urban canyons where
GNSS signals are blocked or jammed by multipath interference. The situation can be improved by
augmenting GNSS receiver data with cellular network information to provide positioning information
even when GNSS reception is degraded or absent. This additional information can benefit numerous
applications.
Positioning through cellular information: CellLocate®
u-blox CellLocate® enables the device position estimation based on the parameters of the mobile
network cells visible to the specific device. To estimate its position, the u-blox cellular module sends
the CellLocate® server the parameters of network cells visible to it using a UDP connection. In return,
the server provides the estimated position based on the CellLocate® database. The module can either
send the parameters of the visible home network cells only (normal scan) or the parameters of all
surrounding cells of all mobile operators (deep scan).
☞ The deep scan is not supported by the "02B", "62B", "82B", and "03B" product versions.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 63 of 163
C1-Public
The CellLocate® database is compiled from the position of devices which observed, in the past, a
specific cell or set of cells (historical observations) as follows:
1. Several devices reported their position to the CellLocate
®
server when observing a specific cell
(the As in the picture represent the position of the devices which observed the same cell A)
2. CellLocate
®
server defines the area of Cell A visibility
3. If a new device reports the observation of Cell A, CellLocate
®
is able to provide the estimated
position from the area of visibility.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 64 of 163
C1-Public
4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of
visibility.
CellLocate® is implemented using a set of two AT commands that allow configuration of the
CellLocate® service (AT+ULOCCELL) and requesting position according to the user configuration
(AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude,
longitude and estimated accuracy.
☞ The accuracy of the position estimated by CellLocate
®
depends on the availability of historical
observations in the specific area.
Hybrid positioning
With u-blox hybrid positioning technology, u-blox cellular modules can be triggered to provide their
current position using either a u-blox GNSS receiver or the position estimated from CellLocate®. The
choice depends on which positioning method provides the best and fastest solution according to the
user configuration, exploiting the benefit of having multiple and complementary positioning methods.
Hybrid positioning is implemented through a set of three AT commands that allow GNSS receiver
configuration (AT+ULOCGNSS), CellLocate® service configuration (AT+ULOCCELL), and requesting
the position according to the user configuration (AT+ULOC). The answer is provided in the form of an
unsolicited AT command including latitude, longitude and estimated accuracy (if the position has
been estimated by CellLocate®), and additional parameters if the position has been computed by the
GNSS receiver.
The configuration of mobile network cells does not remain static (e.g. new cells are continuously
added or existing cells are reconfigured by the network operators). For this reason, when a hybrid
positioning method has been triggered and the GNSS receiver calculates the position, a database selflearning mechanism has been implemented so that these positions are sent to the server to update
the database and maintain its accuracy.
The use of hybrid positioning requires a connection via the DDC (I2C) bus between the cellular modules
and the u-blox GNSS receiver (see section 2.6.5).
See the GNSS implementation application note [22] for a complete description of the feature.
☞ u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate
®
server, u-blox
is unable to track the SIM used or the specific device.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 65 of 163
C1-Public
1.14.12 Wi-Fi integration
☞ Full access to external u-blox short range communication Wi-Fi modules is available through SDIO
interface is not supported by the "02B", "62B", "82B", and "03B" product versions.
The SDIO interface is designed to provide full access to external u-blox short range communication
Wi-Fi modules (see sections 1.9.6 and 2.6.6). This means that combining a LARA-R2 series cellular
module with a u-blox short range communication module gives designers full access to the Wi-Fi
module directly via the cellular module, so that a second interface connected to the Wi-Fi module is
not necessary.
AT commands via the AT interfaces of the cellular module (UART, USB) allows a full control of the
Wi-Fi module from any host processor, because Wi-Fi control messages are relayed to the Wi-Fi
module via the dedicated SDIO interface.
All the management software for Wi-Fi module operations runs inside the cellular module in addition
to those required for cellular-only operation.
1.14.13 Firmware upgrade Over AT (FOAT)
This feature allows upgrading the module firmware over the USB / UART serial interfaces, using AT
commands.
• The +UFWUPD AT command triggers a reboot followed by the upgrade procedure at a specified
baud rate.
• A special boot loader on the module performs firmware installation, security verifications and
module reboot.
• Firmware authenticity verification is performed via a security signature during the download. The
firmware is then installed, overwriting the current version. In the event of a power loss during this
phase, the boot loader detects a fault at the next wake-up, and restarts the firmware download.
After completing the upgrade, the module is reset again and wakes-up in normal boot.
For more details about the Firmware update Over AT procedure, see the FW update application
note [23] and the u-blox AT commands manual [2], +UFWUPD AT command.
1.14.14 Firmware update Over The Air (FOTA)
This feature allows upgrading the module firmware over the LTE/3G/2G air interface.
In order to reduce the amount of data to be transmitted over the air, the implemented FOTA feature
requires downloading only a “delta file” instead of the full firmware. The delta file contains only the
differences between the two firmware versions (old and new), and is compressed. The firmware
update procedure can be triggered using a dedicated AT command with the delta file stored in the
module file system via over the air FTP.
For more details about the Firmware update Over The Air procedure, see the Firmware update
application note [23] and the u-blox AT commands manual [2], +UFWINSTALL AT command.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 66 of 163
C1-Public
1.14.15 Smart temperature management
Cellular modules – independently from the specific model – always have a well-defined operating
temperature range. This range should be respected to guarantee full device functionality and long life
span.
Nevertheless, there are environmental conditions that can affect the operating temperature, e.g. if
the device is located near a heating/cooling source, if there is/is not air circulating, etc.
The module itself can also influence the environmental conditions; such as when it is transmitting at
full power. In this case, its temperature increases very quickly and can raise the temperature nearby.
The best solution is always to properly design the system where the module is integrated.
Nevertheless an extra check/security mechanism embedded into the module is a good solution to
prevent operation of the device outside of the specified range.
Smart Temperature Supervisor (STS)
The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command.
See the u-blox AT commands manual [2] for more details. An URC indication is provided once the
feature is enabled and at the module power-on.
The cellular module measures the internal temperature (Ti) and its value is compared with predefined
thresholds to identify the actual working temperature range.
☞ Temperature measurement is done inside the module: the measured value could be different from
the environmental temperature (Ta).
Warning
area
t
-1
t
+1
t
+2
t
-2
Valid temperature range
Safe
area
Dangerous
area
Dangerous
area
Warning
area
Figure 25: Temperature range and limits
The entire temperature range is divided into sub-regions by limits (see Figure 25) named t-2, t-1, t+1
and t+2.
• Within the first limit, (t
-1
< Ti < t+1), the cellular module is in the normal working range, the Safe
Area.
• In the Warning Area, (t
-2
< Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid
temperature range, but the measured temperature is approaching the limit (upper or lower). The
module sends a warning to the user (through the active AT communication interface), who can
take, if possible, the necessary actions to return to a safer temperature range or simply ignore the
indication. The module is still in a valid and good working condition.
• Outside the valid temperature range, (Ti < t
-2
) or (Ti > t+2), the device is working outside the
specified range and represents a dangerous working condition. This condition is indicated and the
device shuts down to avoid damage.
☞ For security reasons, the shutdown is suspended whenever an emergency call is in progress. In
this case, the device switches off upon call termination.
☞ The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If
the feature is disabled, there is no embedded protection against disallowed temperature
conditions.
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 67 of 163
C1-Public
Figure 26 shows the flow diagram implemented for the Smart Temperature Supervisor.
IF STS
enabled
Read
temperature
IF
(t-1<Ti<t+1)
IF
(t-2<Ti<t+2)
Send
notification
(warning)
Send
notification
(dangerous)
Wait emergency
call termination
IF
emerg.
call in
progress
Shut the device
down
Yes
No
Yes
Yes
No
No
No
Yes
Send
shutdown
notification
Feature enabled
(full logic or
indication only)
IF
Full Logic
Enabled
Feature disabled:
no action
Temperature is
within normal
operating range
Yes
Tempetature
is within
warning area
Tempetature is
outside valid
temperature range
No
Feature enabled
in full logic mode
Feature enabled in
indication only mode:
no further actions
Send
notification
(safe)
Previously
outside of
Safe Area
Tempetatur
e is back to
safe area
No
No
further
actions
Yes
Figure 26: Smart Temperature Supervisor (STS) flow diagram
Threshold definitions
When the application of the cellular module operates at extreme temperatures with the Smart
Temperature Supervisor enabled, the user should note that when outside of the valid temperature
range, the device will automatically shut down as described above.
The input for the algorithm is always the temperature measured within the cellular module (Ti,
internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for
example) during transmission at maximum power a significant fraction of DC input power is
LARA-R2 series - System integration manual
UBX-16010573 - R21 System description Page 68 of 163
C1-Public
dissipated as heat. This behavior is partially compensated for by the definition of the upper shutdown
threshold (t+2) that is slightly higher than the declared environmental temperature limit.
The temperature thresholds are defined according the Table 19.
Symbol
Parameter
Temperature
t-2
Low temperature shutdown
–40 °C
t-1
Low temperature warning
–30 °C
t+1
High temperature warning
+77 °C
t+2
High temperature shutdown
+97 °C
Table 19: Thresholds definition for Smart Temperature Supervisor
☞ The sensor measures board temperature inside the shields, which can differ from the ambient
temperature.
1.14.16 Power saving
The power saving configuration is disabled by default, but it can be enabled using the AT+UPSV
command (for the complete description of the AT+UPSV command, see the u-blox AT commands
manual [2]).
When power saving is enabled, the module automatically enters the low power idle mode whenever
possible, reducing current consumption (see section 1.5.1.5 and the LARA-R2 series data sheet [1]).
During the low power idle mode, the module is temporarily not ready to communicate with an external
device, as it is configured to reduce power consumption. The module wakes up from low power idle
mode to active mode in the following events:
• Automatic periodic monitoring of the paging channel for the paging block reception according to
network conditions (see 1.5.1.5, 1.9.1.4)
• Automatic periodic enable of the UART interface to receive / send data, with AT+UPSV=1
(see 1.9.1.4)
• RTS input set ON by the host DTE, with HW flow control disabled and AT+UPSV=2 (see 1.9.1.4)
• DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4)
• USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.3)
• The connected USB host forces a remote wake-up of the module as USB device (see 1.9.3.4)
• The connected u-blox GNSS receiver forces a wake-up of the cellular module using the GNSS Tx
data ready function over GPIO3 (see 1.9.5)
• The connected SDIO device forces a wake-up of the module as SDIO host (see 1.9.6)
• A preset RTC alarm occurs (see the u-blox AT commands manual [2], AT+CALA)
For the definition and the description of LARA-R2 series modules operating modes, including the
events forcing transitions between the different operating modes, see section 1.4.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 69 of 163
C1-Public
2 Design-in
2.1 Overview
For an optimal integration of LARA-R2 series modules in the final application board, follow the design
guidelines stated in this section.
Every application circuit must be properly designed to guarantee the correct functionality of the
related interface, but a number of points require greater attention during the design of the application
device.
The following list provides a ranking of importance in the application design, starting from the highest
relevance:
1. Module antenna connection: ANT1, ANT2 and ANT_DET pins.
Antenna circuit directly affects the RF compliance of the device integrating a LARA-R2 series
module with the applicable certification schemes. Very carefully follow the suggestions provided
in section 2.4 for schematic and layout design.
2. Module supply: VCC and GND pins.
The supply circuit affects the RF compliance of the device integrating a LARA-R2 series module
with applicable certification schemes as well as antenna circuit design. Very carefully follow the
suggestions provided in section 2.2.1 for schematic and layout design.
3. USB interface: USB_D+, USB_D- and VUSB_DET pins.
Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully
follow the suggestions provided in the related section 2.6.1 for schematic and layout design.
4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST, SIM_DET pins.
Accurate design is required to guarantee SIM card functionality and compliance with applicable
conformance standards, also reducing the risk of RF coupling. Carefully follow the suggestions
provided in section 2.5 for schematic and layout design.
5. HSIC interface: HSIC_DATA, HSIC_STRB pins.
Accurate design is required to guarantee HSIC interface functionality. Carefully follow the
suggestions provided in the relative section 2.6.4 for schematic and layout design.
6. SDIO interface: SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD pins.
Accurate design is required to guarantee SDIO interface functionality. Carefully follow the
suggestions provided in the relative section 2.6.6 for schematic and layout design.
7. System functions: RESET_N, PWR_ON pins.
Accurate design is required to guarantee that the voltage level is well defined during operation.
Carefully follow the suggestions provided in section 2.3 for schematic and layout design.
8. Other digital interfaces: UART, I2C, I2S, Host Select, GPIOs, and Reserved pins.
Accurate design is required to guarantee proper functionality and reduce the risk of digital data
frequency harmonics coupling. Follow the suggestions provided in 2.6.1, 2.6.5, 2.7.1, 2.3.3, 2.8
and 2.9 for schematic and layout design.
9. Other supplies: the V_BCKP RTC supply input/output and the V_INT digital interfaces supply
output.
Accurate design is required to guarantee proper functionality. Follow the suggestions provided
in sections 2.2.2 and 2.2.3 for schematic and layout design.
☞ It is recommended to follow the specific design guidelines provided by each manufacturer of any
external part selected for the application board integrating the u-blox cellular modules.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 70 of 163
C1-Public
2.2 Supply interfaces
2.2.1 Module supply (VCC)
2.2.1.1 General guidelines for VCC supply circuit selection and design
All of the available VCC pins must be connected to the external supply minimizing the power loss due
to series resistance.
GND pins are internally connected but connect all the available pins to solid ground on the application
board, since a good (low impedance) connection to external ground can minimize power loss and
improve RF and thermal performance.
LARA-R2 series modules must be supplied through the VCC pins by a proper DC power supply that
should comply with the module VCC requirements summarized in Table 6.
The proper DC power supply can be selected according to application requirements (see Figure 27)
between various possible supply sources types, of which the most common ones are the following:
• Switching regulator
• Low Drop-Out (LDO) linear regulator
• Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery
• Primary (disposable) battery
Main Supply
Available?
Battery
Li-Ion 3.7 V
Linear LDO
Regulator
Main Supply
Voltage > 5V?
Switching Step-Down
Regulator
No, portable device
No, less than 5 V
Yes, greater than 5 V
Yes, always available
Figure 27: VCC supply concept selection
The DC/DC switching step-down regulator is the typical choice when the available primary supply
source has a nominal voltage much higher (e.g. greater than 5 V) than the modules VCC operating
supply voltage. The use of switching step-down provides the best power efficiency for the overall
application and minimizes current drawn from the main supply source. See sections 2.2.1.2 and
2.2.1.6, 2.2.1.10, 2.2.1.12 for the specific design-in.
The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low
voltage (e.g. less than 5 V). In this case the typical 90% efficiency of the switching regulator
diminishes the benefit of voltage step-down and no true advantage is gained in input current savings.
On the opposite side, linear regulators are not recommended for high voltage step-down as they
dissipate a considerable amount of energy in thermal power. See sections 2.2.1.3 and 2.2.1.6,
2.2.1.10, 2.2.1.12 for the specific design-in.
If LARA-R2 series modules are deployed in a mobile unit where no permanent primary supply source
is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery
pack directly connected to VCC is the usual choice for battery-powered devices. During charging,
batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating
for VCC, and should therefore be avoided. See sections 2.2.1.4, 2.2.1.6, 2.2.1.7, 2.2.1.10, 2.2.1.12 for
the specific design-in.
Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger
circuit which is not included in the modules. The charger circuit must be designed to prevent
over-voltage on the VCC pins, and it should be selected according to the application requirements: a
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 71 of 163
C1-Public
DC/DC switching charger is the typical choice when the charging source has an high nominal voltage
(e.g. ~12 V), whereas a linear charger is the typical choice when the charging source has a relatively
low nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a
rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as a possible supply
source, then a proper charger / regulator with integrated power path management function can be
selected to supply the module while simultaneously and independently charging the battery. See
sections 2.2.1.8, 2.2.1.9, and 2.2.1.4, 2.2.1.6, 2.2.1.7, 2.2.1.10, 2.2.1.12 for the specific design-in.
An appropriate primary (not rechargeable) battery can be selected taking into account the maximum
current specified in the LARA-R2 series data sheet [1] during connected mode, considering that
primary cells might have weak power capability. See sections 2.2.1.5, 2.2.1.6, 2.2.1.10, and 2.2.1.12
for the specific design-in.
The usage of more than one DC supply at the same time should be carefully evaluated: depending on
the supply source characteristics, different DC supply systems can be mutually exclusive.
The usage of a regulator or a battery not able to support the highest peak of VCC current consumption
specified in the LARA-R2 series data sheet [1] is generally not recommended. However, if the selected
regulator or battery is not able to support the highest peak current of the module, it must be able to
support at least the highest averaged current consumption value specified in the LARA-R2 series
data sheet [1] with an adequate margin. The additional energy required by the module during a 2G Tx
slot can be provided by an appropriate bypass tank capacitor or super-capacitor with very large
capacitance and very low ESR placed close to the module VCC pins. Depending on the actual capability
of the selected regulator or battery, the required capacitance can be considerably larger than 1 mF
and the required ESR can be in the range of few tens of m. Carefully evaluate the super-capacitor
characteristics, since aging and temperature may affect the actual characteristics.
The following sections highlight some design aspects for each of the supplies listed above, providing
application circuit design-in compliant with the module VCC requirements summarized in Table 6.
2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
The use of a switching regulator is suggested when the difference from the available supply rail to the
VCC value is high: switching regulators provide good efficiency transforming a 12 V or greater voltage
supply to the typical 3.8 V value of the VCC supply.
The characteristics of the switching regulator connected to the VCC pins should meet the following
prerequisites to comply with the module’s VCC requirements summarized in Table 6:
• Power capability: the switching regulator with its output circuit must be capable of providing a
voltage value to the VCC pins within the specified operating range and must be capable of
delivering to the VCC pins the specified maximum peak / pulse current consumption during Tx
burst at the maximum Tx power specified in the LARA-R2 series data sheet [1]
• Low output ripple: the switching regulator together with its output circuit must be capable of
providing a clean (low noise) VCC voltage profile.
• High switching frequency: for best performance and for smaller applications, it is recommended
to select a switching frequency ≥ 600 kHz (since the L-C output filter is typically smaller for high
switching frequencies). The use of a switching regulator with a variable switching frequency or
with a switching frequency lower than 600 kHz must be evaluated carefully, since this can produce
noise in the VCC voltage profile and therefore negatively impact modulation spectrum
performance.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 72 of 163
C1-Public
• PWM mode operation: it is preferable to select regulators with a Pulse Width Modulation (PWM)
mode. While in connected mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM
modes transitions must be avoided in order to reduce noise on the VCC voltage profile. Switching
regulators can be used that are able to switch between low ripple PWM mode and high ripple PFM
mode, provided that the mode transition occurs when the module changes status from the
idle/active modes to connected mode. It is permissible to use a regulator that switches from the
PWM mode to the burst or PFM mode at an appropriate current threshold.
• Output voltage slope: the use of the soft start function provided by some voltage regulators
should be evaluated carefully, as the VCC voltage must ramp from 2.3 V to 2.8 V in less than 4 ms
to switch on the module by applying the VCC supply. The module can be otherwise switched on by
forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the RESET_N
pin when the VCC supply voltage stabilizes at its proper nominal value.
Figure 28 and the components listed in Table 20 show an example of a high reliability power supply
circuit, where the VCC module is supplied by a step-down switching regulator capable of delivering
the specified maximum peak / pulse current to the VCC pins, with low output ripple and with fixed
switching frequency in PWM mode operation greater than 1 MHz.
LARA-R2 series
12V
C5
R3
C4
R2
C2C1
R1
VIN
RUN
VC
RT
PG
SYNC
BD
BOOST
SW
FB
GND
6
7
10
9
5
C6
1
2
3
8
11
4
C7 C8
D1
R4
R5
L1
C3
U1
52
VCC
53
VCC
51
VCC
GND
Figure 28: Example of high reliability VCC supply application circuit using a step-down regulator
Reference
Description
Part number - manufacturer
C1
10 µF Capacitor Ceramic X7R 5750 15% 50 V
C5750X7R1H106MB - TDK
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
680 pF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71H681KA01 - Murata
C4
22 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1H220JZ01 - Murata
C5
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C6
470 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E474KA12 - Murata
C7
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 - Murata
C8
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
D1
Schottky Diode 40 V 3 A
MBRA340T3G - ON Semiconductor
L1
10 µH Inductor 744066100 30% 3.6 A
744066100 - Wurth Electronics
R1
470 k Resistor 0402 5% 0.1 W
2322-705-87474-L - Yageo
R2
15 k Resistor 0402 5% 0.1 W
2322-705-87153-L - Yageo
R3
22 k Resistor 0402 5% 0.1 W
2322-705-87223-L - Yageo
R4
390 k Resistor 0402 1% 0.063 W
RC0402FR-07390KL - Yageo
R5
100 k Resistor 0402 5% 0.1 W
2322-705-70104-L - Yageo
U1
Step-Down Regulator MSOP10 3.5 A 2.4 MHz
LT3972IMSE#PBF - Linear Technology
Table 20: Components for high reliability VCC supply application circuit using a step-down regulator
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 73 of 163
C1-Public
Figure 29 and the components listed in Table 21 show an example of a low cost power supply circuit,
where the VCC module supply is provided by a step-down switching regulator capable of delivering
the specified maximum peak / pulse current to the VCC pins, transforming a 12 V supply input.
LARA-R2 series
12V
R5
C6C1
VCC
INH
FSW
SYNC
OUT
GND
2
6
3
1
7
8
C3
C2
D1
R1
R2
L1
U1
GND
FB
COMP
5
4
R3
C4
R4
C5
52
VCC
53
VCC
51
VCC
Figure 29: Example of low cost VCC supply application circuit using step-down regulator
Reference
Description
Part number - manufacturer
C1
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 – Murata
C2
100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15m
T520B107M006ATE015 – Kemet
C3
5.6 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H562KA88 – Murata
C4
6.8 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H682KA88 – Murata
C5
56 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H560JA01 – Murata
C6
220 nF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E224KA88 – Murata
D1
Schottky Diode 25V 2 A
STPS2L25 – STMicroelectronics
L1
5.2 µH Inductor 30% 5.28A 22 m
MSS1038-522NL – Coilcraft
R1
4.7 k Resistor 0402 1% 0.063 W
RC0402FR-074K7L – Yageo
R2
910 Resistor 0402 1% 0.063 W
RC0402FR-07910RL – Yageo
R3
82 Resistor 0402 5% 0.063 W
RC0402JR-0782RL – Yageo
R4
8.2 k Resistor 0402 5% 0.063 W
RC0402JR-078K2L – Yageo
R5
39 k Resistor 0402 5% 0.063 W
RC0402JR-0739KL – Yageo
U1
Step-Down Regulator 8-VFQFPN 3 A 1 MHz
L5987TR – ST Microelectronics
Table 21: Components for a low cost VCC supply application circuit using a step-down regulator
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 74 of 163
C1-Public
2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
The use of a linear regulator is suggested when the difference from the available supply rail and the
VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to a voltage
value within the module VCC normal operating range.
The characteristics of the LDO linear regulator connected to the VCC pins should meet the following
prerequisites to comply with the module’s VCC requirements summarized in Table 6:
• Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a
voltage value to the VCC pins within the specified operating range and must be capable of
delivering the maximum peak / pulse current consumption to the VCC pins during a Tx burst at
the maximum Tx power specified in the LARA-R2 series data sheet [1].
• Power dissipation: the power handling capability of the LDO linear regulator must be checked to
limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop
from the max input voltage to the min output voltage to evaluate the power dissipation of the
regulator).
• Output voltage slope: the use of the soft start function provided by some voltage regulators
should be evaluated carefully, as the VCC voltage must ramp from 2.3 V to 2.8 V in less than 4 ms
to switch on the module by applying the VCC supply. The module can be otherwise switched on by
forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the RESET_N
pin when the VCC supply voltage stabilizes at its proper nominal value.
Figure 30 and the components listed in Table 22 show an example of a high reliability power supply
circuit, where the VCC module supply is provided by an LDO linear regulator which is capable of
delivering the specified highest peak / pulse current, with the proper power handling capability. The
regulator described in this example supports a wide input voltage range, and it includes internal
circuitry for reverse battery protection, current limiting, thermal limiting and reverse current
protection.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit
described in Figure 30 and Table 22). This reduces the power on the linear regulator and improves the
whole thermal design of the supply circuit.
5V
C1
IN OUT
ADJ
GND
1
2
4
5
3
C2R1
R2
U1
SHDN
LARA-R2 series
52
VCC
53
VCC
51
VCC
GND
Figure 30: Example of a high reliability VCC supply application circuit using an LDO linear regulator
Reference
Description
Part number - manufacturer
C1, C2
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
R1
9.1 k Resistor 0402 5% 0.1 W
RC0402JR-079K1L - Yageo Phycomp
R2
3.9 k Resistor 0402 5% 0.1 W
RC0402JR-073K9L - Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LT1764AEQ#PBF - Linear Technology
Table 22: Components for a high reliability VCC supply application circuit using an LDO linear regulator
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 75 of 163
C1-Public
Figure 31 and the components listed in Table 23 show an example of a low cost power supply circuit,
where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified
highest peak / pulse current, with the proper power handling capability. The regulator described in this
example supports a limited input voltage range and it includes internal circuitry for current and
thermal protection.
It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly
below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit
described in Figure 31 and Table 23). This reduces the power on the linear regulator and improves the
whole thermal design of the supply circuit.
5V
C1
IN OUT
ADJ
GND
1
2
4
5
3
C2R1
R2
U1
EN
LARA-R2 series
52
VCC
53
VCC
51
VCC
GND
Figure 31: Example of a low cost VCC supply application circuit using an LDO linear regulator
Reference
Description
Part number - manufacturer
C1, C2
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
R1
27 k Resistor 0402 5% 0.1 W
RC0402JR-0727KL - Yageo Phycomp
R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
U1
LDO Linear Regulator ADJ 3.0 A
LP38501ATJ-ADJ/NOPB - Texas Instrument
Table 23: Components for a low cost VCC supply application circuit using an LDO linear regulator
2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following
prerequisites to comply with the module VCC requirements summarized in Table 6:
• Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output
circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum
peak / pulse current consumption during a Tx burst at the maximum Tx power specified in the
LARA-R2 series data sheet [1], and must be capable of extensively delivering a DC current as the
maximum average current consumption specified in the LARA-R2 series data sheet [1]. The
maximum discharge current is not always reported in the data sheets of batteries, but the
maximum DC discharge current is typically almost equal to the battery capacity in amp-hours
divided by 1 hour.
• DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of
avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit
bursts.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 76 of 163
C1-Public
2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
The characteristics of a primary (non-rechargeable) battery connected to the VCC pins should meet
the following prerequisites to comply with the module’s VCC requirements summarized in Table 6:
• Maximum pulse and DC discharge current: the non-rechargeable battery with its related output
circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum
peak current consumption during a Tx burst at the maximum Tx power specified in the LARA-R2
series data sheet [1], and must be capable of extensively delivering a DC current as the maximum
average current consumption specified in the LARA-R2 series data sheet [1]. The maximum
discharge current is not always reported in the data sheets of batteries, but the max DC discharge
current is typically almost equal to the battery capacity in amp-hours divided by 1 hour.
• DC series resistance: the non-rechargeable battery with its output circuit must be capable of
avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit
bursts.
2.2.1.6 Additional guidelines for VCC supply circuit design
To reduce voltage drops, use a low impedance power source. The series resistance of the power supply
lines (connected to the VCC and GND pins of the module) on the application board and battery pack
should also be considered and minimized: cabling and routing must be as short as possible to
minimize power losses.
Three pins are allocated for the VCC supply. Several pins are designated for the GND connection. It is
recommended to properly connect all of them to supply the module to minimize series resistance
losses.
For modules supporting 2G radio access technology, to avoid voltage drop undershoot and overshoot
at the start and end of a transmit burst during a GSM call (when current consumption on the VCC
supply can rise up as specified in the LARA-R2 series data sheet [1]), place a bypass capacitor with
large capacitance (at least 100 µF) and low ESR near the VCC pins, for example:
• 330 µF capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)
To reduce voltage ripple and noise, improving RF performance especially if the application device
integrates an internal antenna, place the following bypass capacitors near the VCC pins:
• 68 pF 0402 capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata
GRM1555C1E560J)
• 15 pF 0402 capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata
GRM1555C1E150J)
• 8.2 pF 0402 capacitor with Self-Resonant Frequency in 2500/2600 MHz range (e.g. Murata
GRM1555C1H8R2D)
• 10 nF 0402 capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and
data sources
• 100 nF 0402 capacitor (e.g. Murata GRM155R61C104K) to filter digital logic noise from clocks
and data sources
A suitable series ferrite bead can be properly placed on the VCC line for additional noise filtering if
required by the specific application according to the whole application board design.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 77 of 163
C1-Public
C2
GND
C3 C4
LARA-R2 series
52
VCC
53
VCC
51
VCC
C1 C6
3V8
+
Recommended for
cellular modules
supporting 2G
C5
Recommended for
cellular modules
supporting LTE band-7
Figure 32: Suggested schematic for the VCC bypass capacitors to reduce ripple / noise on the supply voltage profile
Reference
Description
Part number - manufacturer
C1
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 - Murata
C2
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 - Murata
C3
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C4
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C5
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C104KA01 - Murata
C6
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
Table 24: Suggested components to reduce ripple / noise on VCC
☞ The necessity of each part depends on the specific design, but it is recommended to provide all
the bypass capacitors described in Figure 32 / Table 24 if the application device integrates an
internal antenna.
☞ ESD sensitivity rating of the VCC supply pins is 1 kV (Human Body Model as per JESD22-A114).
Higher protection level can be required if the line is externally accessible on the application board,
e.g. if the accessible battery connector is directly connected to VCC pins. A higher protection level
can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array)
close to the accessible point.
2.2.1.7 Additional guidelines for VCC supply circuit design of LARA-R211
modules
LARA-R211 modules provide separate supply inputs over the VCC pins (see Figure 3):
• VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding
most of the total current drawn of the module when RF transmission is enabled during a
voice/data call
• VCC pin #51 represents the supply input for the internal baseband Power Management Unit and
the internal transceiver, demanding a minor part of the total current drawn of the module when
RF transmission is enabled during a voice/data call
LARA-R211 modules support two different extended operating voltage ranges: one for the VCC pins
#52 and #53, and another one for the VCC pin #51 (see the LARA-R2 series data sheet [1]).
All the VCC pins are in general intended to be connected to the same external power supply circuit,
but separate supply sources can be implemented for specific (e.g. battery-powered) applications
considering that the voltage at the VCC pins #52 and #53 can drop to a value lower than the one at
the VCC pin #51, keeping the module still switched-on and functional. Figure 33 describes a possible
application circuit.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 78 of 163
C1-Public
C1 C4
GND
C3C2 C6
LARA-R211
52
VCC
53
VCC
51
VCC
+
Li-Ion/Li-Pol
Battery
C7
SWVIN
SHDNn
GND
FB
C8
R1
R2
L1
U1
Step-up
Regulator
D1
C9
C5
Figure 33: VCC circuit example with a separate supply for LARA-R211 modules
Reference
Description
Part number - manufacturer
C1
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C4
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C5
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 - Murata
C6
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 - Murata
C7
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
C8
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 - Murata
C9
10 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E100JA01 - Murata
D1
Schottky Diode 40 V 1 A
SS14 - Vishay General Semiconductor
L1
10 µH Inductor 20% 1 A 276 m
SRN3015-100M - Bourns Inc.
R1
1 M Resistor 0402 5% 0.063 W
RC0402FR-071ML - Yageo Phycomp
R2
412 k Resistor 0402 5% 0.063 W
RC0402FR-07412KL - Yageo Phycomp
U1
Step-up Regulator 350 mA
AP3015 - Diodes Incorporated
Table 25: Example of components for VCC circuit with a separate supply for LARA-R211 modules
2.2.1.8 Guidelines for external battery charging circuit
LARA-R2 series modules do not have an on-board charging circuit. Figure 34 provides an example of
a battery charger design, suitable for applications powered with a Li-Ion (or Li-Polymer) battery.
In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse
and DC discharge current capabilities and proper DC series resistance, is directly connected to the
VCC supply input of the module. Battery charging is completely managed by the STMicroelectronics
L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges as a linear charger the
battery, in three phases:
• Pre-charge constant current (active when the battery is deeply discharged): the battery is
charged with a low current, set to 10% of the fast-charge current
• Fast-charge constant current: the battery is charged with the maximum current, configured by
the value of an external resistor to a value suitable for USB power source (~500 mA)
• Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the
L6924U starts to reduce the current until the charge termination is done. The charging process
ends when the charging current reaches the value configured by an external resistor to ~15 mA or
when the charging timer reaches the value configured by an external capacitor to ~9800 s.
Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature
to protect the battery from operating under unsafe thermal conditions.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 79 of 163
C1-Public
The L6924U, as a linear charger, is more suitable for applications where the charging source has a
relatively low nominal voltage (~5 V), so that a switching charger is suggested for applications where
the charging source has a relatively high nominal voltage (e.g. ~12 V, see the following section 2.2.1.9
for specific design-in).
C5 C8
GND
C7C6 C9
LARA-R2 series
52
VCC
53
VCC
51
VCC
+
USB
Supply
C3
R4
θ
U1
IUSB
IAC
IEND
TPRG
SD
VIN
VINSNS
MODE
ISEL
C2C1
5V
TH
GND
VOUT
VOSNS
VREF
R1
R2
R3
Li-Ion/Li-Pol
Battery Pack
D1
B1
C4
Li-Ion/Li-Polymer
Battery Charger IC
D2
C10
Figure 34: Li-Ion (or Li-Polymer) battery charging application circuit
Reference
Description
Part number - manufacturer
B1
Li-Ion (or Li-Polymer) battery pack with 470 NTC
Various manufacturer
C1, C4
1 µF Capacitor Ceramic X7R 0603 10% 16 V
GRM188R71C105KA12 - Murata
C2, C6
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
1 nF Capacitor Ceramic X7R 0402 10% 50 V
GRM155R71H102KA01 - Murata
C5
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C7
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C8
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C9
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 - Murata
C10
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 - Murata
D1, D2
Low Capacitance ESD Protection
CG0402MLE-18G - Bourns
R1, R2
24 k Resistor 0402 5% 0.1 W
RC0402JR-0724KL - Yageo Phycomp
R3
3.3 k Resistor 0402 5% 0.1 W
RC0402JR-073K3L - Yageo Phycomp
R4
1.0 k Resistor 0402 5% 0.1 W
RC0402JR-071K0L - Yageo Phycomp
U1
Single Cell Li-Ion (or Li-Polymer) Battery Charger IC
for USB port and AC Adapter
L6924U - STMicroelectronics
Table 26: Suggested components for a Li-Ion (or Li-Polymer) battery charging application circuit
2.2.1.9 Guidelines for external charging and power path management circuit
Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a
rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as the possible supply
source should implement a suitable charger / regulator with an integrated power path management
function to supply the module and the whole device while simultaneously and independently charging
the battery.
Figure 35 illustrates a simplified block diagram circuit showing the working principle of a
charger / regulator with integrated power path management function. This component allows the
system to be powered by a permanent primary supply source (e.g. ~12 V) using the integrated
regulator which simultaneously and independently recharges the battery (e.g. 3.7 V Li-Pol) that
represents the back-up supply source of the system: the power path management feature permits
the battery to supplement the system current requirements when the primary supply source is not
available or cannot deliver the peak system currents.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 80 of 163
C1-Public
A power management IC should meet the following prerequisites to comply with the module VCC
requirements summarized in Table 6:
• High efficiency internal step down converter, compliant with the performances specified in
section 2.2.1.2
• Low internal resistance in the active path Vout – Vbat, typically lower than 50 m
• High efficiency switch mode charger with separate power path control
GND
Power path management IC
VoutVin
θ
Li-Ion/Li-Pol
Battery Pack
GND
System
12 V
Primary
Source
Charge
controller
DC/DC
converter and
battery FET
control logic
Vbat
Figure 35: Charger / regulator with an integrated power path management circuit block diagram
Figure 36 and the components listed in Table 27 provide an application circuit example where the MPS
MP2617H switching charger / regulator with an integrated power path management function
provides the supply to the cellular module, while concurrently and autonomously charging a suitable
Li-Ion (or Li-Polymer) battery with the proper pulse and DC discharge current capabilities and the
proper DC series resistance according to the rechargeable battery recommendations described in
section 2.2.1.4.
The MP2617H IC constantly monitors the battery voltage and selects whether to use the external
main primary supply / charging source or the battery as the supply source for the module, and starts
a charging phase accordingly.
The MP2617H IC normally provides a supply voltage to the module regulated from the external main
primary source allowing immediate system operation even under missing or deeply discharged
battery conditions: the integrated switching step-down regulator is capable of provifing up to 3 A
output current with low output ripple and fixed 1.6 MHz switching frequency in PWM mode operation.
The module load is satisfied in priority, then the integrated switching charger will take the remaining
current to charge the battery.
Additionally, the power path control allows an internal connection from the battery to the module with
a low series internal ON resistance (40 m typical), in order to supplement additional power to the
module when the current demand increases over the external main primary source or when this
external source is removed.
Battery charging is managed in three phases:
• Pre-charge constant current (active when the battery is deeply discharged): the battery is
charged with a low current, set to 10% of the fast-charge current
• Fast-charge constant current: the battery is charged with the maximum current, configured by
the value of an external resistor to a value suitable for the application
• Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the
current is progressively reduced until the charge termination is done. The charging process ends
when the charging current reaches the 10% of the fast-charge current or when the charging timer
reaches the value configured by an external capacitor.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 81 of 163
C1-Public
Using a battery pack with an internal NTC resistor, the MP2617H IC can monitor the battery
temperature to protect the battery from operating under unsafe thermal conditions.
Several parameters, such as the charging current, the charging timings, the input current limit, the
input voltage limit, and the system output voltage, can be easily set according to the specific
application requirements, as the actual electrical characteristics of the battery and the external
supply / charging source: proper resistors or capacitors must be accordingly connected to the related
pins of the IC.
C10 C13
GND
C12C11
LARA-R2
52
VCC
53
VCC
51
VCC
+
Primary
Source
R3
U1
ENn
ILIM
ISET
TMR
AGND
VIN
C2C1
12V
NTC
PGND
SW
SYS
BAT
C4
R1
R2
D1
θ
Li-Ion/Li-Pol
Battery Pack
B1
C5
Li-Ion/Li-Polymer Battery
Charger / Regulator with
Power Path Managment
VCC
C3 C6
L1
BST
D2
VLIM
R4
R5
C7 C8
D3
R6
SYSFB
R7
Figure 36: Li-Ion (or Li-Polymer) battery charging and power path management application circuit
Reference
Description
Part number - manufacturer
B1
Li-Ion (or Li-Polymer) battery pack with 10 k NTC
Various manufacturer
C1, C6
22 µF Capacitor Ceramic X5R 1210 10% 25 V
GRM32ER61E226KE15 - Murata
C2, C4, C10
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C3
1 µF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E105KA12 - Murata
C5
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C7, C12
68 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H680JA01 - Murata
C8, C13
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 - Murata
C11
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
D1, D2
Low Capacitance ESD Protection
CG0402MLE-18G - Bourns
D3
Schottky Diode 40 V 3 A
MBRA340T3G - ON Semiconductor
R1, R3, R5, R7
10 k Resistor 0402 1% 1/16 W
Generic manufacturer
R2
1.05 k Resistor 0402 1% 0.1 W
Generic manufacturer
R4
22 k Resistor 0402 1% 1/16 W
Generic manufacturer
R6
26.5 k Resistor 0402 1% 1/16 W
Generic manufacturer
L1
2.2 µH Inductor 7.4 A 13 m 20%
SRN8040-2R2Y - Bourns
U1
Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator
with integrated Power Path Management function
MP2617H - Monolithic Power Systems (MPS)
Table 27: Suggested components for Li-Ion (or Li-Pol) battery charging and power path management application circuit
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 82 of 163
C1-Public
2.2.1.10 Guidelines for removing VCC supply
As described in section 1.6.2 and Figure 15, the VCC supply can be removed after the end of
LARA-R2 series modules internal power-off sequence, which must be properly started sending the
AT+CPWROFF command (see the u-blox AT commands manual [2]). Removing the VCC power can be
useful in order to minimize the current consumption when the LARA-R2 series modules are switched
off. Afterwards, the modules can be switched on again by re-applying the VCC supply.
If the VCC supply is generated by a switching or an LDO regulator, the application processor may
control the input pin of the regulator which is provided to enable / disable the output of the regulator
(as for example, the RUN input pin for the regulator described in Figure 28, or the SHDNn input pin for
the regulator described in Figure 30), in order to apply / remove the VCC supply.
If the regulator that generates the VCC supply does not provide an on / off pin, or for other applications
such as the battery-powered ones, the VCC supply can be switched off using an appropriate external
p-channel MOSFET controlled by the application processor by means of a proper inverting transistor
as shown in Figure 37, given that the external pMOS has to provide:
• Very low R
DS(ON)
(for example, less than 50 m), to minimize voltage drops
• Adequate maximum Drain current (see LARA-R2 series data sheet [1] for module consumption)
• Low leakage current, to minimize the consumption
C3
GND
C2C1 C4
LARA-R2 series
52
VCC
53
VCC
51
VCC
+
VCC Supply Source
GND
GPIO
C5 C6
R1
R3
R2
T2
T1
Application
Processor
Figure 37: Example of application circuit for a VCC supply removal
Reference
Description
Part number - manufacturer
R1
47 k Resistor 0402 5% 0.1 W
RC0402JR-0747KL - Yageo Phycomp
R2
10 k Resistor 0402 5% 0.1 W
RC0402JR-0710KL - Yageo Phycomp
R3
100 k Resistor 0402 5% 0.1 W
RC0402JR-07100KL - Yageo Phycomp
T1
P-Channel MOSFET Low On-Resistance
AO3415 - Alpha & Omega Semiconductor Inc.
T2
NPN BJT Transistor
BC847 - Infineon
C1
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
T520D337M006ATE045 - KEMET
C2
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C3
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
C4
56 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E560JA01 - Murata
C5
15 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1E150JA01 - Murata
C6
8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H8R2DZ01 - Murata
Table 28: Components for a VCC supply removal application circuit
☞ It is highly recommended to avoid an abrupt removal of the VCC supply during LARA-R2 series
modules normal operations: the power-off procedure must be started by the AT+CPWROFF
command, waiting the command response for a proper time period (see the u-blox AT commands
manual [2]), and then a proper VCC supply must be held at least until the end of the modules’
internal power-off sequence, which occurs when the generic digital interfaces supply output
(V_INT) is switched off by the module.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 83 of 163
C1-Public
2.2.1.11 Guidelines for VCC supply layout design
• Good connection of the module VCC pins with a DC supply source is required for correct RF
performance. Guidelines are summarized in the following list:
• All the available VCC pins must be connected to the DC source.
• VCC connection must be as wide as possible and as short as possible.
• Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must
be avoided.
• VCC connection must be routed through a PCB area separated from sensitive analog signals and
sensitive functional units: it is good practice to interpose at least one layer of PCB ground between
VCC track and other signal routing.
• Coupling between VCC and audio lines (especially microphone inputs) must be avoided, because
the typical GSM burst has a periodic nature of approximately 217 Hz, which lies in the audio range.
• The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.6
should be placed close to the VCC pins. If the main DC source is a switching DC-DC converter, place
the large capacitor close to the DC-DC output and minimize the VCC track length. Otherwise,
consider using separate large capacitors for the DC-DC converter and the cellular module.
• The bypass capacitors in the pF range described in section 2.2.1.6 should be placed as close as
possible to the VCC pins. This is highly recommended if the device integrates an internal antenna.
• Since VCC is directly connected to RF Power Amplifiers, voltage ripple at high frequency may
result in unwanted spurious modulation of the transmitter RF signal. This is more likely to happen
with switching DC-DC converters, in which case it is better to select the highest operating
frequency for the switcher and add a large L-C filter before connecting to the LARA-R2 series
modules in the worst case.
• Shielding of the switching DC-DC converter circuit, or at least the use of shielded inductors for the
switching DC-DC converter, may be considered since all switching power supplies may potentially
generate interfering signals as a result of high-frequency, high-power switching.
• If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings
are not exceeded, place the protecting device along the path from the DC source toward the
cellular module, preferably closer to the DC source (otherwise protection functionality may be
compromised).
2.2.1.12 Guidelines for grounding layout design
Good connection of the module GND pins with the application board solid ground layer is required for
correct RF performance. It significantly improves RF and thermal heat sink figures for the module.
• Connect each GND pin with the application board solid GND layer. It is strongly recommended that
each GND pin surrounding VCC pins have one or more dedicated via down to the application board
solid ground layer.
• The VCC supply current flows back to the main DC source through GND as ground current: provide
an adequate return path with a suitable uninterrupted ground plane to the main DC source.
• It is recommended to implement one layer of the application PCB as a ground plane as wide as
possible.
• If the application board is a multilayer PCB, then all the board layers should be filled with GND plane
as much as possible and each GND area should be connected together with a complete via stack
down to the main ground layer of the PCB. Use as many vias as possible to connect ground planes
• Provide a dense line of vias at the edges of each GND area, in particular along RF and high speed
lines
• If the whole application device is composed of more than one PCB, then it is required to provide a
good and solid ground connection between the GND areas of all the multiple PCBs.
• Good grounding of GND pins also ensures thermal heat sink. This is critical during call connection,
when the real network commands the module to transmit at maximum power: proper grounding
helps prevent module overheating.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 84 of 163
C1-Public
2.2.2 RTC supply (V_BCKP)
2.2.2.1 Guidelines for V_BCKP circuit design
LARA-R2 series modules provide the V_BCKP RTC supply input/output, which can be mainly used to:
• Provide RTC back-up when VCC supply is removed
If RTC timing is required to run for a time interval of T [s] when VCC supply is removed, place a
capacitor with a nominal capacitance of C [µF] at the V_BCKP pin. Choose the capacitor using the
following formula:
C [µF] = (Current_Consumption [µA] x T [s]) / Voltage_Drop [V]
= 2.5 x T [s]
For example, a 100 µF capacitor can be placed at V_BCKP to provide RTC backup holding the V_BCKP
voltage within its valid range for around 40 s at +25 °C, after the VCC supply is removed. If a longer
buffering time is required, a 70 mF super-capacitor can be placed at V_BCKP, with a 4.7 k series
resistor to hold the V_BCKP voltage within its valid range for approximately 8 hours at +25 °C, after
the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current
due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the
V_BCKP pin after VCC supply has been provided. These capacitors allow the time reference to run
during battery disconnection.
LARA-R2 series
C1
(a)
2
V_BCKP
R2
LARA-R2 series
C2
(superCap)
(b)
2
V_BCKP
D3
LARA-R2 series
B3
(c)
2
V_BCKP
Figure 38: Real time clock supply (V_BCKP) application circuits: (a) using a 100 µF capacitor to let the RTC run for ~1 minute
after VCC removal; (b) using a 70 mF capacitor to let the RTC run for ~10 hours after VCC removal; (c) using a
non-rechargeable battery
Reference
Description
Part number - manufacturer
C1
100 µF Tantalum Capacitor
GRM43SR60J107M - Murata
R2
4.7 k Resistor 0402 5% 0.1 W
RC0402JR-074K7L - Yageo Phycomp
C2
70 mF Capacitor
XH414H-IV01E - Seiko Instruments
Table 29: Example of components for V_BCKP buffering
If a longer buffering time is required to allow the RTC time reference to run during a disconnection of
the VCC supply, then an external battery can be connected to the V_BCKP pin. The battery should be
able to provide a proper nominal voltage and must never exceed the maximum operating voltage for
V_BCKP (specified in the Input characteristics of Supply/Power pins table in the LARA-R2 series data
sheet [1]). The connection of the battery to V_BCKP should be done with a suitable series resistor for
a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The
purpose of the series resistor is to limit the battery charging current due to the battery specifications,
and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been
provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to
the non-rechargeable battery.
☞ If the RTC timing is not required when the VCC supply is removed, it is not needed to connect the
V_BCKP pin to an external capacitor or battery. In this case, the date and time are not updated
when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from
the main supply and there is no need for an external component on V_BCKP.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 85 of 163
C1-Public
Combining a LARA-R2 series cellular module with a u-blox GNSS positioning receiver, the positioning
receiver VCC supply is controlled by the cellular module by means of the “GNSS supply enable”
function provided by the GPIO2 of the cellular module. In this case, the V_BCKP supply output of the
cellular module can be connected to the V_BCKP backup supply input pin of the GNSS receiver to
provide the supply for the positioning real time clock and backup RAM when the VCC supply of the
cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This
enables the u-blox GNSS receiver to recover from a power breakdown with either a hot start or a warm
start (depending on the duration of the positioning VCC outage) and to maintain the configuration
settings saved in the backup RAM. Refer to section 2.6.5 for more details regarding the application
circuit with a u-blox GNSS receiver.
☞ The internal regulator for V_BCKP is optimized for low leakage current and very light loads. Do not
apply loads which might exceed the limit for the maximum available current from V_BCKP supply,
as this can cause malfunctions in the module. The LARA-R2 series data sheet [1] describes the
detailed electrical characteristics.
The V_BCKP supply output pin provides internal short circuit protection to limit the start-up current
and protect the device in short circuit situations. No additional external short circuit protection is
required.
☞ ESD sensitivity rating of the V_BCKP supply pin is 1 kV (Human Body Model according to
JESD22-A114). Higher protection level can be required if the line is externally accessible on the
application board, e.g. if an accessible back-up battery connector is directly connected to V_BCKP
pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) close to the accessible point.
2.2.2.2 Guidelines for V_BCKP layout design
The RTC supply (V_BCKP) requires careful layout: avoid injecting noise on this voltage domain, as it
may affect the stability of the 32 kHz oscillator.
2.2.3 Interface supply (V_INT)
2.2.3.1 Guidelines for V_INT circuit design
LARA-R2 series provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly
used to:
• Indicate when the module is switched on (see sections 1.6.1, 1.6.2 for more details)
• Pull-up SIM detection signal (see section 2.5 for more details)
• Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see
section 2.6.1)
• Pull-up DDC (I2C) interface signals (see section 2.6.5 for more details)
• Supply a 1.8 V u-blox 6 or subsequent GNSS receiver (see section 2.6.5 for more details)
• Supply an external device as an external 1.8 V audio codec (see section 2.7.1 for more details)
The V_INT supply output pin provides internal short circuit protection to limit the start-up current
and protect the device in short circuit situations. No additional external short circuit protection is
required.
☞ Do not apply loads which might exceed the limit for maximum available current from V_INT supply
(see the LARA-R2 series data sheet [1]) as this can cause malfunctions in the internal circuitry.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 86 of 163
C1-Public
☞ Since the V_INT supply is generated by an internal switching step-down regulator, the V_INT
voltage ripple can range as specified in the LARA-R2 series data sheet [1]: it is not recommended
to supply sensitive analog circuitry without adequate filtering for digital noise.
☞ V_INT can only be used as an output: do not connect any external supply source on V_INT.
☞ ESD sensitivity rating of the V_INT supply pin is 1 kV (HBM according to JESD22-A114).
A higher protection level could be required if the line is externally accessible and it can be achieved
by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the
accessible point.
☞ It is recommended to provide direct access to the V_INT pin on the application board by means of
an accessible test point directly connected to the V_INT pin.
2.2.3.2 Guidelines for V_INT layout design
The V_INT supply output is generated by an integrated switching step-down converter, used
internally to supply the generic digital interfaces. Because of this, it can be a source of noise: avoid
coupling with sensitive signals.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 87 of 163
C1-Public
2.3 System functions interfaces
2.3.1 Module power-on (PWR_ON)
2.3.1.1 Guidelines for PWR_ON circuit design
LARA-R2 series modules’ PWR_ON input is equipped with an internal active pull-up resistor to the
VCC module supply as described in Figure 39: an external pull-up resistor is not required and should
not be provided.
If connecting the PWR_ON input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD
protection should be provided close to the accessible point, as described in Figure 39 and Table 30.
☞ The ESD sensitivity rating of the PWR_ON pin is 1 kV (HBM according to JESD22-A114).
A higher protection level can be required if the line is externally accessible on the application board,
e.g. if an accessible push button is directly connected to the PWR_ON pin. A higher protection level
can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array)
close to the accessible point.
An open drain or open collector output is suitable to drive the PWR_ON input from an application
processor, as the pin is equipped with an internal active pull-up resistor to the V_BCKP supply, as
described in Figure 39.
A compatible push-pull output of an application processor can also be used. In any case, take care to
set the proper level in all the possible scenarios to avoid an inappropriate module switch-on.
1:1 scaling
LARA-R2 series
2
V_BCKP
15
PWR_ON
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
LARA-R2 series
2
V_BCKP
15
PWR_ON
TP
TP
10 k
10 k
Figure 39: PWR_ON application circuits using a push button and an open drain output of an application processor
Reference
Description
Part number - manufacturer
ESD
Varistor array for ESD protection
CT0402S14AHSG - EPCOS
Table 30: Example of pull-up resistor and ESD protection for the PWR_ON application circuit
☞ It is recommended to provide direct access to the PWR_ON pin on the application board by means
of an accessible testpoint directly connected to the PWR_ON pin.
2.3.1.2 Guidelines for PWR_ON layout design
The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to
switch on the LARA-R2 series modules. It is required to ensure that the voltage level is well defined
during operation and no transient noise is coupled on this line, otherwise the module might detect a
spurious power-on request.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 88 of 163
C1-Public
2.3.2 Module reset (RESET_N)
2.3.2.1 Guidelines for RESET_N circuit design
LARA-R2 series RESET_N is equipped with an internal pull-up to the V_BCKP supply as described in
Figure 40. An external pull-up resistor is not required.
If connecting the RESET_N input to a push button, the pin will be externally accessible on the
application device. According to EMC/ESD requirements of the application, an additional ESD
protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to the
accessible point on the line connected to this pin, as described in Figure 40 and Table 31.
☞ The ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model as per JESD22-A114).
A higher protection level can be required if the line is externally accessible on the application board,
e.g. if an accessible push button is directly connected to the RESET_N pin. A higher protection
level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) close to the accessible point.
An open drain output is suitable to drive the RESET_N input from an application processor as it is
equipped with an internal pull-up to V_BCKP supply, as described in Figure 40.
A compatible push-pull output of an application processor can also be used. In any case, take care to
set the proper level in all the possible scenarios to avoid an inappropriate module reset, switch-on or
switch-off.
1:1 scaling
LARA-R2 series
2
V_BCKP
18
RESET_N
Power-on
push button
ESD
Open
Drain
Output
Application
Processor
LARA-R2 series
2
V_BCKP
18
RESET_N
TP
TP
10 k
10 k
Figure 40: RESET_N application circuits using a push button and an open drain output of an application processor
Reference
Description
Part number - manufacturer
ESD
Varistor for ESD protection
CT0402S14AHSG - EPCOS
Table 31: Example of ESD protection component for the RESET_N application circuit
☞ If the external reset function is not required by the customer application, the RESET_N pin can be
left unconnected to external components, but it is recommended to provide direct access on the
application board by means of an accessible testpoint directly connected to the RESET_N pin.
2.3.2.2 Guidelines for RESET_N layout design
The reset circuit (RESET_N) requires careful layout due to the pin function: ensure that the voltage
level is well defined during operation and no transient noise is coupled on this line, otherwise the
module might detect a spurious reset request. It is recommended to keep the connection line to
RESET_N as short as possible.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 89 of 163
C1-Public
2.3.3 Module / host configuration selection
2.3.3.1 Guidelines for HOST_SELECT circuit design
☞ The HOST_SELECT pin functionality is not supported by the "02B", "62B", "82B", "03B" versions.
LARA-R2 series modules include one pin (HOST_SELECT) to select the module / host application
processor configuration: the pin is available to select, enable, connect, disconnect and subsequently
re-connect the HSIC (USB High-Speed Inter-Chip) interface.
LARA-R2 series data sheet [1] describes the detailed electrical characteristics of HOST_SELECT pin.
☞ Further guidelines for HOST_SELECT pin circuit design will be described in detail in a successive
release of the System Integration Manual.
☞ Do not apply voltage to the HOST_SELECT pin before the switch-on of its supply source (V_INT),
to avoid latch-up of circuits and allow a proper boot of the module. If the external signal connected
to the cellular module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI
SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to
high impedance before the V_INT switch-on.
☞ The ESD sensitivity rating of the HOST_SELECT pin is 1 kV (HBM as per JESD22-A114). A higher
protection level could be required if the line is externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG) close to the accessible points.
☞ If the HOST_SELECT pin is not used, it can be left unconnected on the application board.
2.3.3.2 Guidelines for HOST_SELECT layout design
The pin for the selection of the module / host application processor configuration (HOST_SELECT) is
generally not critical for layout.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 90 of 163
C1-Public
2.4 Antenna interface
LARA-R2 series modules provide two RF interfaces for connecting the external antennas:
• The ANT1 pin represents the primary RF input/output for LTE/3G/2G RF signals transmission and
reception.
• The ANT2 pin represents the secondary RF input for LTE/3G Rx diversity RF signals reception.
Both the ANT1 and the ANT2 pins have a nominal characteristic impedance of 50 and must be
connected to the related antenna through a 50 transmission line to allow proper
transmission / reception of RF signals.
☞ Two antennas (one connected to ANT1 pin and one connected to ANT2 pin) must be used to
support the LTE/3G Rx diversity radio technology. This is a required feature for LTE category 1
User Equipment (up to 10.2 Mb/s Down-Link data rate) according to the 3GPP specifications.
2.4.1 Antenna RF interface (ANT1 / ANT2)
2.4.1.1 General guidelines for antenna selection and design
The antenna is the most critical component to be evaluated. Designers must take care of the
antennas from all perspectives at the very start of the design phase when the physical dimensions of
the application board are under analysis/decision, since the RF compliance of the device integrating
LARA-R2 series modules with all the applicable required certification schemes depends on the
antenna radiating performance.
Cellular antennas are typically available in the types of linear monopole or PCB antennas such as
patches or ceramic SMT elements.
• External antennas (e.g. linear monopole)
o External antennas basically do not imply a physical restriction to the design of the PCB where
the LARA-R2 series module is mounted.
o The radiation performance mainly depends on the antennas. It is required to select antennas
with optimal radiating performance in the operating bands.
o RF cables should be carefully selected to have minimum insertion losses. Additional insertion
loss will be introduced by low quality or long cable. Large insertion loss reduces both transmit
and receive radiation performance.
o A high quality 50 RF connector provides proper PCB-to-RF-cable transition. It is
recommended to strictly follow the layout and cable termination guidelines provided by the
connector manufacturer.
o If antenna detection functionality is required, select an antenna assembly provided with a
proper built-in diagnostic circuit with a resistor connected to ground: see guidelines in
section 2.4.2.
• Integrated antennas (e.g. patch-like antennas):
o Internal integrated antennas imply a physical restriction to the design of the PCB:
An integrated antenna excites RF currents on its counterpoise, typically the PCB ground plane
of the device that becomes part of the antenna: its dimension defines the minimum frequency
that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that
should be similar to the quarter of the wavelength of the minimum frequency that must be
radiated, given that the orientation of the ground plane relative to the antenna element must
be considered.
The isolation between the primary and the secondary antennas must be as high as possible
and the correlation between the 3D radiation patterns of the two antennas must be as low as
possible. In general, a separation of at least a quarter wavelength between the two antennas
is required to achieve a good isolation and low pattern correlation.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 91 of 163
C1-Public
As a numerical example, the physical restriction to the PCB design can be considered as
following:
Frequency = 750 MHz → Wavelength = 40 cm → Minimum GND plane size = 10 cm
o Radiation performance depends on the whole PCB and antenna system design, including
product mechanical design and usage. Antennas should be selected with optimal radiating
performance in the operating bands according to the mechanical specifications of the PCB and
the whole product.
o It is recommended to select a pair of custom antennas designed by an antennas’ manufacturer
if the required ground plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm
wide). The antenna design process should begin at the start of the whole product design
process.
o It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including PCB layout and matching circuitry.
o Further to the custom PCB and product restrictions, antennas may require tuning to obtain
the required performance for compliance with all the applicable required certification schemes.
It is recommended to consult the antenna manufacturer for the design-in guidelines for
antenna matching relative to the custom application.
In both cases, selecting external or internal antennas, these recommendations should be observed:
• Select antennas providing optimal return loss (or VSWR) figure over all the operating frequencies.
• Select antennas providing optimal efficiency figure over all the operating frequencies.
• Select antennas providing similar efficiency for both the primary (ANT1) and the secondary
(ANT2) antenna.
• Select antennas providing appropriate gain figure (i.e. combined antenna directivity and efficiency
figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits
specified in some countries (e.g. by the FCC in the United States, as reported in section 4.2.2).
• Select antennas capable to provide low Envelope Correlation Coefficient between the primary
(ANT1) and the secondary (ANT2) antenna: the 3D antenna radiation patterns should have lobes
in different directions.
2.4.1.2 Guidelines for antenna RF interface design
Guidelines for ANT1 / ANT2 pins RF connection design
Proper transition between ANT1 / ANT2 pads and the application board PCB must be provided,
implementing the following design-in guidelines for the layout of the application PCB close to the
ANT1 / ANT2 pads:
• On a multilayer board, the whole layer stack below the RF connection should be free of digital lines.
• Increase GND keep-out (i.e. clearance, a void area) around the ANT1 / ANT2 pads, on the top layer
of the application PCB, to at least 250 µm up to adjacent pads metal definition and up to 400 µm
on the area below the module, to reduce parasitic capacitance to ground, as described in the left
example of Figure 41.
• Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT1 / ANT2
pads if the top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic
capacitance to ground, as described in the right example of Figure 41.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 92 of 163
C1-Public
Min.
250 µm
Min. 400 µm
GND
ANT1
GND clearance
on very close buried layer
below ANT1 pad
GND clearance
on top layer
around ANT1 pad
Min.
250 µm
Min. 400 µm
GND
ANT2
GND clearance
on very close buried layer
below ANT2 pad
GND clearance
on top layer
around ANT2 pad
Figure 41: GND keep-out area on top layer around ANT1 / ANT2 pads and on very close buried layer below ANT1 / ANT2 pads
Guidelines for RF transmission line design
Any RF transmission line, such as the ones from the ANT1 and ANT2 pads up to the related antenna
connector or up to the related internal antenna pad, must be designed so that the characteristic
impedance is as close as possible to 50 .
RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from
a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is
sandwiched between two parallel ground planes within a dielectric material). The micro strip,
implemented as a coplanar waveguide, is the most common configuration for printed circuit boards.
Figure 42 and Figure 43 provide two examples of proper 50 coplanar waveguide designs. The first
example of an RF transmission line can be implemented for a 4-layer PCB stack-up herein described,
and the second example of an RF transmission line can be implemented for a 2-layer PCB stack-up
herein described.
35 µm
35 µm
35 µm
35 µm
270 µm
270 µm
760 µm
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielectric
FR-4 dielectric
FR-4 dielectric
380 µm 500 µm500 µm
Figure 42: Example of a 50 coplanar waveguide transmission line design for the described 4-layer board layup
35 µm
35 µm
1510 µm
L2 Copper
L1 Copper
FR-4 dielectric
1200 µm 400 µm400 µm
Figure 43: Example of a 50 coplanar waveguide transmission line design for the described 2-layer board layup
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 93 of 163
C1-Public
If the two examples do not match the application PCB layup, the 50 characteristic impedance
calculation can be made using the HFSS commercial finite element method solver for
electromagnetic structures from Ansys Corporation, or using freeware tools like Avago / Broadcom
AppCAD (https://www.broadcom.com/appcad), taking care of the approximation formulas used by
the tools for the impedance computation.
To achieve a 50 characteristic impedance, the width of the transmission line must be chosen
depending on:
• the thickness of the transmission line itself (e.g. 35 µm in the examples of Figure 42 and Figure
43)
• the thickness of the dielectric material between the top layer (where the transmission line is
routed) and the inner closer layer implementing the ground plane (e.g. 270 µm in Figure 42,
1510 µm in Figure 43)
• the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric
material in Figure 42 and Figure 43)
• the gap from the transmission line to the adjacent ground plane on the same layer of the
transmission line (e.g. 500 µm in Figure 42, 400 µm in Figure 43)
If the distance between the transmission line and the adjacent GND area (on the same layer) does not
exceed 5 times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50
calculation.
Additionally to the 50 impedance, the following guidelines are recommended for the transmission
line design:
• Minimize the transmission line length: the insertion loss should be minimized as much as possible,
in the order of a few tenths of a dB.
• Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component
present on the RF transmission line, if top-layer to buried layer dielectric thickness is below
200 µm, to reduce parasitic capacitance to ground.
• The transmission line width and spacing to GND must be uniform and routed as smoothly as
possible: avoid abrupt changes of width and spacing to GND.
• Add GND vias around transmission line, as described in Figure 44.
• Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to the main ground
layer, providing enough on the adjacent metal layer, as described in Figure 44.
• Route RF transmission lines far from any noise source (as switching supplies and digital lines) and
from any sensitive circuit (as analog audio lines).
• Avoid stubs on the transmission line.
• Avoid signal routing in parallel to the transmission line or crossing the transmission line on buried
metal layer.
• Do not route the microstrip line below discrete components or other mechanics placed on the top
layer.
An example of proper RF circuit design is illustrated in Figure 44. In this case, the ANT1 and ANT2
pins are directly connected to SMA connectors by means of proper 50 transmission lines, designed
with proper layout.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 94 of 163
C1-Public
LARA
SMA
SMA
Figure 44: Example of the circuit and layout for antenna RF circuits on the application board
Guidelines for RF termination design
RF terminations must provide a characteristic impedance of 50 as well as the RF transmission lines
up to the RF terminations themselves, to match the characteristic impedance of the ANT1 / ANT2
ports of the modules.
However, real antennas do not have a perfect 50 load on all the supported frequency bands.
Therefore, to reduce as much as possible any performance degradation due to antennas mismatch,
the RF terminations must provide optimal return loss (or VSWR) figure over all the operating
frequencies, as summarized in Table 7 and Table 8.
If external antennas are used, the antenna connectors represent the RF termination on the PCB:
• Use suitable 50 connectors providing proper PCB-to-RF-cable transition.
• Strictly follow the connector manufacturer’s recommended layout, for example:
o SMA Pin-Through-Hole connectors require GND keep-out (i.e. clearance, a void area) on all the
layers around the central pin up to annular pads of the four GND posts, as shown in Figure 44.
o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in
the area below the connector between the GND land pads, as illustrated in Figure 45
Figure 45: U.FL surface mounted connector mounting pattern layout
• Cut out the GND layer under RF connectors and close to buried vias, in order to remove stray
capacitance and thus keep the RF line 50 , e.g. the active pad of U.FL connectors needs to have
a GND keep-out (i.e. clearance, a void area) at least on the first inner layer to reduce parasitic
capacitance to ground.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 95 of 163
C1-Public
If integrated antennas are used, the RF terminations are represented by the integrated antennas
themselves. The following guidelines should be followed:
• Use antennas designed by an antenna manufacturer, providing the best possible return loss (or
VSWR).
• Provide a ground plane large enough according to the relative integrated antenna requirements.
The ground plane of the application PCB can be reduced down to a minimum size that must be
similar to one quarter of a wavelength of the minimum frequency that must be radiated. As a
numerical example,
Frequency = 750 MHz → Wavelength = 40 cm → Minimum GND plane size = 10 cm
• It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including PCB layout and matching circuitry.
• Further to the custom PCB and product restrictions, antennas may require a tuning to comply with
all the applicable required certification schemes. It is recommended to consult the antenna
manufacturer for the design-in guidelines for the antenna matching relative to the custom
application.
Additionally, these recommendations regarding the antenna system placement must be followed:
• Do not place antennas within a closed metal case.
• Do not place the antennas in close vicinity to the end user since the emitted radiation in human
tissue is limited by regulatory requirements.
• Place the antennas far from sensitive analog systems or employ countermeasures to reduce EMC
issues.
• Take care of interaction between co-located RF systems since the cellular transmitted power may
interact or disturb the performance of companion systems.
• Place the two LTE antennas providing low Envelope Correlation Coefficient (ECC) between primary
(ANT1) and secondary (ANT2) antenna: the antenna 3D radiation patterns should have lobes in
different directions. The ECC between the primary and secondary antennas needs to be enough
low to comply with the radiated performance requirements specified by related certification
schemes, as indicated in Table 9.
• Place the two LTE antennas providing enough high isolation (see Table 9) between primary (ANT1)
and secondary (ANT2) antenna. The isolation depends on the distance between antennas
(separation of at least a quarter wavelength required for good isolation), antenna type (using
antennas with different polarization improves isolation), and the antenna 3D radiation patterns
(uncorrelated patterns improve isolation).
Examples of antennas
Table 32 lists some examples of possible internal on-board surface-mount antennas.
Manufacturer
Part number
Product name
Description
Taoglas
PA.710.A
Warrior
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
40.0 x 6.0 x 5.0 mm
Taoglas
PA.711.A
Warrior II
GSM / WCDMA / LTE SMD Antenna
Pairs with the Taoglas PA.710.A Warrior for LTE MIMO applications
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
40.0 x 6.0 x 5.0 mm
Taoglas
PCS.26.A
Havok
LTE SMD dielectric antenna
617..960 MHz, 1710..2690 MHz
54.6 x 13.0 x 3.0 mm
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 96 of 163
C1-Public
Manufacturer
Part number
Product name
Description
Taoglas
PCS.66.A
Reach
Wideband LTE SMD antenna
600..6000 MHz
32.0 x 25.0 x 1.6 mm
Taoglas
PCS.06.A
Havok
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2500..2690 MHz
42.0 x 10.0 x 3.0 mm
Antenova
SR4L002
Lucida
GSM / WCDMA / LTE SMD Antenna
698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz
35.0 x 8.5 x 3.2 mm
Ethertronics
P822601 /
P822602
GSM / WCDMA / LTE SMD antenna
698..960 MHz, 1710..2170 MHz, 2490..2700 MHz
50.0 x 8.0 x 3.2 mm
Ethertronics
1002436
GSM / WCDMA / LTE vertical mount antenna
698..960 MHz, 1710..2700 MHz
50.6 x 19.6 x 1.6 mm
Fractus
NN03-310
TRIO mXTEND™
GSM / WCDMA / LTE SMD antenna
698..8000 MHz
30.0 x 3.0 x 1.0 mm
PulseLarsen
Antennas
W3796
Domino
GSM / WCDMA / LTE SMD antenna
698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz
42.0 x 10.0 x 3.0 mm
TE Connectivity
2118310-1
GSM / WCDMA / LTE vertical mount antenna
698..960 MHz, 1710..2170 MHz, 2300..2700 MHz
74.0 x 10.6 x 1.6 mm
Molex
1462000001
GSM / WCDMA / LTE SMD antenna
698..960 MHz, 1700..2700 MHz
40.0 x 5.0 x 5.0 mm
Table 32: Examples of internal surface-mount antennas
Table 33 lists some examples of possible internal off-board PCB-type antennas with cable and
connector.
Manufacturer
Part number
Product name
Description
Taoglas
FXUB63.07.0150C
GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz
96.0 x 21.0 mm
Taoglas
FXUB66.07.0150C
Maximus
GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL
698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz,
2400..2700 MHz, 3400..3600 MHz, 4800..6000 MHz
120.2 x 50.4 mm
Taoglas
FXUB70.A.07.C.001
GSM / WCDMA / LTE MIMO Antenna on flexible PCB with cable and
U.FL
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz
182.2 x 21.2 mm
Ethertronics
1002289
GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL
698..960 MHz, 1710..2700 MHz
50.0 x 8.0 x 3.2 mm
EAD
FSQS35241-UF-10
SQ7
GSM / WCDMA / LTE Antenna on PCB with cable and U.FL
690..960 MHz, 1710..2170 MHz, 2500..2700 MHz
110.0 x 21.0 mm
Table 33: Examples of internal antennas with cable and connector
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 97 of 163
C1-Public
Table 34 lists some examples of possible external antennas.
Manufacturer
Part number
Product name
Description
Taoglas
GSA.8827.A.101111
Phoenix
GSM / WCDMA / LTE adhesive-mount antenna with cable and
SMA(M)
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz
105 x 30 x 7.7 mm
Taoglas
GSA.8842.A.105111
Wideband LTE I-Bar adhesive antenna with cable and SMA(M)
617..960 MHz, 1710..2700 MHz, 4900..5850 MHz
176.5 x 59.2 x 13.6 mm
Taoglas
TG.55.8113
LTE terminal mount monopole antenna with 90° hinged SMA(M)
617..960 MHz, 1427..2170 MHz, 2300..2690 MHz
172.0 x 23.88 x 13 mm
Taoglas
TG.35.8113W
Apex II
Wideband LTE dipole terminal antenna hinged SMA(M)
617..1200 MHz, 1710..2700 MHz, 4900..5900 MHz
224 x 58 x 13 mm
Taoglas
TG.30.8112
GSM / WCDMA / LTE swivel dipole antenna with SMA(M)
698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz
148.6 x 49 x 10 mm
Taoglas
MA241.BI.001
Genesis
GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination
antenna waterproof IP67 rated with cable and SMA(M)
698..960 MHz, 1710..2170 MHz, 2400..2700 MHz
205.8 x 58 x 12.4 mm
Laird Tech.
TRA6927M3PW-001
GSM / WCDMA / LTE screw-mount antenna with N-type(F)
698..960 MHz, 1710..2170 MHz, 2300..2700 MHz
83.8 x Ø 36.5 mm
Laird Tech.
CMS69273
GSM / WCDMA / LTE ceiling-mount antenna with cable and
N-type(F)
698..960 MHz, 1575.42 MHz, 1710..2700 MHz
86 x Ø 199 mm
Laird Tech.
OC69271-FNM
GSM / WCDMA / LTE pole-mount antenna with N-type(M)
698..960 MHz, 1710..2690 MHz
248 x Ø 24.5 mm
Laird Tech.
CMD69273-30NM
GSM / WCDMA / LTE ceiling-mount MIMO antenna with cables &
N-type(M)
698..960 MHz, 1710..2700 MHz
43.5 x Ø 218.7 mm
Pulse Electronics
WA700/2700SMA
GSM / WCDMA / LTE clip-mount MIMO antenna with cables and
SMA(M)
698..960 MHz,1710..2700 MHz
149 x 127 x 5.1 mm
Table 34: Examples of external antennas
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 98 of 163
C1-Public
2.4.2 Antenna detection interface (ANT_DET)
2.4.2.1 Guidelines for ANT_DET circuit design
Figure 46 and Table 35 describe the recommended schematic / components for the antennas
detection circuit that must be provided on the application board and for the diagnostic circuit that
must be provided on the antennas’ assembly to achieve primary and secondary antenna detection
functionality.
Application Board
Antenna Cable
LARA-R2 series
56
ANT1
59
ANT_DET
R1
C1 D1
C2
J1
Z0= 50 ohm Z0= 50 ohm
Z0= 50 ohm
Primary Antenna Assembly
R2
C4
L3
Radiating
Element
Diagnostic
Circuit
L2
L1
Antenna Cable
62
ANT2
C3
J2
Z0= 50 ohm Z0= 50 ohm
Z0= 50 ohm
Secondary Antenna Assembly
R3
C5
L4
Radiating
Element
Diagnostic
Circuit
D2
Figure 46: Suggested schematic for the antenna detection circuit on the application board and the diagnostic circuit on the
antennas assembly
Reference
Description
Part number - manufacturer
C1
27 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H270J - Murata
C2, C3
33 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H330J - Murata
D1
Very Low Capacitance ESD Protection
PESD0402-140 - Tyco Electronics
D2
Ultra Low Capacitance ESD Protection
ESD0P2RF-02LRH - Infineon
L1, L2
68 nH Multilayer Inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 - Murata
R1
10 k Resistor 0402 1% 0.063 W
RK73H1ETTP1002F - KOA Speer
J1, J2
SMA Connector 50 Through Hole Jack
SMA6251A1-3GT50G-50 - Amphenol
C4, C5
22 pF Capacitor Ceramic C0G 0402 5% 25 V
GRM1555C1H220J - Murata
L3, L4
68 nH Multilayer Inductor 0402 (SRF ~1 GHz)
LQG15HS68NJ02 - Murata
R2, R3
15 k Resistor for Diagnostic
Various Manufacturers
Table 35: Suggested components for the antenna detection circuit on the application board and the diagnostic circuit on the
antennas assembly
The antenna detection circuit and diagnostic circuit suggested in Figure 46 and Table 35 are
explained here:
• When antenna detection is forced by the AT+UANTR command, ANT_DET generates a DC current
measuring the resistance (R2 // R3) from the antenna connectors (J1, J2) provided on the
application board to GND.
• DC blocking capacitors are needed at the ANT1 / ANT2 pins (C2, C3) and at the antenna radiating
element (C4, C5) to decouple the DC current generated by the ANT_DET pin.
• Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series
at the ANT_DET pin (L1, L2) and in series at the diagnostic resistor (L3, L4), to avoid a reduction
of the RF performance of the system, improving the RF isolation of the load resistor.
• Additional components (R1, C1 and D1 in Figure 46) are needed at the ANT_DET pin as ESD
protection
• The ANT1 / ANT2 pins must be connected to the antenna connector by means of a transmission
line with nominal characteristics impedance as close as possible to 50 .
The DC impedance at the RF port for some antennas may be a DC open (e.g. linear monopole) or a DC
short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of
Figure 46, the measured DC resistance is always at the limits of the measurement range (respectively
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 99 of 163
C1-Public
open or short), and there is no means to distinguish between a defect on the antenna path with similar
characteristics (respectively: removal of linear antenna or RF cable shorted to GND for a PIFA
antenna).
Furthermore, any other DC signal injected to the RF connection from an ANT connector to a radiating
element will alter the measurement and produce invalid results for antenna detection.
☞ It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to
30 k to assure good antenna detection functionality and avoid a reduction of module RF
performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the
range of 1 GHz to improve the RF isolation of load resistor.
For example:
Consider an antenna with a built-in DC load resistor of 15 k. Using the +UANTR AT command, the
module reports the resistance value evaluated from the antenna connector provided on the
application board to GND:
• Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k
if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected.
• Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit
“over range” report (see the u-blox AT commands manual [2]) means that that the antenna is not
connected or the RF cable is broken.
• Reported values below the measurement range minimum limit (1 k) highlights a short to GND at
the antenna or along the RF cable.
• Measurement inside the valid measurement range and outside the expected range may indicate
an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostics.
• The reported value could differ from the real resistance value of the diagnostic resistor mounted
inside the antenna assembly due to antenna cable length, antenna cable capacity or the
measurement method used.
☞ If the primary / secondary antenna detection function is not required by the customer application,
the ANT_DET pin can be left not connected and the ANT1 / ANT2 pins can be directly connected
to the related antenna connector by means of a 50 transmission line as described in Figure 44.
2.4.2.2 Guidelines for ANT_DET layout design
The recommended layout for the primary antenna detection circuit to be provided on the application
board to achieve the primary antenna detection functionality, implementing the recommended
schematic described in Figure 46 and Table 35, is explained here:
• The ANT1 / ANT2 pins must be connected to the antenna connector by means of a 50
transmission line, implementing the design guidelines described in section 2.4.1 and the
recommendations of the SMA connector manufacturer.
• DC blocking capacitor at ANT1 / ANT2 pins (C2, C3) must be placed in series to the 50 RF line.
• The ANT_DET pin must be connected to the 50 transmission line by means of a sense line.
• Choke inductors in series at the ANT_DET pin (L1, L2) must be placed so that one pad is on the
50 transmission line and the other pad represents the start of the sense line to ANT_DET pin.
• The additional components (R1, C1, D1) on the ANT_DET line must be placed as ESD protection.
LARA-R2 series - System integration manual
UBX-16010573 - R21 Design-in Page 100 of 163
C1-Public
2.5 SIM interface
2.5.1.1 Guidelines for SIM circuit design
Guidelines for SIM cards, SIM connectors and SIM chips selection
The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical,
electrical and functional characteristics of Universal Integrated Circuit Cards (UICC) which contains
the Subscriber Identification Module (SIM) integrated circuit that securely stores all the information
needed to identify and authenticate subscribers over the cellular network.
Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as
follows:
• Contact C1 = VCC (Supply) → It must be connected to VSIM
• Contact C2 = RST (Reset) → It must be connected to SIM_RST
• Contact C3 = CLK (Clock) → It must be connected to SIM_CLK
• Contact C4 = AUX1 (Auxiliary contact) → It must be left not connected
• Contact C5 = GND (Ground) → It must be connected to GND
• Contact C6 = VPP/SWP (Other function) → It can be left not connected
• Contact C7 = I/O (Data input/output) → It must be connected to SIM_IO
• Contact C8 = AUX2 (Auxiliary contact) → It must be left not connected
A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the
auxiliary contacts C4 and C8. Only 6 contacts are required and must be connected to the module SIM
interface.
Removable SIM cards are suitable for applications requiring a change of SIM card during the product
lifetime.
A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or
it can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch
integrated in the SIM connector for the mechanical card presence detection are provided. Select a
SIM connector providing 6+2 or 8+2 positions if the optional SIM detection feature is required by the
custom application, otherwise a connector without an integrated mechanical presence switch can be
selected.
Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671
as:
• Case pin 8 = UICC contact C1 = VCC (Supply) → It must be connected to VSIM
• Case pin 7 = UICC contact C2 = RST (Reset) → It must be connected to SIM_RST
• Case pin 6 = UICC contact C3 = CLK (Clock) → It must be connected to SIM_CLK
• Case pin 5 = UICC contact C4 = AUX1 (Aux.contact) → It must be left not connected
• Case pin 1 = UICC contact C5 = GND (Ground) → It must be connected to GND
• Case pin 2 = UICC contact C6 = VPP/SWP (Other) → It can be left not connected
• Case pin 3 = UICC contact C7 = I/O (Data I/O) → It must be connected to SIM_IO
• Case pin 4 = UICC contact C8 = AUX2 (Aux. contact) → It must be left not connected
A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other
uses, but only 6 contacts are required and must be connected to the module SIM card interface as
described above.
Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM
once installed.
Loading...