This document describes the hardware features and specifications of
the cost effective AMY-6M GPS module featuring the u-blox 6
positioning engine.
The AMY-6M module boasts the industry’s smallest form factor and
is a fully tested standalone solution that requires no host
integration.
This module combines exceptional GPS performance with highly
flexible power, design, and serial communication options.
www.u-blox.com
AMY-6M
u-blox 6 GPS Modules
Hardware Integration Manual
Document Information
Title
AMY-6M
Subtitle
u-blox6 GPS Modules
Document type
Hardware Integration Manual
Document number
UBX-17021971
Revision and Date
UBX-17021971 – R07
06-Jun-2017
Document status
This document contains data from product verification. Revised and supplementary
data may be published later.
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
GPS Compendium: This document, also known as the GPS book, provides a wealth of information
regarding generic questions about GPS system functionalities and technology.
Receiver Description including Protocol Specification: Messages, configuration and functionalities of
the u-blox 6 software releases and receivers are explained in this document.
Application Note: document provides general design instructions and information that applies to all u-blox
GPS receivers. See Section Related documents for a list of Application Notes related to your GPS receiver.
How to use this Manual
The AMY-6M Hardware Integration Manual provides the necessary information to successfully design in and
configure these u-blox 6-based GPS receiver modules. For navigating this document please note the following:
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox 6 Hardware Integration, please:
Read this manual carefully.
Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com
Contact our information service on the homepage http://www.u-blox.com
Technical Support
Worldwide Web
Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and
helpful FAQ can be accessed 24h a day.
By E-mail
If you have technical problems or cannot find the required information in the provided documents, contact the
nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal
email address of our staff. This makes sure that your request is processed as soon as possible. You will find the
contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support please have the following information ready:
Receiver type (AMY-6M) and firmware version (e.g. V6.02)
Receiver configuration
Clear description of your question or the problem together with a u-center logfile
A short description of the application
Your complete contact details
2.1.11 Active antenna supply ................................................................................................................. 16
2.2 System functions ................................................................................................................................ 17
2.3.2 USB ............................................................................................................................................. 17
2.3.3 Display Data Channel (DDC) ........................................................................................................ 19
4.1 Test parameters for OEM manufacturer .............................................................................................. 44
4.2 System sensitivity test ......................................................................................................................... 44
4.2.1 Guidelines for sensitivity tests ...................................................................................................... 44
4.2.2 ‘Go/No go’ tests for integrated devices ........................................................................................ 44
The AMY-6M is the GPS industry’s smallest standalone receiver. It is a fully tested ROM-based solution that
features the high performance u-blox 6 positioning engine. The AMY-6M has been developed for easy design
and integration and requires no host integration, which enables extremely short times to market.
The AMY-6M offers four different serial interfaces. The receiver provides fast acquisition and excellent tracking
performance at an economical price. Furthermore, 2-layer PCB integration is supported, which brings additional
cost savings.
AMY-6M’s miniature size means that it can be integrated into the smallest portable devices. Advanced
interference suppression mechanisms and innovative RF architecture ensure maximum performance even in
hostile signal environments.
1.2 Architecture
The AMY-6M module consists of two functional parts - the RF and the Baseband sections. See Figure 1 for a
block diagram of the AMY-6M.
The RF section includes the DC-block, the RF input matching, the SAW bandpass filter, the u-blox 6 RF-IC (with
integrated LNA) and the Crystal.
The Baseband section contains the u-blox 6 Baseband processor.
An RTC crystal and additional elements such as an external memory for enhanced programmability and flexibility
are optional.
Figure 1:AMY-6M hardware block schematic
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2 Design-in
In order to obtain good performance with a GPS receiver module, there are a number of points that require
careful attention during the design-in. These include:
Power Supply
Good performance requires a clean and stable power supply.
Interfaces
Ensure correct wiring, rate and message setup on the module and your host system.
Antenna interface
For optimal performance seek short routing, matched impedance and no stubs.
With AMY-6M an additional external LNA is mandatory if no active antenna is used.
2.1 Power management
2.1.1 Overview
The power supply circuitry can be adapted to various concepts, depending on the intended application.
Figure 2 gives an overview of the power supply features.
Figure 2: Power supply diagram
2.1.1.1 Main supply voltage
During operation the base-band supply current is supplied through the V_DCDC pin. The built-in LDO generates
the stabilized core voltage VDD_C from V_DCDC. The current at V_DCDC depends heavily on the current system
state and is in general very dynamic.
Use a low-impedance supply (<< 1 Ohm) at the V_DCDC pin.
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u-blox 6 supports use of an external DC/DC converter for improved power efficiency supplying V_DCDC and
eventually the RF section. The DCDC_EN signal allows shutting down this external DC/DC converter when
V_DCDC is not needed. If the DCDC_EN signal shall be used, VDD_IO must be supplied independently of the
DC/DC converter, i.e. these voltages must be supplied even if the DC/DC converter is disabled.
2.1.1.2 Base-band I/O supply voltage
The digital I/Os of the base-band part are supplied with VDD_IO from the host system. The wide range of
VDD_IO allows seamless interfacing to standard logic voltage levels.
VDD_IO must be supplied in order for the system to boot.
2.1.1.3 Base-band core voltages
The core voltages VDD_B and VDD_C core are generated separately to enable main supply VDD_C switch off
while the back-up domain VDD_B remains alive. The core voltages are generated by means of internal LDOs. The
input voltage range of the LDOs is wide and allows the use of several types of batteries.
2.1.1.4 Backup power supply
A backup battery can be connected to V_BCKP to supply the RTC and backup RAM in case of power failure at
the main battery for backup domain (VDD_IO). An internal switch supplies the internal VDD_B power domain in
case VDD_IO drops below the specified minimum value. VDD_IO will supply the VDD_B power domain if a
sufficiently high input voltage is detected. See Figure 3 below and see also section 2.1.1.6.
Figure 3: Supply of Backup Domain (VDD_B)
Limit V_BCKP and VDD_IO to 3.6 V.
2.1.1.5 RF supply voltages
The RF unit is supplied through the VDD_RF pin. This supply voltage can optionally be generated internally with
an LDO from the VDD_3V input. If the supply voltage is 1.8 V, then the VDD_3V must be shorted to the VDD_RF
pin, so that the internal LDO is shorted and there is no voltage drop.
Depending on the application, the RF supply voltage can be supplied from 3 different sources:
1. From the V_DCDC node of the baseband power supply, taking advantage of the optional DC/DC
converter.
2. From the VDD_IO node, in cases where the Main Battery voltage and/or V_DCDC are lower than the
minimum RF supply voltage.
3. From a source independent of the baseband power management pins, e.g. the Main Battery node or a
totally independent voltage source.
In all 3 cases, the connections to VDD_3V and VDD_RF must be made according to the supply voltage range that
is actually supplied.
The RF supply voltage shall be free of noise and low frequency modulations.
There are two other LDOs in the RF unit providing improved supply rejection at very low dropout voltage for the
noise sensitive parts of the RF-circuits.
Insert a ferrite bead (FB1) to isolate the RF supply from digital noise.
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2.1.1.6 Built-in supply voltage monitors
Built-in supply voltage monitors ensure that the system always operates within safe limits. The following
conditions need to be met in order for the system to run properly:
1. The core voltages VDD_C and VDD_B need to be within specification. These voltages are supervised by
internal supply monitors.
2. The I/O voltage VDD_IO needs to be within specification. This voltage is supervised by an internal supply
monitor. This supply monitor has a system configurable threshold done automatically by the Firmware.
3. The RF supply voltage needs to be within specification. This voltage is supervised at pin V_RESET by an
internal supply monitor. The threshold of this supply monitor can be configured using the V_TH pin. If
V_TH is open, the threshold is set for a nominal supply voltage of 1.8 V, if this pin is connected to GND
the threshold is set for a nominal supply voltage of 2.5 V and above.
4. If external memory is used, its supply voltage, i.e. VDD_IO, needs to be within the specification of this
part.
With respect to points 2 and 3 listed above, the voltage that defines the lowest operational boundary condition
of the system shall be supervised at the V_RESET pin. This is usually the RF IC supply voltage (VDD_3V). In
designs using EEPROM memory it may also be VDD_IO. Normally, higher system supply voltages take longer to
rise and fall faster than lower supply voltages, e.g. if in a given application, the RF section requires 1.8 V but
external memory requires 2.7 V, it is advisable to monitor VDD_IO rather than VDD_3V.
With respect to item 4 above the design must ensure that VDD_IO is present and within the operating range of
the external memory at system boot time. Else, the system may fail in detecting the external memory and the
memory will be ignored.
Initially at system start-up, the threshold of the VDD_IO supply monitor is set to its lowest value in order to
ensure the system only starts when I/Os are operational. Once external memory is detected, the threshold will be
adapted according to memory type in order to detect brown-out conditions in case VDD_IO would drop below
the operational range of external memory. The following rules do apply:
1. In case of EEPROM at DDC interface, the VDD_IO threshold is set to 1.8V. All EEPROMs used with u-blox
6 must support operation down to 1.8V. Only EEPROM types listed in Table 14 must be used.
2. In case of Serial FLASH memory at SPI interface, VDD_IO threshold is set according to its type. Only
FLASH memory types listed in Table 15 must be used.
Internally, VDD_B and VDD_C are supervised by power-on reset circuits. Reset signals on backup and core
domains are only released once the respective supply voltages fall within the operational conditions.
After release of the power-on reset on circuit at VDD_C the systems waits for 2048 clock cycles to stabilize
before the clock signal is fed into the core. This ensures system operation only with a clean clock signal.
An additional monitor switches the supply of the back-up region VDD_B (RTC and backup RAM) from VDD_IO to
V_BCKP, once VDD_IO falls below its operational specification. Thus, a separate supply source can be used to
maintain RTC and backup RAM information even if VDD_IO fails. If this feature is not needed, V_BCKP must be
connected to GND.
2.1.1.7 USB interface power supply
VDD_USB supplies the I/Os of the USB interface. If the USB interface is not used, the VDD_USB pin must be
connected to GND.
If the USB interface is being used the system can be either self-powered, i.e. powered independently from the
USB bus, or it can be bus-powered, i.e. powered through the USB connection. In bus-powered mode, the system
supply voltages need to be generated from the USB supply voltage VBUS. See section 2.3.2.
If the application uses USB, the correct USB power mode needs to be configured (bus-powered or self
powered). See the u-blox 6 Receiver Description including Protocol Specification [1].
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BB 1.4 V / RF 1.8 V
BB 1.4 V / RF 2.5 V
Continuous
Acquisition
Continuous
Acquisition
Continuous
Acquisition
mA
mA
mW
mW
mW
mW
RF-IC
20
20
36
36
50
50
BB-IC
17
27
24
38
24
38
Total
37
47
60
74
74
88
Supply Voltage V
LDO [mW]
Single 1.8V DCDC Converter [mW]
1.8
67
83
2.5
93
83 3 111
83
3.3
122
83
4.2
155
83 5 185
83
2.1.2 Power management configuration
Depending on the application, the power supply schematic will differ. Some examples are shown in the
following sections:
Supply voltage nominal 3.3 V (2.5–3.6V) see section 2.1.5
Supply voltage nominal 1.8 V (1.75–2.0V) see section 2.1.6
Direct supply of core voltages (1.75–2.0V for RF part, 1.4–3.6V for digital part) see section 2.1.7
Dual power supply using 3.0V and 1.4V (VDD_3V 3.0 V, V_DCDC 1.4 V) see section 2.1.8
Use of external DCDC converter 1.8V (1.75–2.0V) see section 2.1.9
2.1.3 System power consumption
This chapter is targeted at the design and dimensioning of the system power supply. In order to analyze the
power consumption and supply currents for various scenarios, Table 1 lists the respective supply currents at the
minimum supply voltages which are 1.4V for the baseband part and 1.8V for the RF part. Table 1 further shows
the power consumption if the RF section needs to be supplied with 2.5V
Table 1: Raw Current and Power Consumption (ECO Mode, moderate signal levels)
Table 2 and Table 3 compare the approximate power consumption for the different scenarios and different
system supply voltages. Table 2 shows the continuous power consumption when the system has acquired all
satellites and is running in steady state. Table 3 shows the peak power consumption during signal acquisition.
These two cases allow assessing the dimensioning of peak power and continuous power capabilities of the
power supply circuit. The green and red highlighting illustrates the best and the worst solution in terms of power
consumption.
The following 2 scenarios are being compared:
1. Using linear regulators (LDO) only. For supply voltages up to 3.6 V the built-in LDOs of u-blox 6 can be
used. For higher supply voltages, an additional external LDO is needed. There is no effect on power
consumption or efficiency regardless whether external or built-in LDOs are being used.
2. Using an additional external single output voltage DC/DC converter to generate the intermediate system
supply voltage of 1.8V which then is further regulated by the individual LDOs of base-band and RF-IC.
The maximum system supply voltage is only limited by the external DC/DC converter being used.
For the DC/DC converter, an efficiency of 80% has been assumed in calculating the power values shown in
Table 2 and Table 3. If power-efficiency at high system supply voltages is key for the application, use of an ultrahigh efficiency external DC/DC converter such as Linear Technology’s LTC3410 (2.0 × 2.0 mm2 SC70 package) is
recommended.
Table 2: Continuous Tracking Power Consumption (ECO Mode)
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Supply Voltage [V]
LDO [mW]
Single 1.8V DCDC Converter [mW]
1.8
85
106
2.5
118
106 3 141
106
3.3
155
106
4.2
197
106 5 235
106
Pin
Function
Comments
V_DCDC
Main Core (VDD_C) Supply
Always needs input. The current consumption varies over time (peak currents).
Keep series resistance low to prevent ripple on the power supply.
VDD_3V
Main RF Supply
Supplied by 2.5…3.6V or connected to VDD_RF, depends on supply scheme.
VDD_IO
I/O Supply Voltage
Always needs to be supplied.
V_BCKP
Backup voltage (VDD_B) supply
Connect to GND if not used.
VDD_B
Backup Core Voltage
Leave open.
VDD_C
Main Core Voltage
Leave open.
VDD_RF
RF Core Supply Voltage
Leave open or must be supplied by 1.75…2.0V, depends on supply scheme.
In case of supplied by 1.75…2.0V it also has to be shorted to VDD_3V.
VDD_ANA
Analog Power
Leave open.
VDD_LNA
LNA Power Supply
Leave open.
V_RESET
RESET input
Connect to supervising voltage, mostly to VDD_3V (see 2.1.1.6)
V_TH
Sets Threshold for V_RESET
V_TH = open: V_RESET supervised voltage at nominal 1.8 V.
V_TH= GND: V_RESET supervised voltage at nominal 2.5 V and above.
DCDC_EN
Enable for external DCDC
converter
Leave open if not used. Otherwise connect to enable pin of external DCDC
converter.
VDD_USB
Supply for USB interface
Connect to GND if not used.
Table 3: Acquisition Power Consumption (ECO Mode)
Some conclusions from Table 1 to Table 3:
The most efficient solution is to have a direct 1.4 V / 1.8 V supply available from the system. The respective
application circuit is shown in section 2.1.7
If a 1.8V supply is available the best solution is to supply RF and BB part directly. The respective application
circuit is shown in section 2.1.6.
For supply voltages above 2.5 V, a DC/DC converter having a 1.8 V output voltage should be used for good
efficiency. The respective application circuit is shown in section 2.1.9.
Using only the built-in LDOs of u-blox 6 at supply voltages between 2.5 V and 3.6 V is not efficient but very
cost effective in terms of BoM. The respective application circuit is shown in section 2.1.5
2.1.4 How to connect the power supply pins
Table 4 lists the power supply pins and their connection requirements.
Table 4: Power Supply Pins
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2.1.5 Single 2.5…3.6 V supply
A single 3.0V power supply is very easy to design but is not the most efficient solution to run u-blox 6 receivers
(see section 2.1.3 for details).
Figure 4: Single 2.5…3.6 V supply.
2.1.6 Single 1.75…2.0 V supply
The single 1.8V power supply is a very efficient configuration to run u-blox 6 receivers (see section 2.1.3 for
details).
Figure 5: Single 1.75…2.0 V supply
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2.1.7 Separate supplies of 1.8 V (1.75…2.0V) and 1.4 V(1.4…3.6V)
The dual 1.8V and 1.4V power supply the most efficient configuration to run u-blox 6 receivers (see section
2.1.3 for details). It assures stability since the sensitive RF supply is well separated from the fluctuating base band
power supply.
Figure 6: Separate supplies of 1.8 V and 1.4 V
2.1.8 Separate supplies of 3.0 V (2.5…3.6V) and 1.4 V (1.4…3.6 V)
It assures a better stability than a single 3.0V power supply as the sensitive RF supply is well separated from the
fluctuating base band power supply.
Figure 7: Dual supplies of 3.0 V and 1.4 V
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2.1.9 External 1.8V DCDC converter
The external DCDC converter providing 1.8V is the most efficient solution for main supply voltages above 2.5V.
Figure 8: External 1.8V DCDC converter
2.1.10 Operating modes
The u-blox AMY-6M features one continuous operating mode (Eco Mode) Eco Mode
In Eco Mode, u-blox AMY-6M uses the acquisition engine to search for new satellites only when needed for
navigation:
In cold starts, u-blox AMY-6M searches for enough satellites to navigate and optimizes use of the acquisition
engine to download their ephemeris.
In non-cold starts, u-blox AMY-6M focuses on searching for visible satellites whose orbits are known from
the Almanac.
In Eco Mode, the u-blox AMY-6M acquisition engine limits use of its searching resources to minimize power
consumption.
u-blox AMY-6M deactivates the acquisition engine as soon as a position is fixed and a sufficient number (at least
4) of satellites are being tracked. The tracking engine continues to search and track new satellites without orbit
information.
Power Save Mode and Maximum Performance Mode are not supported by AMY-6M.
Power Save Mode requires an external RTC crystal to schedule system wake-up at pre-defined
intervals.
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2.1.11 Active antenna supply
With AMY-6M active antennas are supplied via an external coil or circuit. AMY-6M does not provide the antenna
bias voltage for active antennas on the RF_IN pin as other u-blox modules do. It is therefore necessary to provide
this voltage outside the module via an inductor as indicated in Figure 9. u-blox recommends using an inductor
from Murata (LQG15HS27NJ02). Alternative parts can be used if the inductor’s resonant frequency matches the
GPS frequency of 1575.42MHz.
Figure 9: Recommended wiring for active antennas
For C and L values see Component Selection Section B.
For optimal performance, it is important to place the inductor as close to the microstrip as possible. Figure
10 illustrates the recommended layout and how it should not be done.
Figure 10: Recommended layout for connecting the antenna bias voltage for AMY-6M
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2.2 System functions
2.2.1 EXTINT - external interrupt pin
EXTINT0 and EXTINT1 are external interrupt pins. It can be used for wake-up functions in low-power modes.
See the u-blox 6 Receiver Description including Protocol Specification [2].
2.2.2 System monitoring
The u-blox-6 GPS Receiver provides System Monitoring functions that allow the operation of the embedded
processor and associated peripherals to be supervised. These System Monitoring functions are being output as
part of the UBX protocol, class ‘MON’.
Please refer to the u-blox 6 Receiver Description including Protocol Specification [2]. For more information on
UBX messages, serial interfaces for design analysis and individual system monitoring functions.
2.2.3 Interference Monitor
New with firmware version 7 and above is the Interference Monitor feature. In contrast to the CW Jamming
Indicator, it is designed to detect both broad band and narrow band jammers. The receiver monitors the
background noise and reports any abnormal behavior.
For more information about the Interference Monitor refer to the u-blox 6 Receiver Description including
Protocol Specification [2].
2.3 Interfaces
u-blox AMY-6 receivers offer a number of different interfaces that can be used to connect to a host CPU: UART,
USB, DDC (I2C compatible), and SPI. Depending on the application any of these interfaces may be selected.
For debugging purposes it is recommended to have a second interface (unused by the actual application)
available on test-points.
New with firmware version 7 and above is the feature that each interface can define a corresponding pin, which
indicates if bytes are ready to be transmitted. The Tx-ready pin can be selected from all PIOs which are not in
use. Each Tx-ready pin is exclusively for one interface and cannot be shared.
See u-blox 6 Receiver Description including Protocol Specification [2] for description of the communication
protocols available at these interfaces and the respective configuration options.
2.3.1 UART
UART 1 (RxD1/TxD1) is the default serial interface. It supports data rates from 4.8 kbit/s to 115.2 kbit/s. An
interface based on RS232 standard levels (+/- 12 V) can be realized using external level shifters such as Maxim
MAX3232.
For the default settings on the messages on UART1 see the AMY-6M Data Sheet [1].
Hardware handshake signals and synchronous operation are not supported.
2.3.2 USB
The u-blox 6 USB interface supports the full-speed data rate of 12 Mbit/s.
2.3.2.1 USB external components
The USB interface requires some external components in order to implement the physical characteristics required
by the USB 2.0 specification. These external components are shown in Figure 11 and listed in Table 5.
In order to comply with USB specifications, VBUS must be connected through an LDO (U4) to pin VDD_USB of
the module.
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Name
Component
Function
Comments
U4
LDO
Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V.
Almost no current requirement (~1 mA) if the GPS receiver is operated as a USB
self-powered device, but if bus-powered LDO (U4) must be able to deliver the
maximum current of ~70 mA. A low-cost DC/DC converter such as LTC3410
from Linear Technology may be used as an alternative.
C23,
C24
Capacitors
Required according to the specification of LDO U4
D2
Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5
Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44 Ohms
A value of 22 Ohms is recommended.
R11
Resistor
Ensures a pull down when LDO
is disabled.
1k Ohms is recommended for USB self-powered setup. For bus-powered setup
R11 is not required.
FB1
Ferrite Bead
Filters Noise at GPS frequency
The AMY-6M can be either bus-powered or self-powered. Bus-powered means the AMY-6M is supplied by the
VBUS voltage from the USB. Self-powered means the AMY-6M is powered by another supply independent from
VBUS supply and just the USB interface VDD_USB is supplied by VBUS (through an LDO (U4)).
Depending on the characteristics of the LDO (U4) it is recommended to add a pull-down resistor (R11) at its
output to ensure VDD_USB is not floating if LDO (U4) is disabled or the USB cable is not connected i.e. VBUS is
not supplied.
All u-blox 6 receivers support both Bus and Self Powered Mode on the USB interface. Please be sure to use the
latest drivers from our website.
Connect VDD_USB to GND if not used. With config pin CFG_COM0 the AMY-6M can be set to Bus (CFG_COM1=open) or Self Powered
(CFG_COM1=GND)
USB is not compatible with Power Save Mode with FW6.02 and below
Figure 11: USB Interface (bus powered setup)
Table 5: Summary of USB external components
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Load Capacitance
Pull-Up Resistor Value R20, R21
50 pF
N/A
100 pF
18 k
250 pF
4.7 k
2.3.3 Display Data Channel (DDC)
An I2C compatible Display Data Channel (DDC) interface is available for serial communication. For more
information about DDC implementation refer to the u-blox 6 Receiver Description including Protocol Specification [2]. Background information about the DDC interface is available in Appendix C.1.
u-blox 6 GPS receivers normally run in I
EEPROM is used to store configuration, at this time no other nodes may be connected to the bus. In this
case, the receiver attempts to detect the EEPROM by writing and reading from a specific location.
Pins SDA2 and SCL2 have internal pull-ups. These pull-up resistors integrated in the pads of the baseband-IC are
sufficient for most applications. However, for high capacitive loads, parallel external pull-up resistors need to be
added. Table 6 lists the externally required pull-up resistor values for the DDC interface.
Table 6: Pull-up resistor values for DDC interface
2
C slave mode. Master Mode is only supported when external
2.3.3.1 Communicating to an I
2
C EEPROM with the GPS receiver as I2C master
Serial I2C memory can be connected to the DDC interface as shown in Figure 12. This can be used to
permanently save configuration settings. It will automatically be recognized by firmware. The memory address
must be set to 0b10100000 see Figure 12 (A0, A1 and A2 must be connected to GND), and the size must be to
4 kByte (32 kBit).
The AMY-6M monitors the supply voltage VDD_IO. This implies the I2C EEPROM is operating above the VDD_IO
threshold defined for I2C EEPROM operation (see Section 2.1.1.6).
Only use I
2
C EEPROM types listed in Table 14
Figure 12: Connecting external serial I2C memory used by the AMY-6M to save configuration (see EEPROM data sheet for exact
pin orientation)
In limited cases u-blox 6 GPS receivers can fail to correctly write to external I
successful storage of the configuration into external I2C EEPROM, the writing cycles need to be verified by a
read cycle (see u-blox 6 firmware version 7 Release Notes [5] for details).
2.3.3.2 Communicating as I
An I2C master can communicate with the AMY-6M through the DDC interface.
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2
C EEPROM. To guarantee
2
C slave to a host
AMY-6M - Hardware Integration Manual
Figure 13: Connecting external serial I2C memory used by external host (see data sheet for exact pin orientation)
Note that the case shown on Figure 12 is different than the case when EEPROM is present but used by external
host / CPU as indicated on Figure 13. This is allowed but precaution is required to ensure that the GPS receiver
does not detect the EEPROM device, which would effectively configure the GPS receiver to be MASTER on the
bus causing collision with the external host.
To ensure that the EEPROM device (connected to the bus and used by the host) is not detected by the GPS
receiver it is important to set the EEPROM’s address to a value different than 0b10100000. This way EEPROM
remains free to be used for other purposes and the GPS receiver will assume the SLAVE mode.
Ensure that at the start up the host allows enough time for the receiver to communicate over the bus to
establish presence of the EEPROM. It is only when this interrogation is complete that the host can exercise
full control over the bus (MASTER mode).
The AMY-6M always interrogates external EEPROM at the start-up. The interrogation process is guaranteed
to complete within 250ms upon start up. This is the time the external host has to give to the ROM based
GPS receiver to complete the EEPROM interrogation.
The AMY-6M DDC interface supports serial communication with u-blox wireless modules. See the
specification of the applicable wireless module to confirm compatibility.
TX ready signal (data ready to be picked up) can be activated, for configuration see 2.4.1.3.
2.3.4 SPI
A Serial Peripheral Interface (SPI) is available. The SPI allows for the connection of external devices with a serial
interface, e.g. FLASH memories or A/D converters, or to interface to a host CPU. Background information about
the SPI interface is available in Appendix C.2.
2.3.4.1 Connecting SPI FLASH memory
SPI FLASH memory can be connected to the SPI interface to save AssistNow Offline data and/or receiver
configuration. It will automatically be recognized by firmware when connected to SS_N.
Figure 14 shows how external memory can be connected. Note that an external voltage is required to power the
FLASH (VDD_IO on the receiver is an input). Minimum SPI FLASH memory size is 1 Mbit.
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Figure 14: Connecting external SPI Memory to AMY-6M
Only use Serial FLASH types listed in Table 15. It is not recommended to use Serial Flash at SPI for new designs. The SPI signals at AMY-6M are at VDD_IO voltage levels. VDD_IO must be supplied with same voltage as
external serial FLASH.
2.3.4.2 Detection of SPI serial FLASH
The AMY-6M only detects the serial FLASH if all the SPI pins (CLK, SS_N, MOSI and MISO) are high. This is the
case if only the serial FLASH is connected to the SPI interface pins.
Figure 15: Detection of SPI FLASH memory
2.3.4.3 SPI communication (connecting to an SPI host/master)
Figure 16 shows how to connect an AMY-6M to a host/master. The signal on the pins must meet the conditions
specified in the Data Sheet.
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AMY-6M - Hardware Integration Manual
Component
Description
Model
Supplier
U1 – U3
Buffer
NC7SZ125
Fairchild
Figure 16: Connecting to SPI Host/Master
With AMY-6M the SPI MOSI, MISO and SCK pins share a configuration function at start up. Afterwards the
SPI function will not affect the configuration pins. This might be difficult in case several slaves are
connected to the host. In this case the problem can be solved as shown in Figure 17 by making sure the
SS_N is high when the receiver starts up.
The SPI signals at AMY-6M are at with VDD_IO voltage levels. VDD_IO must be supplied with the same
voltage as the host processor.
TX ready signal (data ready to be picked up) can be configured, see 2.4.1.3.
2.3.4.4 Pin configuration with module as one of several slaves
Figure 17: Diagram of SPI Pin Configuration
Figure 18: Recommended components for SPI pin configuration
Use same power voltage to supply U
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– U3 and VDD_IO.
1
AMY-6M - Hardware Integration Manual
2.4 I/O Pins
2.4.1 Peripheral Input Output (PIO)
All PIOs have internal pull-ups or pull-downs (PIO9 only). Thus there is no need to connect PIOs to GND or VDD if
not used.
A signal change on pins RXD1, EXTINT0, or EXTINT1 can also be used to wake up the receiver from Sleep- or
Backup Mode.
2.4.1.1 PIO23
It is a requirement that pin PIO23 is connected to GND.
Always connect PIO23 to GND!
2.4.1.2 PIO21/SCK
Pin PIO21 is shared with the SPI clock pin SCK. PIO21 must be connected to GND if the SPI interface is not used.
To use the SPI interface PIO21 must be pulled to a low level during startup. This can be done with a 10k Ohm
pull down resistor to GND, see Figure 16. PIO21 must not be left open.
If SPI isn’t used, connect PIO21/SCK to GND.
2.4.1.3 TX Ready (ROM7.03 and above)
The TX ready signal indicates that the receiver has data to transmit. A listener can wait on the TX ready signal
instead of polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you configure the polarity and the
number of bytes in the buffer before the TX ready signal goes active. The TX ready signal can be mapped to
GPIO 05 (TXD1). The TX ready pin is disabled by default.
Most u-blox wireless modules configure and enable the TX ready functionality automatically at GPIO 05
(TXD1) of AMY-6M. See datasheet of the wireless module.
For more information on configuration and remap of this pin see the AMY-6M Data Sheet [1] and see also the
u-blox 6 Receiver Description including Protocol Specification [2].
2.4.2 SAFEBOOT_N
Design a test point to access SAFEBOOT_N in the PCB design. If SAFEBOOT_N is low at start-up, the receiver
starts in a Safe Boot Mode and the GPS navigation engine is not started. This mode can be used for production
test.
Safe Boot Mode can be used to force the system into a known state regardless of any configuration pins or
contents of non-volatile memories. This can be used to recover from a situation where a non-volatile memory
was programmed with wrong settings. Since in Safe Boot Mode only a limited number of configurations are
available the same restriction may apply as mentioned before with regards to un-programmed non-volatile
memory, i.e. baud rates may be wrong or USB may not be functional.
Have at least one test-point available that allows setting pin SAFEBOOT_N to GND. This recommendation
should always be followed if external non-volatile memory is used in the application.
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D et ec t io n o f m em orie s
SYS T E M R U N N ING
Fu n c tio n al C o n fig u ra tionLo w L e ve l C o nf ig ur a tio n
S T AR T O F S YS T E M
2.5 System Configuration
2.5.1 Configuration at start-up
At start-up, the configuration of the system is performed in two steps: First the so-called Low Level
Configuration is applied, and then the Functional Configuration is carried out. In between those two steps, the
non-volatile memories are detected. See Figure 19 for an overview.
Figure 19: Configuration at start-up
2.5.1.1 Low Level Configuration
The Low Level Configuration provides some basic configuration information such as GPS mode or reference
clock frequency. This information can be supplied in different ways. However, not all of them are available in
every setup. The options are:
ROM Defaults: Default settings of the integrated ROM Code. See AMY-6M Data Sheet [1].
CFG Pins: The settings of CFG_COM0/MOSI and CFG_COM1/MISO during boot sequence.
Figure 20: Low level configuration sequence
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2.5.1.2 Functional Configuration
After the Low Level Configuration has been applied the Functional Configuration is executed. The Functional
Configuration offers a wide range of information like the configuration of the ports and the messages, the
navigation engine settings and the NMEA protocol configuration. This information can be stored on the
following non-volatile memories:
On-chip battery backed RAM (BBR), (V_BCKP supplied by backup battery)
External serial EEPROM, connected to the DDC (Section 2.3.3.1)
External serial FLASH memory, connected to the SPI (Section 2.3.4.1)
Figure 21 shows the sequence of the Functional Configuration.
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2.5.2 Configuration at runtime
Once the receiver has started, the Functional Configuration may be modified with UBX configuration messages.
The modified settings remain effective until power-down or reset. If these settings have been stored in nonvolatile memory as the EEPROM at DDC or the serial FLASH at SPI, the modified configuration will be retained. If
these settings have been stored in battery-backup RAM, then the modified configuration will be retained, as
long as the backup battery supply is not interrupted. See chapter “Receiver Configuration” in the u-blox 6 Receiver Description including Protocol Specification [2] for more information.
The configuration pins (CFG_COM0 and CFG_COM1) are shared with other functions (SPI interface pins MOSI
and MISO). During start-up, the module first reads the state of the configuration pins. Afterwards the other
functions can be used.
For more information about settings and messages see the AMY-6M Data Sheet [1].
2.6 RTC
The RTC crystal is optional as it is only required in stand-alone applications where hot or warm starts are
enabled. In these cases, actual time is maintained in the RTC and Ephemeris and other last known data is kept in
the backup RAM. In A-GPS based systems, the RTC is not required and coarse or fine time information is
available from the network. If neither backup RAM nor RTC are required, V_BCKP should be connected to GND.
The external circuit for normal RTC operation is shown in Figure 2.
If the RTC is not used, its input XTAL_IN should be connected to GND and the output XTAL_OUT must be left
open.
As an alternative to the RTC, a 32 kHz signal can be supplied from an external source (e.g. from the host system)
into XTAL_IN. This is a core domain signal; its high level must not exceed VDD_B (1.2V!). If the output buffer of
the RCT signal from host does exceed the VDD_B voltage, with a voltage divider (Rx and Ry) the voltage level can
be adjusted, see Figure 22. Minimum “high” level should be more than 0.8V.
Figure 22: RTC supplied by external source
RTC is highly recommended for Power Save Mode. If AssistNow Autonomus is required, RTC is mandatory if the time at wakeup of receiver is not provided by
message (UBX-AID-INI). For more deatails see u-blox 6 Receiver Description including Protocol Specification
[2].
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AMY-6M - Hardware Integration Manual
2.7 RF input
The AMY-6M RF input is already matched to 50 Ohms and has an internal DC block, see Figure 1. To achieve the
performance values as written in AMY-6M Data Sheet [1] an active antenna with a good LNA inside or the
mandatory LNA in front of AMY-6M must have below 1dB noise figure.
2.7.1 Active Antenna used
In case an active antenna is used, just the active antenna supply circuit has to be added in front of AMY-6M RFinput. See section 2.1.11. In case the active antenna has to be supervised, the Active Antenna Supervisor circuit,
see section 2.8, has to be added to the active antenna circuit. This Active Antenna Supervisor circuit also makes
sure the active antenna is turned off in some Power Save Mode stages.
2.7.2 Passive Antenna
In case no active antenna is connected to the AMY-6M it is mandatory to use an additional LNA in front of
AMY-6M. An LNA (LNA1) alone would make the AMY-6M more sensitive to outband jammers, so an additional
GPS SAW filter (F2) has to be connected between the external LNA (LNA1) and the AMY-6M RF-input.
Figure 23: Recommended passive antenna design
PIO17 can be configured as ANTOFF (active antenna off) signal which can be used to turn off an external LNA.
The ANTOFF signal must be inverted for common LNAs which come with an enable pin which has be “low” to
turn off. To configure PIO17 as ANTOFF, see u-blox 6 Receiver Description including Protocol Specification [2].
2.7.3 Increased Jamming Immunity
If strong outband jammers are close to the GPS antenna (e.g. a GSM antenna) GPS performance can be
decreased or the maximum input power of the AMY-6M RF-input can be exceeded. An additional SAW filter has
to put in front of the external LNA (LNA1). If the external LNA (LNA1) can accept the maximum input power, the
SAW filter between the passive antenna and external LNA (LNA1) might not be necessary. This results in a better
noise figure than an additional SAW filter in front of the external LNA (LNA1).
Figure 24: Recommended circuit for increased jamming immunity
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AMY-6M - Hardware Integration Manual
op t ion al
V _ A N T
A M Y - 6M
PIO 0 8 / E X TIN T 1
R34
PIO 1 7
PIO 1 8
R38
R39
R30
R31
to a nt en na in pu t
U3 2 .1
U3 2 .2
V _ A N T
V D D_ IO
V D D_ IO
T 31
U3 1
Function
Input/Output
Pin
Antenna off
Output
PIO17
Antenna detection
Input
PIO8/EXTINT1
Antenna short circuit detection
Input
PIO18
2.8 Active antenna supervisor
u-blox 6 firmware supports an active antenna supervisor circuit, which can be connected to AMY-6M via pins
PIO08/EXTINT1, PIO17, and PIO18. The external components shown in Figure 25 detect whether an active
antenna is connected, i.e. if the DC supply current exceeds a threshold defined by R34, R38, and R39, or if a
short circuit of the antenna supply has occurred. It will shut down the antenna via transistor T31 if it’s not
needed or if a short circuit has been detected.
Figure 25: Active antenna supervisor circuit
Equation 1 Calculation of antenna supervisor current (I
Equation 1 shows the calculation of the antenna supervisor current I
)
ANT
. In case antenna supply voltage V_ANT
ANT
exceeds VDD_IO, open drain buffers U32 (e.g. Fairchild NC7WZ07) and resistors R31 and R30 are required to
maintain control on T31 as well as to avoid leakage currents into the internal pull-ups of pins PIO8/EXTINT1 and
PIO18.
R34 serves as a current limiter in case of a short circuit.
The three I/Os used for the Antenna Supervisor function are assigned using protocol messages. See u-blox 6
Receiver Description including Protocol Specification [2]
Table 7 shows the functions of the antenna supervisor pins.
Table 7: Assignments of the antenna supervisor function
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AMY-6M - Hardware Integration Manual
2.9 Use RESET input
AMY-6M doesn’t come with a RESET_N pin. However, a RESET_N input pin functionality can be implemented by
adding a 3k3 resistor in the line to V_RESET, which usually supervises the RF part supply, see Figure 26. Then by
driving this Reset input “low” with an open drain buffer, the system is held in a reset state.
Don’t drive this Reset input high! Only drive low or with high impedance (open drain output device).
The open drain buffer connected to the Reset input signal must be able to draw around 1mA to GND. Do not
use a higher value than 3k3 Ohm, otherwise the V_RESET threshold will be affected.
Figure 26: Reset input circuit for a single 3V power supply design
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2.10 Design-in checklist
2.10.1 Schematic design-in checklist for AMY-6M
Check power supply requirements and schematic:
Is the power supply voltage within the specified range? See how to connect power in Section 2.1.
For USB devices: Is the voltage VDDUSB voltage within the specified range? Do you have a Bus or Self
powered setup?
Compare the peak current consumption of AMY-6M with the specification of your power supply.
GPS receivers require a stable power supply. Avoid series resistance in your power supply line (the line to
V_DCDC) to minimize the voltage ripple on V_DCDC and VDD_3V.
Backup battery
For achieving a minimal Time To First Fix (TTFF) after a power down (warmstarts, hotstarts), make sure to
connect a backup battery to V_BCKP, and use an RTC. If not used, make sure V_BCKP is connected to GND.
Antenna/ RF input
The total noise figure including external LNA (or the LNA in the active antenna) should be around 1dB.
With AMY-6M an external LNA is mandatory if no active antenna is used.
Make sure the antenna is not placed close to noisy parts of the circuitry and not facing noisy parts. (e.g.
micro-controller, display, etc.)
To optimize performance in environments with out-band jamming/interference sources, use an additional
SAW filter.
For more information dealing with interference issues see the GPS Antenna Application Note [3].
Schematic
Pins C9 (PIO21) and E8 (PIO23) must be connected to GND. If SPI is used PIO23 should have a 10k
Ohm pull down resistor.
V_RESET connected to VDD_3V.
For a 3V single power supply connect V_TH to GND.
2.10.2 AMY-6M design
For a minimal Design with AMY-6M the following functions and pins need to be considered:
Connect the Power supply to V_DCDC, VDD_IO, VDD_3V, V_BCKP.
VDDUSB: Connect the USB power supply to a LDO before feeding it to VDDUSB and V_DCDC or connect to
GND if USB is not used.
Ensure an optimal ground connection to all ground pins of the AMY module
Choose the required serial communication interface (USART, USB, SPI or DDC) and connect the appropriate
pins to your application
If you need Hot- or Warmstart in your application, connect a Backup Battery to V_BCKP and add RTC circuit.
If antenna bias is required see section 2.1.11.
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AMY-6M - Hardware Integration Manual
2.10.3 Minimal schematic for AMY-6M
This is a minimal schematic for a PVT GPS receiver with an AMY-6M module.
It is a 3V main supply design (2.5…3.6V) for an active antenna running with main supply voltage. Also Backup
part is supplied and RTC connected. Thus Warmstarts and Hotstarts are supported. Communication is UART with
main supply voltage levels. Default messages and baudrate are chosen.
Figure 27: Typical schematic of a 3V design for an active antenna (not shown pins have to be left open)
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2.10.3.1 Pin description for AMY-6M design
Standard Function
Remarks
No
Name
I/O
Description
A1
RF_IN
I
RF Input
Add external LNA and SAW if no active antenna used.
A2
GND I Ground
A3
NC
A4
GND I Ground
A5
XTAL_OUT
O
RTC Output
Leave open if no RTC Crystal attached.
A6
XTAL_IN
I
RTC Input
Connect to GND if no RTC Crystal attached.
A7
VDD_LNA
O
LNA Power Supply
Leave open.
A8
VDD_ANA
O
Analog Power
Leave open.
A9
VDD_RF
I/O
Core Power
See section 2.1
B1
GND I Ground
B2
GND I Ground
B3
Reserved
I/O
Reserved
Do not connect. Must be left open!
B4
GND I Ground
B5
GND I Ground
B6
GND I Ground
B7
V_TH
I
V_RESET Threshold
Leave open or connect to GND. See section 2.1
B8
GND I Ground
B9
VDD_USB
I
USB Interface Power
Connect to GND if not used.
C1
PIO8 / EXTINT1
I
External Interrupt /Alternative function
Leave open if not used.
C2
Reserved
I/O
Reserved
Do not connect. Must be left open!
C7
USB_DM
I/O
USB data
Leave open if not used.
C8
PIO18
I
Alternative function, see 2.8
Leave open if not used.
C9
PIO21/ SPI SCK
I/O
Reserved/ SPI Clock
Must be connected to GND if SPI is not used!
D1
PIO7/ EXTINT0
I
External Interrupt / Time Mark
Leave open if not used.
D2
Reserved
I/O
Reserved
Do not connect. Must be left open!
D7
USB_DP
I/O
USB data
Leave open if not used.
D8
V_RESET
I
Supply Monitor
Connect to VDD_3V. See section 2.1
D9
VDD_3V
I
Main RF Supply
See section 2.1
E1
Reserved
I
Reserved
Do not connect. Must be left open!
E2
Reserved
I
Reserved
Do not connect. Must be left open!
E8
PIO23
I/O
Reserved
Always connect to GND!
E9
VDD_B
O
Backup Power
Leave open.
F1
TIMEPULSE
O Leave open if not used.
F2
GND I Ground
F3
PIO17
I/O
Alternative function, see 2.7 and 2.8
Leave open if not used.
F4
CFG_COM0/ MOSI
I/O
Configuration Pin/ SPI MOSI
Leave open if not used.
F5
CFG_COM1/ MISO
I/O
Configuration Pin/ SPI MISO
Leave open if not used.
F6
SS_N
I/O
SPI Chip Select
Leave open if not used.
F7
Reserved
I/O
Reserved
Do not connect. Must be left open!
F8
GND I Ground
F9
V_DCDC
I
Main Core Supply
1.4-3.6V
G1
VDD_IO
I
I/O Supply
1.65-3.6V
G2
SAFEBOOT_N
I
Boot Mode Selection
Leave open if not used.
G3
SCL2
I/O
DDC for peripherals
Leave open if not used.
G4
SDA2
I/O
DDC for peripherals
Leave open if not used.
G6
TxD1 O Asynchronous Serial
Leave open if not used.
G6
RxD1 I Asynchronous Serial
Leave open if not used.
G7
V_BCKP
I
Backup voltage supply
1.4-3.6V (optional). Connect to GND if not used.
G8
VDD_C
O
Core Power
Leave open.
G9
DCDC_EN
O
Enable for external DCDC-converter
Leave open if not used.
AMY-6M - Hardware Integration Manual
Table 8: Pinout AMY-6M
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2.11 Layout design-in checklist
Follow this checklist for the layout design to get an optimal GPS performance.
Layout optimizations (Section 2.12)
Is the AMY-6M placed according to the recommendation in Section 2.12.3?
Is the Grounding concept optimal?
Has the 50 Ohm line from antenna to AMY-6M (micro strip/coplanar waveguide) been kept as short as
possible?
Assure low serial resistance in V_DCDC power supply line (choose a line width >400um)
Keep power supply line as short as possible
Design a GND guard ring around the optional RTC crystal lines and GND below the RTC circuit.
Add a ground plane underneath the GPS module to reduce interference. Especially for the RF input line.
For improved shielding, add as many vias as possible around the micro strip/coplanar waveguide, around the
serial communication lines, underneath the GPS module etc.
Calculation of the micro strip for RF input
The micro strip/coplanar waveguide must be 50 Ohms and be routed in a section of the PCB where minimal
interference from noise sources can be expected. Make sure around the RF line is only GND as well as under
the RF line.
In case of a multi-layer PCB, use the thickness of the dielectric between the signal and the 1st GND layer
(typically the 2nd layer) for the micro strip/coplanar waveguide calculation.
If the distance between the micro strip and the adjacent GND area (on the same layer) does not exceed 5
times the track width of the micro strip, use the “Coplanar Waveguide” model in AppCad to calculate the
micro strip and not the “micro strip” model.
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2.12 Layout
This section provides important information for designing a reliable and sensitive GPS system.
GPS signals at the surface of the Earth are about 15dB below the thermal noise floor. Signal loss at the antenna
and the RF connection must be minimized as much as possible. When defining a GPS receiver layout, the
placement of the antenna with respect to the receiver, as well as grounding, shielding and jamming from other
digital devices are crucial issues and need to be considered very carefully.
2.12.1 Footprint
Figure 28: Recommended footprint (top view)
Units in are in mm.
2.12.2 Paste mask
The paste maskshall be 50µm smaller than the copper pads with a paste thickness of 100µm.
The paste mask outline needs to be considered when defining the minimal distance to the next component. These are recommendations only and not specifications. The exact geometry, distances, stencil thicknesses
and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the
customer.
2.12.3 Placement
A very important factor in achieving maximum GPS performance is the placement of the receiver on the PCB.
The connection to the antenna must be as short as possible to avoid jamming into the very sensitive RF section.
Make sure that RF critical circuits are clearly separated from any other digital circuits on the system board. To
achieve this, position the receiver digital part towards your digital section of the system PCB. Care must also be
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AMY-6M - Hardware Integration Manual
exercised with placing the receiver in proximity to circuitry that can emit heat. The RF part of the receiver is very
sensitive to temperature and sudden changes can have an adverse impact on performance.
AMY-6M receivers are temperature sensitive devices. Avoid high temperature drift and air vents
near the receiver.
2.13 Migration considerations
The main difference between u-blox AMY-5M and u-blox AMY-6M from migration point of view is that the 3
pins EXTINT0 (PIO7), EXTINT1 (PIO8) and RXD1 (PIO4) have moved from the backup (VDD_B) domain to the IO
(VDD_IO) domain and these 3 pins now have an internal pull-up to VDD_IO.
As a consequence the following things must be considered when migrating from an existing u-blox 5 design to
u-blox 6.
The external series resistors in the USB_DM nd USB_DP lines have changed from 27 Ohm to now 22 Ohm.
Change series resistors in USB_DM and USB_DP line to 22 Ohm
The signal levels for RxD1, EXTINT0 and EXTINT1 are now related to VDD_IO and have the same input
levels as all the other IOs. There is no longer any exception for the signal input levels for RxD1, EXTINT0
or EXTINT1.
External pull-ups or pull-downs at RxD1, EXTINT0 and EXTINT1 must be removed. u-blox AMY-6M has
internal pull-ups to VDD_IO at RxD1, EXTINT0 and EXTINT1.
If RxD1, EXTINT0 and EXTINT1 were connected to GND on the u-blox 5 design, this will result in
increased current for u-blox 6 in SW backup mode. For example if VDD_IO is 3 V, RxD1 is used for
communication and EXTINT0/ EXTINT1 are connected to GND, then there will be an increased current of
about 2 * VDD_IO/pullup = 2 * 3 V / 113k Ohm = 53μA.
For u-blox 5 designs with RxD1, EXTINT0 or EXTINT1 connected directly to VDD_B, the layout cannot be
directly migrated to u-blox AMY-6M and must be modified.
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Abbreviation
Definition
ANSI
American National Standards Institute
CDMA
Code Division Multiple Access
EMC
Electromagnetic compatibility
EMI
Electromagnetic interference
EOS
Electrical Overstress
EPA
Electrostatic Protective Area
ESD
Electrostatic discharge
GND
Ground
GPS
Global Positioning System
GSM
Global System for Mobile Communications
IEC
International Electrotechnical Commission
PCB
Printed circuit board
2.14 EOS/ESD/EMI precautions
When integrating GPS receivers into wireless systems, careful consideration must be given to electromagnetic
and voltage susceptibility issues. Wireless systems include components which can produce Electrostatic Discharge
(ESD), Electrical Overstress (EOS) and Electro-Magnetic Interference (EMI). CMOS devices are more sensitive to
such influences because their failure mechanism is defined by the applied voltage, whereas bipolar
semiconductors are more susceptible to thermal overstress. The following design guidelines are provided to help
in designing robust yet cost effective solutions.
To avoid overstress damage during production or in the field it is essential to observe strict
EOS/ESD/EMI handling and protection measures.
To prevent overstress damage at the RF_IN of your receiver, never exceed the maximum input
power as specified in AMY-6M Data Sheet [1].
2.14.1 Abbreviations
Table 9: Explanation of abbreviations used in this section
2.14.2 Electrostatic Discharge (ESD)
Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between
two objects at different electrical potentials caused by direct contact or induced by an
electrostatic field. The term is usually used in the electronics and other industries to describe
momentary unwanted currents that may cause damage to electronic equipment.
2.14.3 ESD protection measures
GPS receivers are sensitive to Electrostatic Discharge (ESD). Special precautions are required when
handling.
Most defects caused by ESD can be prevented by following strict ESD protection rules for production and
handling. When implementing passive antenna patches or external antenna connection points, then additional
ESD measures as shown in Figure 29 can also avoid failures in the field.
UBX-17021971 – R07 Design-in
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AMY-6M - Hardware Integration Manual
Passive antennas
Active Antennas
A
RF_ IN
G P S
Re c e iver
L N A
B
D
RF_IN
G P S
R e c eiver
LNA with appropriate ESD rating
(see Table 10)
Passive antennas
Active Antennas (without internal filter
which need the module antenna supervisor
circuits)
C
RF_ IN
G P S
Re c e iver
L N A
G PS
B an d p a ss
Fi ltle r
D
LNA with appropriate ESD
rating and maximum input
power (see Table 10)
Figure 29: ESD Precautions
2.14.4 Electrical Overstress (EOS)
Electrical Overstress (EOS) usually describes situations when the maximum input power exceeds the maximum
specified ratings. EOS failure can happen if RF emitters are close to a GPS receiver or its antenna. EOS causes
damage to the chip structures.
If the RF_IN is damaged by EOS, it’s hard to determine whether the chip structures have been damaged by ESD
or EOS.
2.14.5 EOS protection measures
EOS protection measures as shown in Figure 30 are recommended for any designs combining wireless
communication transceivers (e.g. GSM, GPRS) and GPS in the same design or in close proximity.
Figure 30: EOS and ESD Precautions
2.14.6 Electromagnetic Interference (EMI)
Electromagnetic interference (EMI) is the addition or coupling of energy released from any RF emitting device.
This can cause a spontaneous reset of the GPS receiver or result in unstable performance. Any unshielded line or
segment (>3mm) connected to the GPS receiver can effectively act as antenna and lead to EMI disturbances or
damage.
The following elements are critical regarding EMI:
UBX-17021971 – R07 Design-in
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AMY-6M - Hardware Integration Manual
TX
RX
G PS
R e c eive r
FB
FB
B LM 1 5 H D1 0 2 S N1
> 10 m m
Unshielded connectors (e.g. pin rows etc.)
Weakly shielded lines on PCB (e.g. on top or bottom layer and especially at the border of a PCB)
Weak GND concept (e.g. small and/or long ground line connections)
EMI protection measures are recommended when RF emitting devices are near the GPS receiver. To minimize the
effect of EMI a robust grounding concept is essential. To achieve electromagnetic robustness follow the standard
EMI suppression techniques.
Improved EMI protection can be achieved by inserting a resistor or better yet a ferrite bead (BLM15HD102SN1)
into any unshielded PCB lines connected to the GPS receiver. Place the resistor as close as possible to the GPS
receiver pin.
Example of EMI protection measures on the RX/TX line using a ferrite bead:
Figure 31: EMI Precautions
VCC can be protected using a feed thru capacitor. For electromagnetic compatibility (EMC) of the RF_IN pin refer
to section 2.14.5
2.14.7 GSM applications
GSM uses power levels up to 2W (+33dBm). Make sure that absolute maximum input power level of GPS
receiver is not exceeded. See AMY-6M Data Sheet [1].
2.14.7.1 Isolation between GPS and GSM antenna
In a handheld type design an isolation of approximately 20dB can be reached with careful placement of the
antennas. If such isolation can’t be achieved, e.g. in the case of an integrated GSM/GPS antenna, an additional
input filter is needed on the GPS side to block the high energy emitted by the GSM transmitter. Examples of
these kinds of filters would be the SAW Filters from Epcos (B9444 or B7839) or Murata.
2.14.7.2 Increasing interference immunity
Interference signals come from in-band and out-band frequency sources.
2.14.7.3 In-band interference
With in-band interference the signal frequency is very close to the GPS frequency of 1575 MHz (see Figure 32).
Such interference signals are typically caused by harmonics from displays, micro-controller, bus systems, etc.
UBX-17021971 – R07 Design-in
Page 38 of 57
152515501625
GPSinputfilter
characteristics
15751600
0
-1 10
Jammin
gsignal
152515501625
Fre qu ency [MHz ]
Power [dBm]
G P S in pu t f ilte r
c ha r ac t e ris ti cs
15751600
0
Int erferen ce
sign al
GPS
sign als
GPS C arrier
15 75.4 MHz
Figure 32: In-band interference signals
0500100015002000
GPSinputfilter
characteristics
0
-1 10
050015002000
Fre qu ency [MHz ]
GSM
900
GSM
1800
GSM
1900
Power [dBm]
G P S in pu t f ilte r
c ha r ac t e ris ti cs
GPS
1575
0
-1 10
GPS
sign als
GSM
950
AMY-6M - Hardware Integration Manual
Figure 33: In-band interference sources
Measures against in-band interference include:
Maintaining a good grounding concept in the design
Shielding
Layout optimisation
Filtering
Placement of the GPS antenna
Adding a CDMA, GSM, WCDMA bandbass filter before handset antenna
2.14.7.4 Out-band interference
Out-band interference is caused by signal frequencies that are different from the GPS carrier (see Figure 34). The main
sources are wireless communication systems such as GSM, CDMA, WCDMA, WiFi, BT, etc..
Figure 34: Out-band interference signals
UBX-17021971 – R07 Design-in
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AMY-6M - Hardware Integration Manual
Manufacturer
Part ID
Remarks
Parameters to consider
Diode
ON Semiconductor
ESD9R3.3ST5G
ESD9L3.3ST5G
ESD9L5.0ST5G
(2.14.3 B) Standoff Voltage>3.3V
(2.14.3 B) Standoff Voltage>3.3V
(2.14.3 B) Standoff Voltage>5V
• Low Capacitance < 0.5pF
• Standoff Voltage > Voltage for
active antenna
• Low Inductance
SAW
Epcos
B9444: B39162-B9444-M410
B7839: B39162-B7839-K410
(2.14.5) 15dBm Max Power
Input
(2.14.5) 25dBm Max Power
Input
Murata
SAFEA1G57KD0F00
SAFSE1G57KA0T90
(2.14.5) 1.35x1.05x0.5 mm
(2.14.5) 2.5x2.0x1.0 mm
• Low-loss RF filter for GPS
• Unbalanced to unbalanced
operation
• Insertion Loss
• Bandwidth and BW over
temperature
• Electrostatic Sensitive Device
(ESD MM)
CTS
CER0032A
(2.14.5) 4.2x4.0x2.0 mm
> 8kV ESD HBM
LNA
Avago
ALM-1106
ALM-1412
ALM-1712
ALM-2412
(2.14.3 A) LNA
(2.14.5 C) LNA + FBAR Filter
(2.14.5 C) Filter + LNA + FBAR
Filter
(2.14.3 A) LNA + FBAR Filter
pHEMT (GaAS)
MAXIM
MAX2659ELT+
(2.14.3 A) LNA
SiGe
Inductor
Murata
LQG15HS27NJ02
Impedance @ freq GPS > 500
Ohm
Capacitor
Murata
GRM1555C1E470JZ01
(2.14.5 D) C, 47p
Ferrite
Bead
Murata
BLM15HD102SN1
(2.14.5 D) FB
High IZI @ fGSM
Feed thru
Capacitor
for Signal
Murata
NFL18SP157X1A3
NFA18SL307V1A45
Monolithic Type
Array Type
Load Capacitance appropriate to
Baude rate
CL < xxx pF
Feed thru
Capacitor
for VCC
Murata
NFM18PC
NFM21P
0603 2A
0805 4A
Rs < 0.5 Ohm
Measures against out-band interference include maintaining a good grounding concept in the design and
adding a SAW or bandpass ceramic filter (as recommend in Section 2.14.5) into the antenna input line to the
GPS receiver (see Figure 35).
Figure 35: Measures against out-band interference
2.14.8 Recommended parts
Table 10: Recommended parts for ESD/EOS protection
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AMY-6M - Hardware Integration Manual
Unless there is a galvanic coupling between the local GND (i.e. the
work table) and the PCB GND, then the first point of contact when
handling the PCB shall always be between the local GND and PCB
GND.
Before mounting an antenna patch, connect ground of the device.
GND
Lo c al GND
When handling the RF pin, do not come into contact with any
charged capacitors and be careful when contacting materials that
can develop charges (e.g. patch antenna ~10pF, coax cable ~5080pF/m, soldering iron, …)
ESD
S en s it iv e !
R F_ IN
To prevent electrostatic discharge through the RF input, do not
touch the mounted patch antenna.
When soldering RF connectors and patch antennas to the receiver’s
RF pin, make sure to use an ESD safe soldering iron (tip).
R F_ IN
E SD S a fe
3 Product handling & soldering
3.1 Packaging, shipping, storage and moisture preconditioning
For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage
information, as well as drying for preconditioning see the AMY-6M Data Sheet [1] .
3.2 ESD handling precautions
ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working
station or a large manufacturing area. The main principle of an EPA is that there are no highly charging materials
in the vicinity of ESD sensitive electronics, all conductive materials are grounded, workers are grounded, and
charge build-up on ESD sensitive electronics is prevented. International standards are used to define typical EPA
and can be obtained for example from International Electrotechnical Commission (IEC) or American National
Standards Institute (ANSI).
GPS receivers are sensitive to ESD and require special precautions when handling. Particular care must be
exercised when handling patch antennas, due to the risk of electrostatic charges. In addition to standard ESD
safety practices, the following measures should be taken into account whenever handling the receiver.
Failure to observe these precautions can result in severe damage to the GPS receiver!
3.3 Soldering
3.3.1 Soldering paste
Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering
process has taken place.
Stencil Thickness: 100 to 150 µm for base boards
The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.12.2
UBX-17021971 – R07 Product handling & soldering
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AMY-6M - Hardware Integration Manual
Preheat/ Soak Temperature min.
Preheat/ Soak Temperature max.
Preheat/ Soak Time from T
smin
to T
smax
T
smin
T
smax
Ts (T
smin
to T
smax
)
150°C
180°C
< 90 seconds
Liquidus Temperature
Time maintained above TL
TL
tL
217°C
40 to 60 seconds
Peak Package Body Temperature
TP
250°C
Ramp up rate (TL to TP)
3°C/ second max.
Time within +0°C…-5°C of TP
30 seconds
Ramp down rate (TP to TL)
4°C/ second max.
3.3.2 Reflow soldering
Table 11: Recommended conditions for reflow process
The peak temperature must not exceed 250°C. The time above 245°C must not exceed 30 seconds.
AMY-6M must not be soldered with a damp heat process.
3.3.3 Optical inspection
After soldering the AMY-6M module, consider an optical inspection step to check whether:
The module is properly aligned and centered over the pads
3.3.4 Repeated reflow soldering
Only single reflow soldering processes are recommended for boards populated with AMY-6M modules.
3.3.5 Wave soldering
Base boards with combined through-hole technology (THT) components and surface-mount technology (SMT)
devices require wave soldering to solder the THT components. Only a single wave soldering process is
encouraged for boards populated with AMY-6M.
3.3.6 Rework
Not recommended.
3.3.7 Conformal coating
Certain applications employ a conformal coating of the PCB using HumiSeal® or other related coating products.
Conformal Coating of the module will void the warranty.
3.3.8 Casting
If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such
processes in combination with the u-blox 6 module before implementing this in the production.
Casting will void the warranty.
3.3.9 Use of ultrasonic processes
Some components on the u-blox 6 module are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes
(cleaning, welding etc.) may cause damage to the GPS Receiver.
u-blox offers no warranty against damages to the u-blox 6 module caused by any Ultrasonic Processes.
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AMY-6M - Hardware Integration Manual
3.4 Safety precautions
AMY-6M modules must be supplied by an external limited power source in compliance with the clause 2.5 of
the standard IEC 60950-1. In addition to an external limited power source, only separated or Safety Extra-Low
Voltage (SELV) circuits are to be connected to the module, including interfaces and antennas.
For more information about SELV circuits, see section 2.2 in Safety standard IEC 60950-1 [6].
UBX-17021971 – R07 Product handling & soldering
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AMY-6M - Hardware Integration Manual
The best way to test the sensitivity of a GPS device is
with the use of a 1-channel GPS simulator. It assures
reliable and constant signals at every measurement.
u-blox recommends the following Single-Channel GPS
Simulator:
Because of the testing done by u-blox, it is obvious that an OEM manufacturer doesn’t need to repeat firmware
tests or measurements of the GPS parameters/characteristics (e.g. TTFF) in their production test.
An OEM manufacturer should focus on:
Overall sensitivity of the device (including antenna, if applicable)
Communication to a host controller
4.2 System sensitivity test
4.2.1 Guidelines for sensitivity tests
1. Connect a 1-channel GPS simulator to the OEM product
2. Choose the power level in a way that the “Golden Device” would report a C/No ratio of 38-40 dBHz
3. Power up the DUT (Device Under Test) and allow enough time for the acquisition
4. Read the C/No value from the NMEA GSV or the UBX-NAV-SVINFO message (e.g. with u-center)
5. Compare the results to a “Golden Device” or a u-blox 6 Evaluation Kit.
4.2.2 ‘Go/No go’ tests for integrated devices
The best test is to bring the device to an outdoor position with excellent sky view (HDOP < 3.0). Let the
receiver acquire satellites and compare the signal strength with a “Golden Device”.
As the electro-magnetic field of a redistribution antenna is not homogenous, indoor tests are in most cases
not reliable. These kind of tests may be useful as a ‘go/no go’ test but not for sensitivity measurements.
UBX-17021971 – R07 Product testing
Page 44 of 57
Appendix
Pin
AMY-5M
AMY-6M
Remarks for Migration
Pin Name
Typical Assignment
Pin Name
Typical Assignment
A1
RF_IN
RF_IN
no change
A2
GND GND no change
A3
NC NC no change
A4
GND GND no change
A5
XTAL_OUT
Leave open if no
RTC attached.
XTAL_OUT
Leave open in no
RTC attached.
no change
A6
XTAL_IN
GND if no RTC
attached.
XTAL_IN
GND if no RTC
attached.
no change
A7
VDD_LNA
Supply capacitor to
GND.
VDD_LNA
Leave open.
No need to populate capacitor.
A8
VDD_ANA
Supply capacitor to
GND.
VDD_ANA
Leave open.
No need to populate capacitor.
A9
VDD_RF
Supply capacitor to
GND.
VDD_RF
Leave open.
No need to populate capacitor.
B1
GND GND no change
B2
GND GND no change
B3
Reserved
Do not connect
Reserved
Do not connect.
no change
B4
GND GND no change
B5
GND GND no change
B6
GND GND no change
B7
V_TH
V_TH
no change
B8
GND GND no change
B9
VDD_USB
Connect to GND if
not used
VDD_USB
no change
C1
PIO8 /
EXTINT1
Pull-up resistor of
100k to VDD_IO.
PIO8 / EXTINT1
Leave open.
No need to populate resistor. Input voltage levels
have changed. See AMY-6M Data Sheet [1].
C2
Reserved
Do not connect
Reserved
Do not connect.
no change
C7
USB_DM
Leave open if not
used.
USB_DM
Leave open if not
used.
External series resistor should be changed to 22
Ohm instead of 27 Ohm if usb is used.
C8
PIO18
Leave open
PIO18
Do not connect.
no change
C9
PIO21
Always connect to
GND
PIO21/ SPI SCK
Connect to GND if
not used.
no change
D1
PIO7 /
EXTINT0
Pull-up resistor of
100k to VDD_IO.
PIO7/ EXTINT0
Leave open if not
used.
No need to populate resistor. Input voltage levels
have change. See AMY-6M Data Sheet [1].
D2
Reserved
Leave open
Reserved
Leave open.
no change
D7
USB_DP
Leave open if not
used.
USB_DP
Leave open if not
used.
External series resistor should be changed to 22
Ohm instead of 27 Ohm if usb is used.
D8
V_RESET
Connect to
VDD_3V.
V_RESET
Connect to
VDD_3V.
no change
D9
VDD_3V
VDD_3V
no change
E1
Reserved
Leave open.
Reserved
Leave open.
no change
E2
Reserved
Leave open
Reserved
Leave open.
no change
E8
PIO23
Always connect to
GND
PIO23
Always connect to
GND.
no change
E9
VDD_B
NC or supply cap
VDD_B
Leave open.
no change
F1
TIMEPULSE
Leave open if not
used.
TIMEPULSE
Leave open if not
used.
no change
A Migration to u-blox-6 receivers
A.1 Migration from AMY-5M to AMY-6M
AMY-6M - Hardware Integration Manual
UBX-17021971 – R07 Appendix
Page 45 of 57
AMY-6M - Hardware Integration Manual
Pin
AMY-5M
AMY-6M
Remarks for Migration
Pin Name
Typical Assignment
Pin Name
Typical Assignment
F2
GND GND no change
F3
PIO17
Leave open
PIO17
Leave open.
no change
F4
PIO19 /
CFG_COM0
Leave open if not
used
CFG_COM0/
MOSI
Leave open if not
used.
no change
F5
PIO20 /
CFG_COM1
Leave open if not
used
CFG_COM1/
MISO
Leave open if not
used.
no change
F6
PIO6
Leave open
SS_N
Leave open if not
used.
no change
F7
Reserved
Do not connect
Reserved
Leave open
no change
F8
GND GND no change
F9
V_DCDC
V_DCDC
no change
G1
VDD_IO
1.65-3.6V
VDD_IO
1.65-3.6V
no change
G2
TDI /
SAFEBOOT_
N
Leave open if not
used.
SAFEBOOT_N
Leave open if not
used.
no change
G3
PIO3 / SCL2
Leave open if not
used.
SCL2
Leave open if not
used.
no change
G4
PIO2 / SDA2
Leave open if not
used.
SDA2
Leave open if not
used.
no change
G5
PIO5 / TxD1
Leave open if not
used.
TxD1
Leave open if not
used.
no change
G6
PIO4 / RxD1
Pull-up resistor of
100k to VDD_IO.
RxD1
Leave open if not
used.
No need to populate resistor. Input voltage levels
have changed. See AMY-6M Data Sheet [1].
G7
V_BCKP
1.4-3.6V (optional).
Connect to GND if
not used
V_BCKP
1.4-3.6V. Connect
to GND if not used.
no change
G8
VDD_C
Supply capacitor,
required 2.2 F
VDD_C
Leave open.
No need to populate capacitor.
G9
NC
Leave open
DCDC_EN
Leave open if not
used.
no change
UBX-17021971 – R07 Appendix
Page 46 of 57
AMY-6M - Hardware Integration Manual
ID
Parameter
Value
1
Frequency Specifications
1.1
Oscillation mode
Fundamental Mode
1.2
Nominal frequency at 25 ºC
32.768 kHz
1.3
Frequency calibration tolerance at 25 ºC
< ±100 ppm
2
Electrical Specifications
2.1
Load capacitance CL
9 pF
2.2
Equivalent series resistance RS
50 k
Manufacturer
Order No.
Micro Crystal
CC7V-T1A 32.768 kHz 9.0 pF +/- 100 ppm
Manufacturer
Order No.
ST
M24C32-R
Microchip
24AA32A
Catalyst
CAT24C32
Samsung
S524AB0X91
Manufacturer
Order No.
Winbond
W25X10A
Winbond
W25X20A
AMIC
A25L010
AMIC
A25L020
Manufacturer
Order No.
ST Microelectronics
USBLC6-2
Manufacturer
Order No.
Seiko Instruments Inc.
S-1206B33-I6T2G
B Component selection
This section provides information about components that are critical for the performance of the AMY-6M GPS
receiver module.
Temperature range specifications need only be as wide as required by a particular application. For the purpose of
this document, specifications for industrial temperature range (-40 C +85 C) are provided.
B.1 RTC crystal (Y2)
Table 12: RTC Crystal specifications
Table 13: Recommend parts list for RTC Crystal Y2
B.2 I2C Serial EEPROM memory
Table 14: Recommend parts list for I2C Serial EEPROM memory
B.3 Serial FLASH Memory
Table 15: Recommend parts list for serial FLASH memory
B.4 USB line protection (D2)
Table 16: Recommend parts list for USB line protection
B.5 USB LDO (U4)
Table 17: Recommend parts list for USB LDO
UBX-17021971 – R07 Appendix
Page 47 of 57
B.6 Operational amplifier (U31)
Manufacturer
Order No.
Linear Technology
LT6000
Linear Technology
LT6003
Manufacturer
Order No.
Fairchild
NC7WZ07P6X
Manufacturer
Order No.
Vishay
Si1016X-T1-E3
Manufacturer
Order No.
muRata
BLM15HD102SN1
Manufacturer
Order No.
muRata
LQG15HS27NJ02
Name
Use
Type / Value
C1
RF-input DC block
COG 47P 5% 25V
C
Decoupling Capacitor
X5R 100N 10% 10V
C19
Load capacitor XTAL_IN
COG 12P 5% 25V
C20
Load capacitor XTAL_OUT
COG 12P 5% 25V
C23
Decoupling capacitor at VBUS
Depends on USB LDO (U3) specification
C24
Decoupling capacitor at VBUS
Depends on USB LDO (U3) specification
Table 18: Recommend parts list for operational amplifier
B.7 Dual open-drain buffer (U32)
Table 19: Recommend parts list for dual open-drain buffer
B.8 Antenna supervisor switch transistor (T31)
Table 20: Recommend parts list for antenna supervisor switch transistor
B.9 Ferrite bead filter (FB1)
AMY-6M - Hardware Integration Manual
Table 21: Recommend parts list for the ferrite bead filter
B.10 Inductor (L)
Table 22: Recommend parts list for inductor
B.11 Standard capacitors
Table 23: Standard capacitors
UBX-17021971 – R07 Appendix
Page 48 of 57
B.12 Standard resistors
Name
Use
Type / Value
R
Active antenna supply (VDD_3V)
10R 5% 0.1W
R4
USB data serial termination
22R 5% 0.1W
R5
USB data serial termination
22R 5% 0.1W
R8
Pull-up at RXD1
100k 5% 0.1W
R9
Pull-up at EXTINT0
100k 5% 0.1W
R10
Pull-up at EXTINT1
100k 5% 0.1W
R11
Pull-down at VDD_USB
10K 5% 0.1W
R30
Pull-up at antenna supervisor transistor
100K 5% 0.1W
R31
Antenna supervisor input current limiter
39K 5% 0.1W
R34
Antenna supervisor current limiter
10R 5% 0.25W
R38
Antenna supervisor voltage divider
560R 5% 0.1W
R39
Antenna supervisor voltage divider
100K 5% 0.1W
Manufacturer
Order No.
MAXIM
MAX2659ELT+
JRC
NJG1143UA2
Manufacturer
Order No.
Comments
EPCOS
B9415: B39162-B9415-K610
Low insertion loss
EPCOS
B9444: B39162-B9444-M410
Good wireless band suppression
MuRata
SAFEB1G57KB0F00
Very low insertion loss
MuRata
SAFSE1G57KA0T90
MuRata
SAFEA1G57KE0F00
Good wireless band suppression
MuRata
SAFEB1G57KE0F00
Good wireless band suppression
CTS
CER0032A
Ceramic filter also offers robust ESD
Protection
TriQuint
856561
Compliant to the AEC-Q200 standard
Table 24: Standard resistors
B.13 LNA (LNA1)
AMY-6M - Hardware Integration Manual
Table 25: recommended LNAs
B.14 SAW Filter (F2)
Table 26: recommended SAW Filters
UBX-17021971 – R07 Appendix
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AMY-6M - Hardware Integration Manual
DDC D e v i c e ADDC D e v i c e B
V
DD
SDA
SCL
GND
RpRp
SDA in
SDA out
SCL in
SDA out
SDA in
SDA out
SCL in
SDA out
Rp
Rp
C Interface Backgrounder
C.1 DDC Interface
Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus.
These lines are connected to all devices on the DDC. SCL is used to synchronize data transfers and SDA is the
data line. Both SCL and SDA lines are "open drain" drivers. This means that DDC devices can only drive them
low or leave them open. The pull-up resistor (Rp) pulls the line up to VDD if no DDC device is pulling it down to
GND. If the pull-up resistors are missing, the SCL and SDA lines are undefined and the DDC bus will not work.
For most DDC systems the low and high input voltage level thresholds of SDA and SCL depend on VDD. See the
AMY-6M Data Sheet [1] for the applicable voltage levels.
Figure 37: A simple DDC connection
The signal shape and the maximum rate in which data can be transferred over SDA and SCL is limited by the
values of Rp and the wire and I/O capacitance (Cp). Long wires and a large number of devices on the bus
increase Cp, therefore DDC connections should always be as short as possible. The resistance of the pull-up
resistors and the capacitance of the wires should be carefully chosen.
Figure 38: DDC block diagram
C.1.1 Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it’s a microcontroller,
EEPROM or D/A Converter, etc.) and can operate as either a transmitter or receiver, depending on the function
CFG-PRT message for DDC accordingly can change this address.
UBX-17021971 – R07 Appendix
Page 50 of 57
of the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the
AMY-6M - Hardware Integration Manual
Transmit
Receive
Master: sends the clock and addresses slaves
Sends data to slave
Receives data from slave
Slave: receives the clock and address
Sends data to master
Receives data from master
The first byte sent is comprised of the address field and R/W bit. Hence the byte seen on the bus 0x42 is
shifted by 1 to the left plus R/W bit thus being 0x84 or 0x85 if analyzed by scope or protocol analyzer.
In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave. The DDC-bus is a multi-master bus,
i.e. multiple devices are capable of controlling the bus. Such architecture is not permanent and depends on the
direction of data transfer at any given point in time. A master device not only allocates the time slots when
slaves can respond but also enables and synchronizes designated slaves to physically access the bus by driving
the clock. Although multiple nodes can assume the role of a master, only one at any time is permitted to do so.
Thus, when one node acts as master, all other nodes act as slaves. Table 27 shows the possible roles and modes
for devices connected to a DDC bus.
Table 27: Possible roles and modes of devices connected to DDC bus
u-blox 6 GPS receivers normally run in the slave mode. There is an exception when an external EEPROM is
attached. In that case, the receiver attempts to establish presence of such a non-volatile memory component by
writing and reading from a specific location. If EEPROM is present (assumed to be located at a fixed address
0xA0), the receiver assumes the role of a master on the bus and never changes role to slave until the following
start-up (subject to EEPROM presence). This process takes place only once at the start-up, i.e. the receiver’s role
cannot be changed during the normal operation afterward. This model is an exception and should not be
implemented if there are other participants on the bus contending for the bus control (µC / CPU, etc.).
As a slave on the bus, the u-blox 6 GPS receiver cannot initiate the data transfers. The master node has the
exclusive right and responsibility to generate the data clock, therefore the slave nodes need not be configured to
use the same baud rate. For the purpose of simplification, if not specified differently, SLAVE denotes the u-blox 6
GPS receiver while MASTER denotes the external device (CPU, μC) controlling the DDC bus by driving the SCL
line.
u-blox GPS receivers support Standard-Mode I
rate up to 100 kBit/s and a SCL clock frequency up to 100 kHz.
2
C-bus specification with 7-bit addressing and a data transfer
C.1.2 DDC troubleshooting
Consider the following questions when implementing I2C in designs:
Is there a stable supply voltage Vdd? Often, external I
provided with Vdd.
Are appropriate termination resistances attached between SDA, SCL and Vdd? The voltage level on SDA and
SCL must be Vdd as long as the bus is idle and drop near GND if shorted to GND. [Note: Very few I2C
masters exist which drive SCL high and low, i.e. the SCL line is not open-drain. In this case, a termination
resistor is not needed and SCL cannot be pulled low. These masters will not work together with other
masters (as they have no multi-master support) and may not be used with devices which stretch SCL during
transfers.]
Are SDA and SCL mixed up? This may accidentally happen e.g. when connecting I
connectors.
Do all I
Do all I
If more than one I
2
C devices support the I2C supply voltage used on the bus?
2
C devices support the maximum SCL clock rate used on the bus?
2
C master is connected to the bus: do all masters provide multi-master support?
Are the high and low level voltages on SDA and SCL correct during I
the low level threshold with 0.3 Vcc, the high level threshold with 0.7 Vcc. Modifying the termination
resistance Rp, the serial resistors Rs or lowering the SCL clock rate could help here.
UBX-17021971 – R07 Appendix
Page 51 of 57
2
C devices (like I2C masters or monitors) must be
2
C buses with cables or
2
C transfers? The I2C standard defines
AMY-6M - Hardware Integration Manual
SPI S la v e
MIS O
MO SI
SCK
SCS
Are there spikes or noise on SDA, SCL or even Vdd? They may result from interferences from other
components or because the capacitances Cp and/or Cc are too high. The effects can often be reduced by
using shorter interconnections.
For more information about DDC implementation refer to the u-blox 5/6 Receiver Description including
Protocol Specification [2].
C.2 SPI Interface
C.2.1 SPI basics
Devices communicate in master/slave mode where the master device provides the clock signal (SCK) and
determines the state of the chip select (SCS/SS_N) lines, i.e. it activates the slave it wants to communicate with.
The slave device receives the clock and chip select from the master. Multiple slave devices are allowed with
individual slave select (chip select) lines. This means that there is one master, while the number of slaves is only
limited by the number of chip selects. In addition to reliability and relatively high speed (with respect to the
conventional UART), the SPI interface is easy to use and requires no special handling or complex communication
stack implementation in the software.
The standard configuration for a slave device (see Figure 39) uses two control and two data lines. These are
identified as follows:
SCS — Slave Chip Select (control: output from master, usually active low)
SCK — Serial Clock (control: output from master)
MOSI — Master Output, Slave Input (data: output from master)
MISO — Master Input, Slave Output (data: output from slave)
Alternative naming conventions are also widely used. Confirm the pin/signal naming with specific
components used.
Figure 39: SPI slave
SPI always follows the basic principle of a shift register. During an SPI transfer, command codes and data values
are simultaneously transmitted (shifted out serially) and received (shifted in serially). The data is entered into a
shift register and then internally available for parallel processing. The length of the shift registers is not fixed, but
can vary from device to device. Normally the shift registers are 8Bit or integral multiples thereof. However, they
can also have an odd number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data.
When an SPI transfer occurs, an 8-bit character is shifted out one data pin while a different 8-bit character is
simultaneously shifted in a second data pin. Another way to view this transfer is that an 8-bit shift register in the
master and another 8-bit shift register in the slave are connected as a circular 16-bit shift register. When a
transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and
slave are effectively exchanged.
The serial clock (SCK) line synchronizes shifting and sampling of the information on the two serial data lines
(MOSI and MISO). The chip select (SCS/SS_N) line allows individual selection of a slave SPI device. If an SPI slave
device is not selected (i.e. its chip select is not activated), its data output enters a high-impedance state (hi-Z) and
does not interfere with SPI bus activities.
UBX-17021971 – R07 Appendix
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AMY-6M - Hardware Integration Manual
SPI M a st er
SPI S la ve
0
Chip S elect
MO SI
SCK
Dat a Input
MIS O
SPI S la ve
1
SPI S la ve
2
SCS
0
SCS
1
SCS
2
Clock
Dat a Out put
MO SI
MO SI
MO SI
SS_N
SS_N
SS_N
SCK
SCK
SCK
MIS O
MIS O
MIS O
The data output MISO functions as the data return signal from the slave to the master.
Figure 40 shows a typical block diagram for an SPI master with several slaves. Here, the SCK and MOSI data lines
are shared by all of the slaves. Also the MISO data lines are linked together and led back to the master. Only the
chip selects are separately brought to each SPI device.
Figure 40: Master with independent slaves
SPI allows multiple microcontrollers to be linked together. These can be configured according to single or
multiple master protocols. In the first variant the microcontroller(s) designated as slave(s) behave like a normal
peripheral device. The second variant allows for several masters and allows each microprocessor the possibility to
take the role of master and to address another microprocessor. In this case one microcontroller must
permanently provide the clock signal.
There are two SPI system errors. The first occurs if several SPI devices want to become master at the same time.
The other is a collision error that occurs for example when SPI devices work with different polarities.
Systems involving multiple microcontrollers are beyond the scope of this document. Cascading slave peripherals is not supported.
Four I/O pin signals are associated with SPI transfers: the SCK, the MISO data line, the MOSI data line, and the
active low SCS/SS_N pin. In the unselected state the MISO lines are hi-Z and therefore inactive. The master
decides with which peripheral device it wants to communicate. The clock line SCK provides synchronization for
data communication and is brought to the device whether or not it is selected.
The majority of SPI devices provide all four of these lines. Sometimes MOSI and MISO are multiplexed, or else
one is missing. A peripheral device, which must not or cannot be configured, requires no input line but only a
data output. As soon as it gets selected it starts sending data. In some ADCs therefore the MOSI line is missing.
Some devices have no data output (e.g. LCD controllers which can be configured, but cannot send data or status
messages).
The following rules should answer the most common questions concerning these signals:
SCK: The SCK pin is an output when the SPI is configured as a master and an input when the SPI is
configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal bus
clock. When the master initiates a transfer, eight clock cycles are automatically generated on the SCK pin.
UBX-17021971 – R07 Appendix
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AMY-6M - Hardware Integration Manual
When the SPI is configured as a slave, the SCK pin is an input, and the clock signal from the master
synchronizes the data transfer between the master and slave devices. Slave devices ignore the SCK signal
unless the slave select pin is active low. In both the master and slave SPI devices, data is shifted on one edge
of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by
the SPI transfer protocol.
MISO/MOSI: The MISO and MOSI data pins are used for transmitting and receiving serial data. When the
SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line.
When the SPI is configured as a slave, these pins reverse roles.
SCS/SS_N: In master mode, the SCS output(s) select external slaves (e.g. SCS1_N, SCS2_N). In slave mode,
SS_N is the slave select input. The chip select pin behaves differently on master and slave devices. On a slave
device, this pin is used to enable the SPI slave for a transfer. If the SS_N pin of a slave is inactive (high), the
device ignores SCK clocks and keeps the MISO output pin in the high-impedance state. On a master device,
the SCS pin can serve as a general-purpose output not affecting the SPI.
UBX-17021971 – R07 Appendix
Page 54 of 57
D Glossary
API
Application Programming Interface
BBR
Battery backup RAM
ECEF
Earth Centered Earth Fixed
ESD
Electro Static Discharge
HAE
Height Above WGS84-Ellipsoid
LNA
Low Noise Amplifier
LOS
Line of sight,
NMEA 0183
ASCII based standard data communication protocol used by GPS receivers.
PUBX
u-blox proprietary extension to the NMEA protocol
PVT
Position Velocity Time
SA
Selective Availability
SV
Satellite Vehicle
SBAS
Satellite Based Augmentation Systems
UBX
File extension for u-center log file or short form for the UBX protocol
UBX Protocol
A proprietary binary protocol used by the ANTARIS™ GPS technology
AMY-6M - Hardware Integration Manual
UBX-17021971 – R07 Appendix
Page 55 of 57
AMY-6M - Hardware Integration Manual
Revision
Date
Name
Status / Comments
-
21/10/2010
mdur
Objective
1
03/02/2011
mdur
Preliminary
2
11/04/2011
mdur
Preliminary/ Soldering Profile changed
A
06/09/2011
mdur
Preliminary/ ROM7.03 added
A1
19/09/2012
mdur
AMY-6M-0-002 added
A2
14/11/2012
smos
Status changed
Last revision with document number GPS.G6-HW-10037
R07
06/06/2017
rmak
Added Section 3.4 Safety precautions and Reference [6]
Related documents
[1] AMY-6M Data Sheet, Doc No GPS.G6-HW-10039
[2] u-blox 6 Receiver Description including Protocol Specification, Doc No GPS-SW-09018
[3] GPS Antenna Application Note, Doc No GPS-X-08014
[4] GPS Compendium, Doc No GPS-X-02007
[5] u-blox 6 firmware version 7 Release Notes, Doc No GPS.G6-SW-11013
[6] Information technology equipment – Safety Standard IEC 60950-1
https://webstore.iec.ch/publication/4024
Additional information is available in the FAQ section of our website (http://www.u-blox.com/en/faq.html). For regular updates to u-blox documentation and to receive product change notifications please register on
our homepage.
Revision history
UBX-17021971 – R07 Related documents
Page 56 of 57
Contact
Offices
North, Central and South
America
u-blox America, Inc.
Phone: +1 703 483 3180
E-mail: info_us@u-blox.com
Regional Office West Coast:
Phone: +1 408 573 3640