u blox 2AGQN1NNN User Manual

Abstract

This document describes the features and the system integration of SARA-R4 series cellular modules.

These modules are a complete, cost efficient and performance optimized LTE Cat M1 solution in the compact SARA form factor.

www.u-blox.com

UBX-16029218 - R01

SARA-R4 series

LTE Cat M1 modules

System Integration Manual

Document Information

Title

SARA-R4 series

Subtitle

LTE Cat M1 modules

Document type

System Integration Manual

Document number

UBX-16029218

Revision and date

R01

31-Jan-2017

Document status

Objective Specification

Document status explanation

Objective Specification

Document contains target values. Revised and supplementary data will be published later.

Advance Information

Document contains data based on early testing. Revised and supplementary data will be published later.

Early Production Information

Document contains data from product verification. Revised and supplementary data may be published later.

Production Information

Document contains the final product specification.

Name

Type number

Firmware version

PCN / IN

SARA-R404M

SARA-R404M-00B-00

K0.0.00.00.05.01

UBX-17003782

This document applies to the following products:

SARA-R4 series - System Integration Manual

u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited. The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com.

u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners.

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Preface

u-blox Technical Documentation

As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.

 AT Commands Manual: This document provides the description of the AT commands supported by the

u-blox cellular modules.

 System Integration Manual: This document provides the description of u-blox cellular modules’ system

from the hardware and the software point of view, it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules.

 Application Note: These documents provide guidelines and information on specific hardware and/or

software topics on u-blox cellular modules. See Related documents for a list of Application Notes related to your Cellular Module.

How to use this Manual

The SARA-R4 series System Integration Manual provides the necessary information to successfully design and configure the u-blox cellular modules.

This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance.

A warning symbol indicates actions that could negatively impact or damage the module.

Questions

If you have any questions about u-blox Cellular Integration:

 Read this manual carefully.  Contact our information service on the homepage http://www.u-blox.com/

Technical Support

Worldwide Web

Our website (http://www.u-blox.com/) is a rich pool of information. Product information, technical documents can be accessed 24h a day.

By E-mail

Contact the closest Technical Support office by email. Use our service pool email addresses rather than any personal email address of our staff. This makes sure that your request is processed as soon as possible. You will find the contact details at the end of the document.

Helpful Information when Contacting Technical Support

When contacting Technical Support, have the following information ready:

 Module type (SARA-R404M) and firmware version  Module configuration  Clear description of your question or the problem  A short description of the application  Your complete contact details

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Contents

Preface ................................................................................................................................ 3

Contents .............................................................................................................................. 4

1 System description ....................................................................................................... 7

1.1 Overview .............................................................................................................................................. 7

1.2 Architecture .......................................................................................................................................... 8

1.3 Pin-out ................................................................................................................................................. 9

1.4 Operating modes ................................................................................................................................ 12

1.5 Supply interfaces ................................................................................................................................ 14

1.5.1 Module supply input (VCC) ......................................................................................................... 14

1.5.2 Generic digital interfaces supply output (V_INT) ........................................................................... 16

1.6 System function interfaces .................................................................................................................. 17

1.6.1 Module power-on ....................................................................................................................... 17

1.6.2 Module power-off ....................................................................................................................... 18

1.6.3 Module reset ............................................................................................................................... 20

1.7 Antenna interface ............................................................................................................................... 21

1.7.1 Antenna RF interface (ANT) ......................................................................................................... 21

1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 22

1.8 SIM interface ...................................................................................................................................... 22

1.8.1 SIM interface ............................................................................................................................... 22

1.8.2 SIM detection interface (SIM_DET) ............................................................................................... 22

1.9 Data communication interfaces .......................................................................................................... 23

1.9.1 UART interface ............................................................................................................................ 23

1.9.2 USB interface............................................................................................................................... 26

1.9.3 DDC (I2C) interface ...................................................................................................................... 27

1.10 General Purpose Input/Output ........................................................................................................ 28

1.11 Reserved pins (RSVD) ...................................................................................................................... 28

1.12 System features............................................................................................................................... 28

1.12.1 Network indication ...................................................................................................................... 28

1.12.2 Antenna supervisor ..................................................................................................................... 28

1.12.3 Dual stack IPv4/IPv6 ..................................................................................................................... 28

1.12.4 TCP/IP and UDP/IP ....................................................................................................................... 29

1.12.5 FTP .............................................................................................................................................. 29

1.12.6 HTTP ........................................................................................................................................... 29

1.12.7 SSL .............................................................................................................................................. 29

1.12.8 Firmware update Over AT (FOAT) ................................................................................................ 29

1.12.9 Power saving ............................................................................................................................... 30

2 Design-in ..................................................................................................................... 31

2.1 Overview ............................................................................................................................................ 31

2.2 Supply interfaces ................................................................................................................................ 32

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2.2.1 Module supply (VCC) .................................................................................................................. 32

2.2.2 Generic digital interfaces supply output (V_INT) ........................................................................... 42

2.3 System functions interfaces ................................................................................................................ 43

2.3.1 Module power-on (PWR_ON) ...................................................................................................... 43

2.3.2 Module reset (RESET_N) .............................................................................................................. 44

2.4 Antenna interface ............................................................................................................................... 45

2.4.1 Antenna RF interface (ANT) ......................................................................................................... 45

2.4.2 Antenna detection interface (ANT_DET) ...................................................................................... 52

2.5 SIM interface ...................................................................................................................................... 54

2.5.1 Guidelines for SIM circuit design.................................................................................................. 54

2.5.2 Guidelines for SIM layout design ................................................................................................. 56

2.6 Data communication interfaces .......................................................................................................... 58

2.6.1 UART interface ............................................................................................................................ 58

2.6.2 USB interface............................................................................................................................... 63

2.6.3 DDC (I2C) interface ...................................................................................................................... 65

2.7 General Purpose Input/Output ............................................................................................................ 65

2.8 Reserved pins (RSVD) .......................................................................................................................... 66

2.9 Module placement.............................................................................................................................. 66

2.10 Module footprint and paste mask ................................................................................................... 67

2.11 Thermal guidelines .......................................................................................................................... 68

2.12 Schematic for SARA-R4 series module integration ........................................................................... 69

2.12.1 Schematic for SARA-R4 series modules ........................................................................................ 69

2.13 Design-in checklist .......................................................................................................................... 70

2.13.1 Schematic checklist ..................................................................................................................... 70

2.13.2 Layout checklist ........................................................................................................................... 71

2.13.3 Antenna checklist ........................................................................................................................ 71

3 Handling and soldering ............................................................................................. 72

3.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 72

3.2 Handling ............................................................................................................................................. 72

3.3 Soldering ............................................................................................................................................ 73

3.3.1 Soldering paste............................................................................................................................ 73

3.3.2 Reflow soldering ......................................................................................................................... 73

3.3.3 Optical inspection ........................................................................................................................ 74

3.3.4 Cleaning ...................................................................................................................................... 74

3.3.5 Repeated reflow soldering ........................................................................................................... 75

3.3.6 Wave soldering............................................................................................................................ 75

3.3.7 Hand soldering ............................................................................................................................ 75

3.3.8 Rework ........................................................................................................................................ 75

3.3.9 Conformal coating ...................................................................................................................... 75

3.3.10 Casting ........................................................................................................................................ 75

3.3.11 Grounding metal covers .............................................................................................................. 75

3.3.12 Use of ultrasonic processes .......................................................................................................... 75

4 Approvals .................................................................................................................... 76

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4.1 Product certification approval overview ............................................................................................... 76

4.2 US Federal Communications Commission notice ................................................................................. 77

4.2.1 Safety warnings review the structure ........................................................................................... 77

4.2.2 Declaration of Conformity ........................................................................................................... 77

4.2.3 Modifications .............................................................................................................................. 78

5 Product testing ........................................................................................................... 79

5.1 u-blox in-series production test ........................................................................................................... 79

5.2 Test parameters for OEM manufacturer .............................................................................................. 80

5.2.1 “Go/No go” tests for integrated devices ...................................................................................... 80

5.2.2 RF functional tests ....................................................................................................................... 80

Appendix .......................................................................................................................... 82

A Migration between SARA-R4 and SARA-G3 ............................................................. 82

A.1 Overview ............................................................................................................................................ 82

A.2 Pin-out comparison between SARA-R4 and SARA-G3 ......................................................................... 84

A.3 Schematic for SARA-R4 and SARA-G3 integration .............................................................................. 86

B Glossary ...................................................................................................................... 87

Related documents........................................................................................................... 89

Revision history ................................................................................................................ 90

Contact .............................................................................................................................. 91

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Module

LTE

Interfaces

Audio

Features

Grade

SARA-R404M

●

● ● ● ● ●

● F ●

F = supported by future product versions

1 System description

1.1 Overview

The SARA-R4 series comprises LTE Cat M1 modules supporting single band data transmission in the small SARA LGA form-factor (26.0 x 16.0 mm), that allows an easy integration in compact designs and a seamless drop-in migration from u-blox cellular module families.

SARA-R4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module families and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates migration from the u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules, maximizes customers investments, simplifies logistics, and enables very short time-to-market.

The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices that require long battery lifetimes, such as connected health, smart metering, smart cities and wearables.

SARA-R4 series includes the following modules:

 SARA-R404M, designed primarily to operate in North America on the Verizon network.

LTE Cat M1 supports vehicular handover capability and delivers the technology necessary to enable the use of the modules in applications such as vehicle, asset and people tracking where mobility is a pre-requisite. Other applications where the module is well suited include and are not limited to: smart home, security systems, industrial monitoring and control.

SARA-R4 series modules support data communication with a throughput of 375 kb/s.

Table 1 summarizes the main features and interfaces of SARA-R4 series modules.

Table 1: SARA-R4 series main features summary

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Item

SARA-R404M

Protocol stack release

3GPP Release 13 Frequency Division Duplex (FDD) Half-Duplex

Operating band

Band 13 (Upper 700 MHz)

Power class

Power Class 3 (23 dBm)

Data rate

375 kb/s DL/UL

Memory

V_INT (I/O)

transceiver

Cellular

BaseBand

Processor

ANT

VCC (Supply)

USB

DDC (I2C)

SIM card detection

SIM

UART

Power-On

Reset

GPIO

Antenna detection

Switch

19.2 MHz

Power

Management

Filter

sfal1

Table 2 reports a summary of cellular radio access technologies characteristics and features of the modules.

Table 2: SARA-R4 series characteristics summary

1.2 Architecture

Figure 1 summarizes the internal architecture of SARA-R4 series modules.

Figure 1: SARA-R4 series modules simplified block diagram

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Function

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

51, 52, 53

Module supply input

VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes.

See section 1.5.1 for functional description / requirements. See section 2.2.1 for external circuit design-in.

GND

1, 3, 5, 14, 20-22, 30, 32, 43, 50, 54, 55, 57-61, 63-96

N/A

Ground

GND pins are internally connected each other. External ground connection affects the RF and thermal performance of the device. See section 1.5.1 for functional description. See section 2.2.1 for external circuit design-in.

V_INT

4 O Generic digital interfaces supply output

V_INT = 1.8 V (typical) generated by internal DC/DC regulator when the module is switched on. Test-Point for diagnostic access is recommended. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.

System

PWR_ON

15 I Power-on input

Internal 200 k pull-up resistor. See section 1.6.1 for functional description. See section 2.3.1 for external circuit design-in.

RESET_N

18 I External reset input

Internal pull-up resistor to V_INT. Test-Point for diagnostic access is recommended. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in.

Antenna

ANT

I/O

Primary antenna

Main Tx / Rx antenna interface. 50  nominal characteristic impedance. Antenna circuit affects the RF performance and application

device compliance with required certification schemes. See section 1.7 for functional description / requirements. See section 2.4 for external circuit design-in.

ANT_DET

62 I Antenna detection

ADC for antenna presence detection function See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in.

SIM

VSIM

41 O SIM supply output

VSIM = 1.8 V / 3 V output as per the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in.

SIM_IO

I/O

SIM data

Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

SIM_CLK

38 O SIM clock

3.25 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in.

SIM_RST

40 O SIM reset

Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in.

1.3 Pin-out

Table 3 lists the pin-out of the SARA-R4 series modules, with pins grouped by function.

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Function

Pin Name

Pin No

I/O

Description

Remarks

UART

RXD

13 O UART data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for AT commands, data communication, FOAT and diagnostic.

Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

TXD

12 I UART data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT commands, data communication, FOAT and diagnostic.

Internal active pull-up to V_INT. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

CTS

11 O UART clear to send output

1.8 V output, Circuit 106 (CTS) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

RTS

10 I UART ready to send input

1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DSR 6 O

UART data set ready output

1.8 V, Circuit 107 in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

RI 7 O

UART ring indicator output

1.8 V, Circuit 125 in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DTR 9 I

UART data terminal ready input

1.8 V, Circuit 108/2 in ITU-T V.24. Internal active pull-up to V_INT. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DCD 8 O

UART data carrier detect output

1.8 V, Circuit 109 in ITU-T V.24. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

USB

VUSB_DET

17 I USB detect input

VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D-

I/O

USB Data Line D-

USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0) 30  nominal common mode impedance (Z

)

Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D+

I/O

USB Data Line D+

USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0) 30  nominal common mode impedance (Z

) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

DDC

SCL

27 O I2C bus clock line

1.8 V open drain, for communication with I2C-slave devices. External pull-up are not required. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

SDA

I/O

I2C bus data line

1.8 V open drain, for communication with I2C-slave devices. External pull-up are not required. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

GPIO

GPIO1

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.10 for functional description. See section 2.7 for external circuit design-in.

GPIO2

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.10 for functional description. See section 2.7 for external circuit design-in.

GPIO3

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.10 for functional description. See section 2.7 for external circuit design-in.

GPIO4

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.10 for functional description. See section 2.7 for external circuit design-in.

SIM_DET

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.10 for functional description. See section 2.7 for external circuit design-in.

Reserved

RSVD

2, 31, 33-37, 44-49

N/A

Reserved pin

Leave unconnected. See sections 1.11 and 2.8

Table 3: SARA-R4 series module pin definition, grouped by function

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General Status

Operating Mode

Definition Power-down

Not-Powered Mode

VCC supply not present or below operating range: module is switched off.

Power-Off Mode

VCC supply within operating range and module is switched off.

Normal Operation

Idle-Mode

Module processor core runs with 32 kHz reference internally generated.

Active-Mode

Module processor core runs with 19.2 MHz reference generated by the internal oscillator.

Connected-Mode

RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.

Mode

Description

Transition between operating modes

Not-Powered

Module is switched off. Application interfaces are not accessible.

When VCC supply is removed, the modules enter not-powered mode. When in not-powered mode, the module can enter power-off mode applying VCC supply (see 1.6.1).

Power-Off

Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible.

When the modules are switched off by an appropriate switch-off event (see 1.6.2), the modules enter power-off mode from active-mode. When in power-off mode, the modules can be switched on by PWR_ON. When in power-off mode, the modules enter not-powered mode by removing VCC supply.

Idle

Module is switched on with application interfaces temporarily disabled or suspended: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption. The module enters the low power idle-mode whenever possible if power saving is enabled by AT+UPSV command (see u-blox SARA-R404M AT Commands Manual [1]) reducing current consumption (see 1.5.1.3). The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active-mode transitions according to the power saving and HW flow control settings (see

1.9.1.2). Power saving configuration is not enabled by default; it can be enabled by AT+UPSV (see the u-blox SARA-R404M AT Commands Manual [1]).

The modules automatically switch from the active-mode to low power idle-mode whenever possible if power saving is enabled (see sections

1.5.1.30 and u-blox SARA-R404M AT Commands Manual [1], AT+UPSV command). The modules wake up from low power idle-mode to active-mode in the following events:

 Automatic periodic monitoring of the paging channel for the

paging block reception according to network conditions (see

1.5.1.3)

 Automatic periodic enable of the UART interface to receive / send

data, with AT+UPSV=1

 Data received over UART, according to HW flow control (AT&K)

and power saving (AT+UPSV) settings

 RTS input set ON by the host DTE, with HW flow control disabled

and AT+UPSV=2

 DTR input set ON by the host DTE, with AT+UPSV=3  USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2)  The connected USB host forces a remote wakeup of the module as

USB device (see 0)

Active

Module is switched on with application interfaces enabled or not suspended: the module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by AT+UPSV (see 0u-blox SARA-R404M AT Commands Manual [1]).

When the modules are switched on by an appropriate power-on event (see 1.6.1), the modules enter active-mode from not-powered or power-off mode.

If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see idle-mode to active-mode transition description above).

When a RF Tx/Rx data connection is initiated or when RF Tx/Rx activity is required due to a connection previously initiated, the module switches from active to connected-mode.

1.4 Operating modes

SARA-R4 series modules have several operating modes. The operating modes are defined in Table 4 and described in detail in Table 5, providing general guidelines for operation.

Table 4: SARA-R4 series modules operating modes definition

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Mode

Description

Transition between operating modes

Connected

RF Tx/Rx data connection is in progress. The module is prepared to accept data signals

from an external device unless power saving configuration is enabled by AT+UPSV (see 0u- blox SARA-R404M AT Commands Manual [1]).

When a data connection is initiated, the module enters connected-mode from active-mode.

Connected-mode is suspended if Tx/Rx data is not in progress, due to connected discontinuous reception and fast dormancy capabilities of the module and according to the network environment settings and scenario. In such cases the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+UPSV command, the module automatically switches to idle-mode whenever possible. Vice-versa, the module wakes up from idle to active mode and then connected mode if RF Tx/Rx activity is necessary.

When a data connection is terminated, the module returns to the active-mode.

If power saving is enabled and there is no activity for a defined time interval

Any wake up event described in the module operating modes summary table above

Incoming/outgoing data or other dedicated device network communication

No RF Tx/Rx in progress, Communication dropped

Remove VCC

Switch ON:

• PWR_ON

Not

powered

Power off

ActiveConnected Idle

Switch OFF:

• AT+CPWROFF

Apply VCC

Table 5: SARA-R4 series modules operating modes description

Figure 2 describes the transition between the different operating modes.

Figure 2: SARA-R4 series modules operating modes transitions

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Item

Requirement

Remark

VCC nominal voltage

Within VCC normal operating range:

3.20 V min. / 4.40 V max

RF performance is guaranteed when VCC voltage is inside the normal operating range limits. RF performance may be affected when VCC voltage is outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits.

VCC voltage during normal operation

Within VCC extended operating range:

3.00 V min. / 4.30 V max

VCC voltage must be above the extended operating range minimum limit to switch-on the module. The module may switch-off when the VCC voltage drops below the extended operating range minimum limit. Operation above VCC extended operating range is not recommended and may affect device reliability.

VCC average current

Support with adequate margin the highest averaged VCC current consumption value in connected-mode conditions specified in SARA-R4 Data Sheet [1]

The maximum average current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage. Section 1.5.1.2 describes current consumption profiles in LTE connected-mode.

VCC voltage ripple during LTE Tx

Noise in the supply pins has to be minimized

High supply voltage ripple values during LTE RF transmissions in connected-mode directly affect the RF compliance with the applicable certification schemes.

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input. During operation, the current drawn by the SARA-R4 series modules through the VCC pins can vary by several

orders of magnitude, depending on the operating mode and state (as described in sections 1.5.1.2, 1.5.1.3 and

1.5.1.4). It is important that the supply source is able to support the average current consumption occurring during a LTE

transmission at maximum RF power level.

1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to properly design a VCC supply circuit compliant with the requirements listed in Table 6.

The supply circuit affects the RF compliance of the device integrating SARA-R4 series modules

with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the requirements summarized in the Table 6 are fulfilled.

Table 6: Summary of VCC modules supply requirements

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Time

[ms]

Current [mA]

Current consumption value

depends on TX power and

actual antenna load

300

200

100

500

400

600

700

1.5.1.2 VCC current consumption in connected-mode

During an LTE connection, the SARA-R4 module transmits and receives in half duplex mode. The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. Figure 3 shows an example of the module current consumption profile versus time in LTE connected-mode. Detailed current consumption values can be found in SARA-R4 series Data Sheet [1].

Figure 3: VCC current consumption profile versus time during a LTE data connection

1.5.1.3 VCC current consumption in cyclic idle/active mode (power saving enabled)

The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV command (see the u-blox SARA-R404M AT Commands Manual [1]). When power saving is enabled, the module automatically enters the low power idle-mode whenever possible, reducing current consumption.

During low power idle-mode, the module processor runs with internal 32 kHz reference clock frequency. When the power saving configuration is enabled and the module is registered or attached to a network, the

module automatically enters the low power idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the LTE system requirements. When the module monitors the paging channel, it wakes up to the active-mode, to enable the reception of paging block. In between, the module switches to low power idle-mode. This is known as discontinuous reception (DRX).

The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 19.2 MHz used in active-mode.

The time period between two paging block receptions is defined by the network. This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell .

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1.5.1.4 VCC current consumption in fixed active-mode (power saving disabled)

When power saving is disabled, the module does not automatically enter the low power idle-mode whenever possible: the module remains in active-mode. Power saving configuration is by default disabled. It can also be disabled using the AT+UPSV command (see u-blox SARA-R404M AT Commands Manual [1] for detail usage).

The module processor core is activated during idle-mode, and the 19.2 MHz reference clock frequency is used. It would draw more current during the paging period than that in the power saving mode.

1.5.2 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the SARA-R4 series modules is generated by the module internal power management circuitry. The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4 series Data Sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a reference voltage rail for external components.

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VCC

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State

Interna l Rese t → Opera tional Operational

Tristate / Floating

Interna l

Rese t

OFF

Start of interface

configuration

Module interfaces

are configured

Start-up

event

1.6 System function interfaces

1.6.1 Module power-on

When the SARA-R4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied), they can be switched on as follows:

 Rising edge on the VCC input pins to a valid voltage level and then the PWR_ON input pin is held low for a

valid time. After the module power on event, the PWR_ON pin can be released.

When the SARA-R4 series modules are in the power-off mode (i.e. switched off with a valid VCC supply applied), they can be switched on as follows:

 Low pulse on the PWR_ON pin for a valid time period

The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics with voltages and timings are described in SARA-R4 series Data Sheet [1].

Figure 4 shows the module switch-on sequence from the not-powered mode, describing the following phases:

 The external power supply is applied to the VCC module pins  The PWR_ON pin is held low for a valid time  All the generic digital pins of the module are tri-stated until the switch-on of their supply source (V_INT).  The internal reset signal is held low: the baseband core and all the digital pins are held in the reset state.  When the internal reset signal is released, any digital pin is set in a proper sequence from the reset state to

the default operational configured state. The duration of this pins’ configuration phase differs within generic digital interfaces and the USB interface due to host / device enumeration timings (see section 1.9.2).

 The module is fully ready to operate after all interfaces are configured.

Figure 4: SARA-R4 series switch-on sequence description

The Internal Reset signal is not available on a module pin, but the host application can monitor the V_INT

pin to sense the start of the SARA-R4 series module switch-on sequence.

Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage

driven by an external application should be applied to any generic digital interface of the module.

Before the SARA-R4 series module is fully ready to operate, the host application processor should not

send any AT command over the AT communication interfaces (USB, UART) of the module.

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1.6.2 Module power-off

SARA-R4 series can be properly switched off by:

 AT+CPWROFF command (see u-blox SARA-R404M AT Commands Manual [1]). The current parameter

settings are saved in the module’s non-volatile memory and a proper network detach is performed.

 Low pulse on the PWR_ON pin for a valid time period (see SARA-R4 series Data Sheet [1] ).

An abrupt under-voltage shutdown occurs on SARA-R4 series modules when the VCC module supply is

removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the module’s

non-volatile memory or to perform the proper network detach.

It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series modules

normal operations.

An abrupt hardware shutdown occurs on SARA-R4 series modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed.

It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on

the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox SARA-R404M AT Commands Manual [1].

An over-temperature or an under-temperature shutdown occurs on SARA-R4 series modules when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details see section 1.12.9 and u-blox SARA-R404M AT Commands Manual [1], +USTS AT command.

Figure 5 describes the SARA-R4 series modules switch-off sequence started SARA-R4 by means of the AT+CPWROFF command, allowing storage of current parameter settings in the module’s non-volatile memory and a proper network detach, with the following phases:

 When the +CPWROFF AT command is sent, the module starts the switch-off routine.  The module replies OK on the AT interface: the switch-off routine is in progress.  At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators

are turned off, including the generic digital interfaces supply (V_INT).

 Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a

proper low level to the PWR_ON input pin), and enters not-powered mode if the supply is removed from the VCC pins.

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VCC

PWR_ON

RESET_N

V_INT

Internal Reset

Syst em State

BB Pads State

OFF

Tristate / Floating

Operational -> Tristate

Operational

The module starts

the switch-off routine

VCC can be

removed

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

Syst em State

BB Pads State Operational

OFF

Tristate / Floating

Operational → Tristate

AT+CPWROFF

sent to the module

replied by the module

VCC can be

removed

Figure 5: SARA-R4 series switch-off sequence by means of AT+CPWROFF command

The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin

to sense the end of the switch-off sequence.

The duration of each phase in the SARA-R4 series modules’ switch-off routines can largely vary depending

on the application / network settings and the concurrent module activities.

Figure 6 describes the SARA-R4 series modules switch-off sequence started by means of the PWR_ON input pin, allowing storage of current parameter settings in the module’s non-volatile memory and a proper network detach, with the following phases:

 A low pulse with appropriate time duration (see SARA-R4 series Data Sheet [1]) is applied at the PWR_ON

input pin.

 At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators

are turned off, including the generic digital interfaces supply (V_INT).

 Then, the module remains in power-off mode as long as a switch on event does not occur (e.g. applying a

proper low level to the PWR_ON input), and enters not-powered mode if the supply is removed from the VCC pins.

Figure 6: SARA-R4 series switch-off sequence by means of PWR_ON pin

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The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin

to sense the end of the switch-off sequence.

The duration of each phase in the SARA-R4 series modules’ switch-off routines can largely vary depending

on the application / network settings and the concurrent module activities.

1.6.3 Module reset

SARA-R4 series modules can be properly reset (rebooted) by:

 AT+CFUN command (see u-blox SARA-R404M AT Commands Manual [1]).

In the case listed above an “internal” or “software” reset of the module is executed: the current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed.

An abrupt hardware shutdown occurs on SARA-R4 series modules when a low level is applied on RESET_N input pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. Then, the module remains in power-off mode as long as a switch on event does not occur applying a proper low level to the PWR_ON input.

It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on the

RESET_N input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u-blox SARA-R404M AT Commands Manual [1].

The RESET_N input pin is equipped with an internal pull-up to the V_INT supply. For more electrical characteristics details see SARA-R4 series Data Sheet [1].

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Item

Requirements

Remarks

Impedance

50  nominal characteristic impedance

The impedance of the antenna RF connection must match the 50  impedance of the ANT port.

Frequency Range

See the SARA-R4 series Data Sheet [1]

The required frequency range of the antenna connected to ANT port depends on the operating bands of the used cellular module and the used mobile network.

Return Loss

S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable

The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the antenna RF connection matches the 50  characteristic impedance of the ANT port. The impedance of the antenna termination must match as much as possible the 50  nominal impedance of the ANT port over the operating frequency range, reducing as much as possible the amount of reflected power.

Efficiency

> -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable

The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT port needs to be enough high over the operating frequency range to comply with the Over-The-Air (OTA) radiated performance requirements, as Total Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified by applicable related certification schemes.

Maximum Gain

According to radiation exposure limits

The power gain of an antenna is the radiation efficiency multiplied by the directivity: the gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source. The maximum gain of the antenna connected to ANT port must not exceed the herein stated value to comply with regulatory agencies radiation exposure limits.

For additional info see sections 4.2.2 and/or 0.

Input Power

> 24 dBm ( > 0.25 W )

The antenna connected to the ANT port must support with adequate margin the maximum power transmitted by the modules.

1.7 Antenna interface

1.7.1 Antenna RF interface (ANT)

SARA-R4 series modules provide an RF interface for connecting the external antenna. The ANT pin represents the primary RF input/output for transmission and reception of LTE RF signals.

The ANT pin has a nominal characteristic impedance of 50  and must be connected to the primary Tx / Rx antenna through a 50  transmission line to allow proper RF transmission and reception.

1.7.1.1 Antenna RF interfaces requirements

Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to properly design antennas circuits compliant with these requirements.

The antenna circuits affect the RF compliance of the device integrating SARA-R4 series modules

with applicable required certification schemes (for more details see section 4). Compliance is guaranteed if the antenna RF interface requirements summarized in Table 7 are fulfilled.

Table 7: Summary of Tx/Rx antenna RF interface requirements

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1.7.2 Antenna detection interface (ANT_DET)

The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence.

The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the u-blox SARA-R404M AT Commands Manual [1] for more details on this feature.

The ANT_DET pin generates a DC current (for detailed characteristics see the SARA-R4 series Data Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So, the requirements to achieve antenna detection functionality are the following:

 an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used  an antenna detection circuit must be implemented on the application board

See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines.

1.8 SIM interface

1.8.1 SIM interface

SARA-R4 series modules provide high-speed SIM/ME interface including automatic detection and configuration of the voltage required by the connected SIM card or chip.

Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage switch from

1.8 V to 3 V are implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output provides internal short circuit protection to limit start-up current and protect the SIM to short circuits.

The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM card or chip.

1.8.2 SIM detection interface (SIM_DET)

The SIM_DET pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2.5:

 Low logic level at SIM_DET input pin is recognized as SIM card not present  High logic level at SIM_DET input pin is recognized as SIM card present

For more details see the u-blox SARA-R404M AT Commands Manual [1]).

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1.9 Data communication interfaces

SARA-R4 series modules provide the following serial communication interface:

 UART interface: Universal Asynchronous Receiver/Transmitter serial interface available for the communication

with a host application processor (AT commands, data communication, FW update by means of FOAT) and for diagnostic. (see section 1.9.1)

 USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host

application processor (AT commands, data communication, FW update by means of the FOAT feature), for FW update by means of the u-blox EasyFlash tool and for diagnostic. (see section 1.9.2)

 DDC interface: I

chips or modules and with external I2C devices (see section 1.9.3)

1.9.1 UART interface

1.9.1.1 UART features

The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the SARA-R4 series modules, supporting:

 AT command mode  Data mode and Online command mode1  Multiplexer protocol functionality  FW upgrades by means of the FOAT feature (see 1.12.8)  Trace log capture (diagnostic purpose)

UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for detailed electrical characteristics see SARA-R4 series Data Sheet [1]), providing:

 data lines (RXD as output, TXD as input),  hardware flow control lines (CTS as output, RTS as input),  modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output).

SARA-R4 series modules are designed to operate as cellular modems, i.e. as the data circuit-terminating equipment (DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor connected to the module through the UART interface represents the data terminal equipment (DTE).

C bus compatible interface available for the communication with u-blox GNSS positioning

UART signal names of the cellular modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD line

represents data transmitted by the DTE (host processor output) and received by the DCE (module input).

SARA-R4 series modules’ UART interface is by default configured in AT command mode: the module waits for AT command instructions and interprets all the characters received as commands to execute. All the functionalities supported by SARA-R4 series modules can be in general set and configured by AT commands:

 AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]  u-blox AT commands (for the complete list and syntax see the u-blox SARA-R404M AT Commands

Manual [1])

For the definition of the interface data mode, command mode and online command mode see the u-blox SARA-R404M AT Commands

Manual [1]

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D0 D1 D2 D3 D4 D5 D6 D7

Start of 1-Byte transfer

Start Bit (Always 0)

Possible Start of

next transfer

Stop Bit (Always 1)

bit

= 1/(Baudrate)

Normal Transfer, 8N1



Flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see

u-blox SARA-R404M AT Commands Manual [1], &K, \Q AT commands): hardware flow control (over the RTS / CTS lines), software flow control (XON/XOFF), or none flow control.

Hardware flow control is enabled by default. The autobauding is not supported

The following baud rates can be configured by AT command (see u-blox SARA-R404M AT Commands Manual [1]):

 115200 b/s, default value

The following frame formats can be configured by AT command (see u-blox SARA-R404M AT Commands Manual [1]):

 8N1 (8 data bits, No parity, 1 stop bit), default frame configuration with fixed baud rate, see Figure 7

Figure 7: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit)

1.9.1.2 UART signals behavior

At the module switch-on, before the UART interface initialization (as described in the power-on sequence reported in Figure 4), each pin is first tri-stated and then is set to its relative internal reset state4. At the end of the boot sequence, the UART interface is initialized, the module is by default in active-mode, and the UART interface is enabled as AT commands interface.

The configuration and the behavior of the UART signals after the boot sequence are described below. See section 1.4 for definition and description of module operating modes referred to in this section.

RXD signal behavior

The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module holds RXD in the OFF state until the module transmits some data.

For the definition of the interface data mode, command mode and online command mode see the u-blox SARA-R404M AT Commands

Manual [1]

Not supported by “02” product versions See the pin description table in the SARA-R4 series Data Sheet [1]

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TXD signal behavior

The module data input line (TXD) is set by default to the OFF state (high level) at UART initialization. The TXD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TXD input.

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CTS signal behavior

The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is

enabled (data can be received): the module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART.

If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the

module is in low power idle-mode, but only that the UART is not enabled, as the module could be forced to stay in active-mode for other activities, e.g. related to the network or related to other interfaces.

The CTS hardware flow control setting can be changed by AT commands (for more details, see the u-blox SARA-R404M AT Commands Manual [1], AT&K, AT\Q AT commands).

When the power saving configuration is enabled by AT+UPSV command and the hardware flow-control is

not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in low power idle-mode will not be a valid communication character.

RTS signal behavior

The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The module then holds the RTS line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input.

If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any on-going data transmission from the module is interrupted until the RTS line changes to the ON state.

The module behavior according to the RTS hardware flow control status can be configured by AT commands (for more details, see the u-blox SARA-R404M AT Commands Manual [1], AT&K, AT\Q, AT+IFC AT commands).

If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage the power saving configuration (for more details, see u-blox SARA-R404M AT Commands Manual [1], AT+UPSV):

 When an OFF-to-ON transition occurs on the RTS input, the UART is enabled and the module is forced to

active-mode. After ~20 ms, the switch is completed and data can be received without loss. The module cannot enter low power idle-mode and the UART is enabled as long as the RTS is in the ON state

 If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and

the module automatically enters low power idle-mode whenever possible

1.9.2 USB interface

1.9.2.1 USB features

SARA-R4 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate, representing the main interface for transferring high speed data with a host application processor, supporting:

 AT command mode  Data mode and Online command mode6  FW upgrades by means of the FOAT feature (see 1.12.8 and u-blox SARA-R404M AT Commands

Manual [1])

See the u-blox SARA-R404M AT Commands Manual [1] for the definition of the interface data mode, command mode and online

command mode.

For the definition of the interface data mode, command mode and online command mode see the u-blox SARA-R404M AT Commands

Manual [1]

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 FW upgrades by means of the u-blox EasyFlash tool  Trace log capture (diagnostic purpose)

The module itself acts as a USB device and can be connected to a USB host such as a Personal Comput er or an embedded application microprocessor equipped with compatible drivers.

The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus Revision

2.0 specification [4], while the VUSB_DET input pin senses the VBUS USB supply presence (nominally 5 V at the source) to detect the host connection and enable the interface.

The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the SARA-R4 series Data Sheet [1]). Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes.

The USB interface is controlled and operated with:

 AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]  u-blox AT commands (for the complete list and syntax see u-blox SARA-R404M AT Commands Manual [1])

The USB interface of SARA-R4 series modules can provide the following USB functions:

 AT commands and data communication  Diagnostic log

The USB profile of SARA-R4 series modules identifies itself by the following VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [4].

 VID = 0x05C6  PID = 0x90B2

1.9.2.2 USB in Windows

USB drivers are provided for Windows operating system platforms and should be properly installed / enabled by following the step-by-step instructions available in the EVK-R2xx User Guide [2] or in the Windows Embedded OS USB Driver Installation Application Note [3].

USB drivers are available for the following operating system platforms:

 Windows 7  Windows 8  Windows 8.1  Windows 10  Windows Embedded CE 6.0  Windows Embedded Compact 7  Windows Embedded Compact 2013

The module firmware can be upgraded over the USB interface by means of the FOAT fea ture or using the u-blox EasyFlash tool.

1.9.2.3 USB in Linux/Android

It is not required to install a specific driver for each Linux-based or Android-based operating system (OS) to use the module USB interface, which is compatible with standard Linux/Android USB kernel drivers.

1.9.3 DDC (I

The I

C) interface

C interface is not supported by “00” product version.

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Function

Description

Default GPIO

Configurable GPIOs

Network status indication

Network status: registered home network, registered roaming, data transmission, no service

GPIO1-GPIO4 SIM card detection7

External SIM card physical presence detection

GPIO5

General purpose input

Input to sense high or low digital level

GPIO1-GPIO5

General purpose output

Output to set the high or the low digital level

GPIO1-GPIO5

Pin disabled

Tri-state with an internal active pull-down enabled

GPIO1-GPIO5

1.10 General Purpose Input/Output

SARA-R4 series modules include six pins (GPIO1-GPIO5, SIM_DET) which can be configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more details see the u-blox SARA- R404M AT Commands Manual [1], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized in Table 8.

Table 8: SARA-R4 series GPIO custom functions configuration

1.11 Reserved pins (RSVD)

SARA-R4 series modules have pins reserved for future use, marked as RSVD: they can all be left unconnected on the application board.

1.12 System features

1.12.1 Network indication

GPIOs can be configured by the AT command to indicate network status (for further details see section 1.10 and the u-blox SARA-R404M AT Commands Manual [1]):

 No service (no network coverage or not registered)  Registered to the home network  Registered to the visitor network (roaming)  Data call enabled (RF data transmission / reception)

1.12.2 Antenna supervisor

The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional feature that can be implemented if the application requires it. The antenna supervisor is forced by the +UANTR AT command (see the u-blox SARA-R404M AT Commands Manual [1] for more details).

The requirements to achieve antenna detection functionality are the following:

 an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used  an antenna detection circuit must be implemented on the application board

See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines.

1.12.3 Dual stack IPv4/IPv6

SARA-R4 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel. For more details about dual stack IPv4/IPv6 see the u-blox SARA-R404M AT Commands Manual [1].

Not supported by “00” product version

UBX-16029218 - R01 Objective Specification System description

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