u blox 1DIQN3NN System Integrator Manual

Abstract

This document describes the features and the system integration of LARA-R2 series multi-mode cellular modules. These modules are a complete, cost efficient and performance optimized LTE Cat 1 / 3G / 2G multi-mode solution covering up to 4 LTE bands, up to 2 UMTS/HSPA bands and up to 2 GSM/EGPRS bands in the very small and compact LARA form factor.

www.u-blox.com

UBX-16010573 - R08

LARA-R2 series

Size-optimized LTE Cat 1 modules in single and multi-mode configurations

System Integration Manual

Document Information

Title

LARA-R2 series

Subtitle

Size-optimized LTE Cat 1 modules in single and multi-mode configurations

Document type

System Integration Manual

Document number

UBX-16010573

Revision, date

R08

02-Aug-2017

Disclosure restriction

Name

Type number

Modem version

Application version

PCN reference

Product status

LARA-R202

LARA-R202-02B-00

30.36

A01.01

UBX-17024230

Prototypes

LARA-R203

LARA-R203-02B-00

30.39

A01.00

UBX-17048311

Initial Production

LARA-R204

LARA-R204-02B-00

31.34

A01.00

UBX-17012269

Initial Production

LARA-R211

LARA-R211-02B-00

30.31

A01.00

UBX-17012270

Initial Production

LARA-R220

LARA-R220-62B-00

30.38

A01.00

UBX-17047628

Prototypes

LARA-R280

LARA-R280-02B-00

30.39

A01.00

UBX-17048310

Prototypes

This document applies to the following products:

LARA-R2 series - System Integration Manual

u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited.

The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com.

u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners.

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Preface

u-blox Technical Documentation

As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.

 AT Commands Manual: This document provides the description of the AT commands supported by the

u-blox cellular modules.

 System Integration Manual: This document provides the description of u-blox cellular modules’ system

from the hardware and the software point of view, it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules.

 Application Notes: These documents provide guidelines and information on specific hardware and/or

software topics on u-blox cellular modules. See Related documents for a list of application notes related to your cellular module.

How to use this Manual

The LARA-R2 series System Integration Manual provides the necessary information to successfully design in and configure these u-blox cellular modules.

This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance.

A warning symbol indicates actions that could negatively impact or damage the module.

Questions

If you have any questions about u-blox cellular Integration:

 Read this manual carefully.  Contact our information service on the homepage http://www.u-blox.com

Technical Support

Worldwide Web

Our website (http://www.u-blox.com) is a rich pool of information. Product information and technical documents can be accessed 24h a day.

By E-mail

If you have technical problems or cannot find the required information in the provided documents, contact the closest Technical Support office. To ensure that we process your request as soon as possible, use our service pool email addresses rather than personal staff email addresses. Contact details are at the end of the document.

Helpful Information when Contacting Technical Support

When contacting Technical Support, have the following information ready:

 Module type (e.g. LARA-R204) and firmware version  Module configuration  Clear description of your question or the problem  A short description of the application  Your complete contact details

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Preface ................................................................................................................................ 3

Contents .............................................................................................................................. 4

1 System description ....................................................................................................... 7

1.1 Overview .............................................................................................................................................. 7

1.2 Architecture ........................................................................................................................................ 10

1.3 Pin-out ............................................................................................................................................... 12

1.4 Operating modes ................................................................................................................................ 17

1.5 Supply interfaces ................................................................................................................................ 19

1.5.1 Module supply input (VCC) ......................................................................................................... 19

1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 27

1.5.3 Generic digital interfaces supply output (V_INT) ........................................................................... 28

1.6 System function interfaces .................................................................................................................. 29

1.6.1 Module power-on ....................................................................................................................... 29

1.6.2 Module power-off ....................................................................................................................... 31

1.6.3 Module reset ............................................................................................................................... 34

1.6.4 Module / host configuration selection ......................................................................................... 34

1.7 Antenna interface ............................................................................................................................... 35

1.7.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 35

1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 37

1.8 SIM interface ...................................................................................................................................... 37

1.8.1 SIM card interface ....................................................................................................................... 37

1.8.2 SIM card detection interface (SIM_DET) ....................................................................................... 37

1.9 Data communication interfaces .......................................................................................................... 38

1.9.1 UART interface ............................................................................................................................ 38

1.9.2 USB interface............................................................................................................................... 49

1.9.3 HSIC interface ............................................................................................................................. 52

1.9.4 DDC (I2C) interface ...................................................................................................................... 53

1.9.5 SDIO interface ............................................................................................................................. 54

1.10 Audio interface ............................................................................................................................... 55

1.10.1 Digital audio interface ................................................................................................................. 55

1.11 Clock output ................................................................................................................................... 56

1.12 General Purpose Input/Output (GPIO) ............................................................................................. 56

1.13 Reserved pins (RSVD) ...................................................................................................................... 56

1.14 System features............................................................................................................................... 57

1.14.1 Network indication ...................................................................................................................... 57

1.14.2 Antenna detection ...................................................................................................................... 57

1.14.3 Jamming detection ...................................................................................................................... 57

1.14.4 Dual stack IPv4/IPv6 ..................................................................................................................... 58

1.14.5 TCP/IP and UDP/IP ....................................................................................................................... 58

1.14.6 FTP .............................................................................................................................................. 58

1.14.7 HTTP ........................................................................................................................................... 58

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1.14.8 SSL/TLS ........................................................................................................................................ 59

1.14.9 Bearer Independent Protocol ....................................................................................................... 60

1.14.10 AssistNow clients and GNSS integration ................................................................................... 60

1.14.11 Hybrid positioning and CellLocate® .......................................................................................... 61

1.14.12 Wi-Fi integration ...................................................................................................................... 63

1.14.13 Firmware upgrade Over AT (FOAT) .......................................................................................... 63

1.14.14 Firmware update Over The Air (FOTA) ...................................................................................... 64

1.14.15 Smart temperature management ............................................................................................. 64

1.14.16 Power Saving ........................................................................................................................... 66

2 Design-in ..................................................................................................................... 67

2.1 Overview ............................................................................................................................................ 67

2.2 Supply interfaces ................................................................................................................................ 68

2.2.1 Module supply (VCC) .................................................................................................................. 68

2.2.2 RTC supply (V_BCKP) ................................................................................................................... 82

2.2.3 Interface supply (V_INT) ............................................................................................................... 84

2.3 System functions interfaces ................................................................................................................ 85

2.3.1 Module power-on (PWR_ON) ...................................................................................................... 85

2.3.2 Module reset (RESET_N) .............................................................................................................. 86

2.3.3 Module / host configuration selection ......................................................................................... 87

2.4 Antenna interface ............................................................................................................................... 88

2.4.1 Antenna RF interface (ANT1 / ANT2) ........................................................................................... 88

2.4.2 Antenna detection interface (ANT_DET) ...................................................................................... 95

2.5 SIM interface ...................................................................................................................................... 97

2.6 Data communication interfaces ........................................................................................................ 103

2.6.1 UART interface .......................................................................................................................... 103

2.6.2 USB interface............................................................................................................................. 108

2.6.3 HSIC interface ........................................................................................................................... 110

2.6.4 DDC (I2C) interface .................................................................................................................... 112

2.6.5 SDIO interface ........................................................................................................................... 116

2.7 Audio interface ................................................................................................................................. 117

2.7.1 Digital audio interface ............................................................................................................... 117

2.8 General Purpose Input/Output (GPIO) ............................................................................................... 121

2.9 Reserved pins (RSVD) ........................................................................................................................ 122

2.10 Module placement ........................................................................................................................ 122

2.11 Module footprint and paste mask ................................................................................................. 123

2.12 Thermal guidelines ........................................................................................................................ 124

2.13 ESD guidelines .............................................................................................................................. 125

2.13.1 ESD immunity test overview ...................................................................................................... 125

2.13.2 ESD immunity test of u-blox LARA-R2 series reference designs .................................................. 125

2.13.3 ESD application circuits .............................................................................................................. 126

2.14 Schematic for LARA-R2 series module integration ......................................................................... 128

2.15 Design-in checklist ........................................................................................................................ 129

2.15.1 Schematic checklist ................................................................................................................... 129

2.15.2 Layout checklist ......................................................................................................................... 130

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2.15.3 Antenna checklist ...................................................................................................................... 130

3 Handling and soldering ........................................................................................... 131

3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 131

3.2 Handling ........................................................................................................................................... 131

3.3 Soldering .......................................................................................................................................... 132

3.3.1 Soldering paste.......................................................................................................................... 132

3.3.2 Reflow soldering ....................................................................................................................... 132

3.3.3 Optical inspection ...................................................................................................................... 133

3.3.4 Cleaning .................................................................................................................................... 133

3.3.5 Repeated reflow soldering ......................................................................................................... 134

3.3.6 Wave soldering.......................................................................................................................... 134

3.3.7 Hand soldering .......................................................................................................................... 134

3.3.8 Rework ...................................................................................................................................... 134

3.3.9 Conformal coating .................................................................................................................... 134

3.3.10 Casting ...................................................................................................................................... 134

3.3.11 Grounding metal covers ............................................................................................................ 134

3.3.12 Use of ultrasonic processes ........................................................................................................ 134

4 Approvals .................................................................................................................. 135

4.1 Product certification approval overview ............................................................................................. 135

4.2 US Federal Communications Commission notice ............................................................................... 136

4.2.1 Safety warnings review the structure ......................................................................................... 136

4.2.2 Declaration of conformity .......................................................................................................... 136

4.2.3 Modifications ............................................................................................................................ 137

4.3 Innovation, Science and Economic Development Canada notice ....................................................... 138

4.3.1 Declaration of Conformity ......................................................................................................... 138

4.3.2 Modifications ............................................................................................................................ 138

4.4 European Conformance CE mark ...................................................................................................... 140

5 Product testing ......................................................................................................... 141

5.1 u-blox in-series production test ......................................................................................................... 141

5.2 Test parameters for OEM manufacturer ............................................................................................ 142

5.2.1 “Go/No go” tests for integrated devices .................................................................................... 142

5.2.2 Functional tests providing RF operation ..................................................................................... 142

Appendix ........................................................................................................................ 144

A Migration between SARA-U2 and LARA-R2 ........................................................... 144

A.1 Overview .......................................................................................................................................... 144

A.2 Pin-out comparison between SARA-U2 and LARA-R2 ....................................................................... 148

A.3 Schematic for SARA-U2 and LARA-R2 integration ............................................................................. 150

B Glossary .................................................................................................................... 151

Related documents......................................................................................................... 153

Revision history .............................................................................................................. 154

Contact ............................................................................................................................ 155

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1 System description

1.1 Overview

The LARA-R2 series comprises LTE Cat 1 / 3G / 2G multi-mode modules supporting up to four LTE bands, up to two 3G UMTS/HSPA bands and up to two 2G GSM/(E)GPRS bands for voice and/or data transmission in the very small LARA LGA form-factor (26.0 x 24.0 mm, 100-pin), easy to integrate in compact designs:

 LARA-R202 is designed mainly for operation in America (on AT&T LTE and 3G network)  LARA-R203 is designed mainly for operation in America (on AT&T LTE network)  LARA-R204 is designed primarily for operation in North America (on Verizon network)  LARA-R211 is designed primarily for operation in Europe, Asia and other countries  LARA-R220 is designed mainly for operation in Japan (on NTT DoCoMo LTE network)  LARA-R280 is designed mainly for operation in Asia, Oceania and other countries, on LTE and 3G networks

LARA-R2 series modules are form-factor compatible with u-blox SARA, LISA and TOBY cellular module families: this facilitates easy migration from u-blox GSM/GPRS, CDMA, UMTS/HSPA, and LTE high data rate modules, maximizes the investments of customers, simplifies logistics, and enables very short time-to-market.

The modules are ideal for applications that are transitioning to LTE from 2G and 3G, due to the long term availability and scalability of LTE networks.

With a range of interface options and an integrated IP stack, the modules are designed to support a wide range of data-centric applications. The unique combination of performance and flexibility make these modules ideally suited for medium speed M2M applications, such as smart energy gateways, remote access video cameras, digital signage, telehealth and telematics.

LARA-R2 series modules provide Voice over LTE (VoLTE)1 as well as Circuit-Switched-Fall-Back (CSFB)2 voice service over 3G / 2G (CSFB) for applications that require voice, such as security and surveillance systems.

Not supported by LARA-R204 and LARA-R280 modules “02” product version, LARA-R220 modules “62” product version. Not supported by LARA-R203, LARA-R204 and LARA-R220 modules.

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Model

Region

Radio Access Technology

Positioning

Interfaces

Audio

Features

Grade

LTE Bands

UMTS Bands

GSM Bands

GNSS via modem

AssistNow Software

CellLocate

UART

USB 2.0

HSIC *

SDIO *

DDC (I

GPIOs

Analog audio

Digital audio

Network indication

VoLTE

Antenna supervisor

Rx Diversity

Jamming detection

Embedded TCP/UDP stack

Embedded HTTP,FTP,SSL

FOTA

eCall / ERA GLONASS

Dual stack IPv4/IPv6

Standard

Professional

Automotive

LARA-R202

North

America

2,4

5,12

850

1900

● ● ●

1 1 1 1 1 9

● ● ● ● ● □ ● ● ● ●

LARA-R203

North

America

2,4,12

● ● ●

1 1 1 1 1 9

● ● ● ● ●

□

● ● ● ●

LARA-R204

North

America

4,13

□ □ □

1 1 1 1 1 9 □ ● □ ●

● □ ● ● ● ●

LARA-R211

Europe,

APAC

3,7,20

900

1800

□ □ □

1 1 1 1 1 9 ● ● ● ●

● □ ● ● ● □ ●

LARA-R220

Japan

1,19

● ● ●

1 1 1 1 1 9

□ ● □ ● ● □ ● ● ● ●

LARA-R280

APAC

3,8,28

2100

● ● ●

1 1 1 1 1 9

● ● ■ ● ● □ ● ● ● ●

● = Available in any firmware

■ = CSFB only

□ = Available in future firmware

* = HW ready

Table 1 summarizes the main features and interfaces of LARA-R2 series modules.

Table 1: LARA-R2 series main features summary

LTE band 12 is a superset that includes band 17: the LTE band 12 is supported along with Multi-Frequency Band Indicator (MFBI) feature

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4G LTE

3G UMTS/HSDPA/HSUPA

2G GSM/GPRS/EDGE

3GPP Release 9 Long Term Evolution (LTE) Evolved Univ.Terrestrial Radio Access (E-UTRA) Frequency Division Duplex (FDD) DL Rx diversity

3GPP Release 9 High Speed Packet Access (HSPA) UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD) DL Rx Diversity

3GPP Release 9 Enhanced Data rate GSM Evolution (EDGE) GSM EGPRS Radio Access (GERA) Time Division Multiple Access (TDMA) DL Advanced Rx Performance Phase 1

Band support4:

 LARA-R202:

 Band 12 (700 MHz)

 Band 5 (850 MHz)  Band 4 (1700 MHz)  Band 2 (1900 MHz)

Band support:

 LARA-R202:

 Band 5 (850 MHz)  Band 2 (1900 MHz)

Band support:

 LARA-R203:

 Band 12 (700 MHz)

 Band 4 (1700 MHz)  Band 2 (1900 MHz)

 LARA-R204:

 Band 13 (750 MHz)  Band 4 (1700 MHz)

 LARA-R211:

 Band 20 (800 MHz)  Band 3 (1800 MHz)  Band 7 (2600 MHz)

 LARA-R211:

 E-GSM 900 MHz  DCS 1800 MHz

 LARA-R220:

 Band 19 (850 MHz)  Band 1 (2100 MHz)

 LARA-R280:

 Band 28 (750 MHz)  Band 8 (900 MHz)  Band 3 (1800 MHz)

 LARA-R280:

 Band 1 (2100 MHz)

LTE Power Class  Power Class 3 (23 dBm)

UMTS/HSDPA/HSUPA Power Class  Class 3 (24 dBm)

GSM/GPRS (GMSK) Power Class

 Power Class 4 (33 dBm) for E-GSM band  Power Class 1 (30 dBm) for DCS band

EDGE (8-PSK) Power Class

 Power Class E2 (27 dBm) for E-GSM band  Power Class E2 (26 dBm) for DCS band

Data rate  LTE category 1:

up to 10.3 Mb/s DL, 5.2 Mb/s UL

Data rate  HSDPA category 8:

up to 7.2 Mb/s DL

 HSUPA category 6:

up to 5.76 Mb/s UL

Data Rate6  GPRS multi-slot class 33

, CS1-CS4,

up to 107 kb/s DL, up to 85.6 kb/s UL

 EDGE multi-slot class 33

, MCS1-MCS9,

up to 296 kb/s DL, up to 236.8 kb/s UL

Table 2 reports a summary of cellular radio access technologies characteristics of LARA-R2 series modules.

Table 2: LARA-R2 series LTE, 3G and 2G characteristics

LARA-R2 series modules support all the E-UTRA channel bandwidths for each operating band according to 3GPP TS 36.521-1 [13]. LTE band 12 is a superset that includes band 17: the LTE band 12 is supported along with Multi-Frequency Band Indicator (MFBI) feature GPRS/EDGE multi-slot class determines the number of timeslots available for upload and download and thus the speed at which data can

be transmitted and received, with higher classes typically allowing faster data transfer rates.

GPRS/EDGE multi-slot class 33 implies a maximum of 5 slots in DL (reception) and 4 slots in UL (transmission) with 6 slots in total.

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Cellular

Base-band

processor

Memory

Power Management Unit

26 MHz

32.768 kHz

ANT1

transceiver

ANT2

V_INT (I/O)

V_BCKP (RTC)

VCC (Supply)

SIM

USB

HSIC

Power On

External Reset

PAs

LNAs Filters

Filters

Duplexer

Filters

PAs

LNAs Filters

Filters

Duplexer

Filters

LNAs FiltersFilters

Switch

DDC(I2C)

SDIO

UART

ANT_DET

Host Select

GPIO

Digital audio (I2S)

1.2 Architecture

Figure 1 summarizes the internal architecture of LARA-R2 series modules.

Figure 1: LARA-R2 series modules simplified block diagram

LARA-R2 series modules internally consists of the RF, Baseband and Power Management sections here described with more details than the simplified block diagrams of Figure 1.

RF section

The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF switches. Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port (ANT1) of the

module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna switch. Dual receiving paths are implemented according to LTE Receiver Diversity radio technology supported by the

modules as LTE category 1 User Equipments: incoming signal is received through the primary (ANT1) and the secondary (ANT2) antenna input ports which are connected to the RF transceiver via specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.

 RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx, down-conversion and

demodulation of the dual RF signals for Rx. The RF transceiver contains:

Single chain high linearity receivers with integrated LNAs for multi band multi mode operation, Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM, RF synthesizer, VCO.

 Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver  RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx path  SAW duplexers and band pass filters separate the Tx and Rx signal paths and provide RF filtering  26 MHz voltage-controlled temperature-controlled crystal oscillator generates the clock reference in

active-mode or connected-mode.

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Baseband and power management section

The Baseband and Power Management section is composed of the following main elements:

 A mixed signal ASIC, which integrates

Microprocessor for control functions DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths Memory interface controller Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces Interfaces to RF transceiver ASIC

 Memory system, which includes NAND flash and LPDDR2 RAM  Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC  Voltage sources for external use: V_BCKP and V_INT  Hardware power on  Hardware reset  Low power idle-mode support  32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can be set by

enable power saving configuration using the AT+UPSV command.

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Function

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

51, 52, 53

Module supply input

VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes.

See section 1.5.1 for description and requirements. See section 2.2.1 for external circuit design-in.

GND

1, 3, 5, 14, 20, 22, 30, 32, 43, 50, 54, 55, 57, 58, 60, 61, 63, 64, 65-96

N/A

Ground

GND pins are internally connected each other. External ground connection affects the RF and thermal

performance of the device. See section 1.5.1 for functional description.

See section 2.2.1 for external circuit design-in.

V_BCKP

I/O

RTC supply input/output

V_BCKP = 1.8 V (typical) generated by internal regulator when valid VCC supply is present.

See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in.

V_INT

4 O Generic Digital Interfaces supply output

V_INT = 1.8 V (typical), generated by internal DC/DC regulator when the module is switched on.

Test-Point for diagnostic access is recommended. See section 1.5.3 for functional description.

See section 2.2.3 for external circuit design-in.

System

PWR_ON

15 I Power-on input

Internal 10 k pull-up resistor to V_BCKP. See section 1.6.1 for functional description.

See section 2.3.1 for external circuit design-in.

RESET_N

18 I External reset input

Internal 10 k pull-up resistor to V_BCKP. Test-Point for diagnostic access is recommended. See section 1.6.3 for functional description.

See section 2.3.2 for external circuit design-in.

HOST_SELECT

I/O

Selection of module / host configuration

Not supported by “02” and “62” product versions. Pin available to select, enable, connect, disconnect and

subsequently re-connect the HSIC interface. Test-Point for diagnostic access is recommended. See section 1.6.4 for functional description.

See section 2.3.3 for external circuit design-in.

Antenna

ANT1

I/O

Primary antenna

Main Tx / Rx antenna interface. 50  nominal characteristic impedance. Antenna circuit affects the RF performance and compliance of

the device integrating the module with applicable required certification schemes.

See section 1.7 for description and requirements. See section 2.4 for external circuit design-in.

ANT2

62 I Secondary antenna

Rx only for Rx diversity. 50  nominal characteristic impedance. Antenna circuit affects the RF performance and compliance of

the device integrating the module with applicable required certification schemes.

See section 1.7 for description and requirements. See section 2.4 for external circuit design-in.

ANT_DET

59 I Input for antenna detection

ADC for antenna presence detection function. See section 1.7.2 for functional description.

See section 2.4.2 for external circuit design-in.

1.3 Pin-out

Table 3 lists the pin-out of the LARA-R2 series modules, with pins grouped by function.

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Function

Pin Name

Pin No

I/O

Description

Remarks

SIM

VSIM

41 O SIM supply output

VSIM = 1.8 V / 3 V output as per the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in.

SIM_IO

I/O

SIM data

Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in.

SIM_CLK

38 O SIM clock

3.25 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in.

SIM_RST

40 O SIM reset

Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in.

UART

RXD

13 O UART data output

1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

TXD

12 I UART data input

1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

Internal active pull-up to V_INT. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

CTS

11 O UART clear to send output

1.8 V output, Circuit 106 (CTS) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

RTS

10 I UART ready to send input

1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DSR 6 O

UART data set ready output

1.8 V output, Circuit 107 (DSR) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

RI 7 O

UART ring indicator output

1.8 V output, Circuit 125 (RI) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DTR 9 I

UART data terminal ready input

1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

DCD 8 O

UART data carrier detect output

1.8 V input, Circuit 109 (DCD) in ITU-T V.24. Test-Point and series 0  for diagnostic access recommended. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

USB

VUSB_DET

17 I USB detect input

VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface.

If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access recommended.

See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D-

I/O

USB Data Line D-

USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0) 30  nominal common mode impedance (Z

)

Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [9] are part of the USB pin driver and need not be provided externally.

If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended.

See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

USB_D+

I/O

USB Data Line D+

USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

90  nominal differential impedance (Z0) 30  nominal common mode impedance (Z

)

Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [9] are part of the USB pin driver and need not be provided externally.

If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended

See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.

HSIC

HSIC_DATA

I/O

HSIC USB data line

Not supported by “02” and “62” product versions. USB High-Speed Inter-Chip compliant interface for AT

commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic.

50  nominal characteristic impedance. Test-Point for diagnostic / FW update access is recommended. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

HSIC_STRB

100

I/O

HSIC USB strobe line

Not supported by “02” and “62” product versions. HSIC interface for AT commands, data communication, FOAT,

FW update by u-blox EasyFlash tool and diagnostic. 50  nominal characteristic impedance. Test-Point for diagnostic / FW update access is recommended. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in.

DDC

SCL

27 O I2C bus clock line

1.8 V open drain, for communication with I2C-slave devices. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SDA

I/O

I2C bus data line

1.8 V open drain, for communication with I2C-slave devices. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SDIO

SDIO_D0

I/O

SDIO serial data [0]

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

SDIO_D1

I/O

SDIO serial data [1]

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDIO_D2

I/O

SDIO serial data [2]

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDIO_D3

I/O

SDIO serial data [3]

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDIO_CLK

45 O SDIO serial clock

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

SDIO_CMD

I/O

SDIO command

Not supported by “02” and “62” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

Audio

I2S_TXD

O / I/O

I2S transmit data / GPIO

I2S transmit data output, alternatively configurable as GPIO. I2S not supported by LARA-R204-02B and LARA-R220-62B. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in.

I2S_RXD

I / I/O

I2S receive data / GPIO

I2S receive data input, alternatively configurable as GPIO. I2S not supported by LARA-R204-02B and LARA-R220-62B. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in.

I2S_CLK

I/O / I/O

I2S clock / GPIO

I2S serial clock, alternatively configurable as GPIO. I2S not supported by LARA-R204-02B and LARA-R220-62B. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in.

I2S_WA

I/O / I/O

I2S word alignment / GPIO

I2S word alignment, alternatively configurable as GPIO. I2S not supported by LARA-R204-02B and LARA-R220-62B. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in.

Clock output

GPIO6

19 O Clock output

1.8 V configurable clock output. See section 1.11 for functional description. See section 2.7 for external circuit design-in.

GPIO

GPIO1

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in.

GPIO2

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in.

GPIO3

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

GPIO4

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in.

GPIO5

I/O

GPIO

1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in.

Reserved

RSVD

N/A

RESERVED pin

This pin must be connected to ground. See sections 1.13 and 2.9

RSVD

31, 97, 98

N/A

RESERVED pin

Internally not connected. Leave unconnected. See sections 1.13 and 2.9

Table 3: LARA-R2 series modules pin definition, grouped by function

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General Status

Operating Mode

Definition Power-down

Not-Powered Mode

VCC supply not present or below operating range: module is switched off.

Power-Off Mode

VCC supply within operating range and module is switched off.

Normal operation

Idle-Mode

Module processor core runs with 32 kHz reference generated by the internal oscillator.

Active-Mode

Module processor core runs with 26 MHz reference generated by the internal oscillator.

Connected-Mode

RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.

Mode

Description

Transition between operating modes

Not-Powered

Module is switched off. Application interfaces are not accessible.

When VCC supply is removed, the module enters not-powered mode. When in not-powered mode, the modules cannot be switched on by

PWR_ON, RESET_N or RTC alarm. When in not-powered mode, the modules can be switched on applying

VCC supply (see 1.6.1) so that the module switches from not-powered to active-mode.

Power-Off

Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2).

Application interfaces are not accessible.

When the module is switched off by an appropriate switch-off event (see 1.6.2), the module enters power-off mode from active-mode.

When in power-off mode, the modules can be switched on by PWR_ON, RESET_N or RTC alarm (see 1.6.1): the module switches from power-off to active-mode.

When in power-off mode, the modules enter not-powered mode by removing VCC supply.

Idle

Module is switched on with application interfaces temporarily disabled or suspended: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption.

The module enters the low power idle-mode whenever possible if power saving is enabled by AT+UPSV (see u-blox AT Commands Manual [2]) reducing power consumption (see 1.5.1.5).

The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active-mode according to power saving and HW flow control settings (see 1.9.1.3, 1.9.1.4).

Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [2]).

The module automatically switches from active-mode to idle-mode whenever possible if power saving is enabled (see sections 1.5.1.5,

1.9.1.4, 1.9.2.4 and to the u-blox AT Commands Manual [2], AT+UPSV command).

The module wakes up from idle to active mode in the following events:

 Automatic periodic monitoring of the paging channel for the

paging block reception according to network conditions (see

1.5.1.4, 1.9.1.4)

 Automatic periodic enable of the UART interface to receive and

send data, if AT+UPSV=1 power saving is set (see 1.9.1.4)

 Data received on UART interface, according to HW flow control

(AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)

 RTS input set ON by the host DTE, with HW flow control disabled

and AT+UPSV=2 (see 1.9.1.4)

 DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4)  USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2)  The connected USB host forces a remote wakeup of the module

as USB device (see 1.9.2.4)

 The connected u-blox GNSS receiver forces a wakeup of the

cellular module using the GNSS Tx data ready function over the GPIO3 pin (see 1.9.4)

 The connected SDIO device forces a wakeup of the module as

SDIO host (see 1.9.5)

 RTC alarm occurs (see u-blox AT Commands Manual [2], +CALA)

1.4 Operating modes

LARA-R2 series modules have several operating modes. The operating modes defined in Table 4 and described in detail in Table 5 provide general guidelines for operation.

Table 4: Module operating modes definition

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Mode

Description

Transition between operating modes

Active

The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and to the u-blox AT Commands Manual [2]).

When the module is switched on by an appropriate power-on event (see 2.3.1), the module enters active-mode from not-powered or power-off mode.

If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see idle to active transition description).

When a voice call or a data call is initiated, the module switches from active-mode to connected-mode.

Connected

A voice call or a data call is in progress. The module is ready to communicate with an

external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and the u-blox AT Commands Manual [2]).

When a data or voice connection is initiated, the module enters connected-mode from active-mode.

Connected-mode is suspended if Tx/Rx data is not in progress, due to connected discontinuous reception and fast dormancy capabilities of the module and according to network environment settings and scenario. In such case, the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+UPSV command, the module automatically switches to idle-mode whenever possible. Vice-versa, the module wakes up from idle to active mode and then connected mode if RF Tx/Rx is necessary.

When a data connection is terminated, the module returns to the active-mode.

Table 5: Module operating modes description

Switch ON:

• Apply VCC

If power saving is enabled and there is no activity for a defined time interval

Any wake up event described in the module operating modes summary table above

Incoming/outgoing call or other dedicated device network communication

No RF Tx/Rx in progress, Call terminated, Communication dropped

Remove VCC

Switch ON:

• PWR_ON

• RTC alarm

• RESET_N

Not

powered

Power off

ActiveConnected Idle

Switch OFF:

• AT+CPWROFF

• PWR_ON

LARA-R2 series - System Integration Manual

Figure 2 describes the transition between the different operating modes.

Figure 2: Operating modes transition

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VCC

LARA-R2 series

(except LARA-R211)

Power

Management

Unit

Memory

Baseband

Processor

Transceiver

RF PMU

LTE PA

VCC

LARA-R211

Power

Management

Unit

Memory

Baseband

Processor

Transceiver

RF PMU

LTE / 2G PAs

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input. The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit:

all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators, including V_BCKP Real Time Clock supply, V_INT digital interfaces supply and VSIM SIM card supply.

During operation, the current drawn by the LARA-R2 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the pulse of current consumption during GSM transmitting bursts at maximum power level in connected-mode (as described in section 1.5.1.2) to the low current consumption during low power idle-mode with power saving enabled (as described in section 1.5.1.5).

LARA-R211 modules provide separate supply inputs over the three VCC pins:

 VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of

the total current drawn of the module when RF transmission is enabled during a voice/data call

 VCC pin #51 represents the supply input for the internal baseband Power Management Unit and the internal

transceiver, demanding minor part of the total current drawn of the module when RF transmission is enabled during a voice/data call

Figure 3 provides a simplified block diagram of LARA-R2 series modules internal VCC supply routing.

Figure 3: LARA-R2 series modules internal VCC supply routing simplified block diagram

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Item

Requirement

Remark

VCC nominal voltage

Within VCC normal operating range:

3.30 V min. / 4.40 V max

RF performance is guaranteed when VCC PA voltage is inside the normal operating range limits. RF performance may be affected when VCC PA voltage is outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits.

VCC voltage during normal operation

Within VCC extended operating range:

3.00 V min. / 4.50 V max

VCC voltage must be above the extended operating range minimum limit to switch-on the module. The module may switch-off when the VCC voltage drops below the extended operating range minimum limit. Operation above VCC extended operating range is not recommended and may affect device reliability.

VCC average current

Support with adequate margin the highest averaged VCC current consumption value in connected-mode conditions specified in LARA-R2 series Data Sheet [1]

The highest averaged VCC current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and VCC voltage.

See 1.5.1.2, 1.5.1.4 for connected-mode current profiles.

VCC peak current

Support with margin the highest peak VCC current consumption value in connected-mode conditions specified in LARA-R2 series Data Sheet [1]

The specified highest peak of VCC current consumption occurs during GSM single transmit slot in 850/900 MHz connected-mode, in case of mismatched antenna.

See 1.5.1.2 for 2G connected-mode current profiles.

VCC voltage drop during 2G Tx slots

Lower than 400 mV

VCC voltage drop directly affects the RF compliance with applicable certification schemes.

Figure 5 describes VCC voltage drop during Tx slots.

VCC voltage ripple during 2G/3G/LTE Tx

Noise in the supply has to be minimized

VCC voltage ripple directly affects the RF compliance with applicable certification schemes. Figure 5 describes VCC voltage ripple during Tx slots.

VCC under/over-shoot at start/end of Tx slots

Absent or at least minimized

VCC under/over-shoot directly affects the RF compliance with applicable certification schemes. Figure 5 describes VCC voltage under/over-shoot.

1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6.

VCC supply circuit affects the RF compliance of the device integrating LARA-R2 series modules

with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the VCC requirements summarized in the Table 6 are fulfilled.

Table 6: Summary of VCC supply requirements

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Time [ms]

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200 mA

60-120 mA

1900 mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

60-120 mA

10-40 mA

0.0

1.5

1.0

0.5

2.0

Time

undershoot

overshoot

ripple

drop

Voltage

3.8 V (typ)

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

unused

slot

unused

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

GSM frame

4.615 ms

(1 frame = 8 slots)

1.5.1.2 VCC current consumption in 2G connected-mode

When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts.

The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption.

If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands, at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the current consumption can reach an high peak / pulse (see LARA-R2 series Data Sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications.

During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts and it is low in the bursts unused to transmit / receive.

Figure 4 shows an example of the module current consumption profile versus time in GSM talk mode.

Figure 4: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)

Figure 5 illustrates VCC voltage profile versus time during a GSM call, according to the related VCC current consumption profile described in Figure 4.

Figure 5: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot)

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Time [ms]

RX slot

unused

slot

MON

slot

unused

slot

unused

slot

MON

slot

unused

slot

GSM frame

4.615 ms

(1 frame = 8 slots)

Current [A]

200mA

60-130mA

Peak current depends

on TX power and

actual antenna load

GSM frame

4.615 ms

(1 frame = 8 slots)

1600 mA

0.0

1.5

1.0

0.5

2.0

When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the 3GPP specifications the maximum Tx RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as can be in case of a 2G single-slot call.

The multi-slot transmission power can be further reduced by configuring the actual Multi-Slot Power Reduction profile with the dedicated AT command, AT+UDCONF=40 (see the u-blox AT Commands Manual [2]).

If the module transmits in GPRS class 12 in the 850 or 900 MHz bands, at the maximum RF power control level, the current consumption can reach a quite high peak but lower than the one achievable in 2G single-slot mode. This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to 2G TDMA.

If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications.

Figure 6 reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive.

Figure 6: VCC current consumption profile versus time during a 2G GPRS/EDGE multi-slot connection (4 TX slots, 1 RX slot)

In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 6, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well.

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Time

[ms]

3G frame

10 ms

(1 frame = 15 slots)

Current [mA]

Current consumption value

depends on TX power and

actual antenna load

170 mA

1 slot

666 µs

850 mA

300

200

100

500

400

600

700

1.5.1.3 VCC current consumption in 3G connected mode

During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA).

The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a maximum rate of 1.5 kHz.

There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case.

In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins is considerable (see the “Current consumption” section in LARA-R2 series Data Sheet [1]). At the lowest output RF power (approximately 0.01 µW or –50 dBm), the current drawn by the internal power amplifier is strongly reduced. The total current drawn by the module at the VCC pins is due to baseband processing and transceiver activity.

Figure 7 shows an example of current consumption profile of the module in 3G WCDMA/HSPA continuous transmission mode.

Figure 7: VCC current consumption profile versus time during a 3G connection (TX and RX continuously enabled)

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Time

[ms]

Current [mA]

Current consumption value

depends on TX power and

actual antenna load

1 Slot

1 Resource Block

(0.5 ms)

1 LTE Radio Frame

(10 ms)

300

200

100

500

400

600

700

1.5.1.4 VCC current consumption in LTE connected-mode

During an LTE connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation used in LTE radio access technology.

The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz.

The current consumption profile is similar to that in 3G radio access technology. Unlike the 2G connection mode, which uses the TDMA mode of operation, there are no high current peaks since transmission and reception are continuously enabled in FDD.

In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins is considerable (see the “Current consumption” section in LARA-R2 series Data Sheet [1]). At the lowest output RF power (approximately 0.1 µW or –40 dBm), the current drawn by the internal power amplifier is strongly reduced and the total current drawn by the module at the VCC pins is due to baseband processing and transceiver activity.

Figure 8 shows an example of the module current consumption profile versus time in LTE connected-mode. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1].

Figure 8: VCC current consumption profile versus time during LTE connection (TX and RX continuously enabled)

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~50 ms

IDLE MODE ACTIVE MODE IDLE MODE

Active Mode

Enabled

Idle Mode

Enabled

2G case: 0.44-2.09 s 3G case: 0.61-5.09 s LTE case: 0.27-2.51 s

IDLE MODE

~50 ms

ACTIVE MODE

Time [s]

Current [mA]

Time [ms]

Current [mA]

Enabled

100

1.5.1.5 VCC current consumption in cyclic idle/active-mode (power saving enabled)

The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, reducing current consumption.

When the power saving configuration is enabled and the module is registered or attached to a network, the module automatically enters the low power idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the 2G / 3G / LTE system requirements, even if connected-mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active-mode, to enable the reception of paging block. In between, the module switches to low power idle-mode. This is known as discontinuous reception (DRX).

The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode.

The time period between two paging block receptions is defined by the network. This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell:

 In case of 2G radio access technology, the paging period can vary from 470.8 ms (DRX = 2, length of 2 x 51

2G frames = 2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms)

 In case of 3G radio access technology, the paging period can vary from 640 ms (DRX = 6, i.e. len gth of 2

3G frames = 64 x 10 ms) up to 5120 ms (DRX = 9, length of 29 3G frames = 512 x 10 ms).

 In case of LTE radio access technology, the paging period can vary from 320 ms (DRX = 5, i.e. length of 2

LTE frames = 32 x 10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms).

Figure 9 illustrates a typical example of the module current consumption profile when power saving is enabled. The module is registered with network, automatically enters the low power idle-mode and periodically wakes up to active-mode to monitor the paging channel for the paging block reception. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1]).

Figure 9: VCC current consumption profile with power saving enabled and module registered with the network: the module is in low-power idle-mode and periodically wakes up to active-mode to monitor the paging channel for paging block reception

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ACTIVE MODE

2G case: 0.44-2.09 s 3G case: 0.61-5.09 s

LTE case: 0.32-2.56 s

Paging period

Time [s]

Current [mA]

Time [ms]

Current [mA]

Enabled

100

1.5.1.6 VCC current consumption in fixed active-mode (power saving disabled)

Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle-mode whenever possible: the module remains in active-mode.

The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. Figure 10 illustrates a typical example of the module current consumption profile when power saving is disabled.

In such case, the module is registered with the network and while active-mode is maintained, the receiver is periodically activated to monitor the paging channel for paging block reception. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1].

Figure 10: VCC current consumption profile with power saving disabled and module registered with the network: active-mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception

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Baseband

Processor

VCC

V_BCKP

Linear

LDO

RTC

Power

Management

LARA-R2 series

32 kHz

1.5.2 RTC supply input/output (V_BCKP)

The V_BCKP pin of LARA-R2 series modules connects the supply for the Real Time Clock (RTC) and Power-On internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 11. The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range, with the module switched off or switched on.

Figure 11: RTC supply input/output (V_BCKP) and 32 kHz RTC timing reference clock simplified block diagram

The RTC provides the module time reference (date and time) that is used to set the wake-up interval during the low power idle-mode periods, and is able to make available the programmable alarm functions.

The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid range (specified in the “Input characteristics of Supply/Power pins” table in LARA-R2 series Data Sheet [1]). The RTC can be supplied from an external back-up battery through the V_BCKP, when the main module voltage supply is not applied to the VCC pins. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module.

Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).

The RTC has very low current consumption, but is highly temperature dependent. For example, V_BCKP current consumption at the maximum operating temperature can be higher than the typical value at 25 °C specified in the “Input characteristics of Supply/Power pins” table in the LARA-R2 series Data Sheet [1].

If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range. This has no impact on cellular connectivity, as all the module functionalities do not rely on date and time setting.

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Baseband

Processor

VCC

V_INT

Switching

Step-Down

Digital I/O

Interfaces

Power

Management

LARA-R2 series

1.5.3 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the LARA-R2 series modules is connected to an internal 1.8 V supply with current capability specified in the LARA-R2 series Data Sheet [1]. This supply is internally generated by a switching stepdown regulator integrated in the Power Management Unit and it is internally used to source the generic digital I/O interfaces of the cellular module, as described in Figure 12. The output of this regulator is enabled when the module is switched on and it is disabled when the module is switched off.

Figure 12: LARA-R2 series interfaces supply output (V_INT) simplified block diagram

The switching regulator operates in Pulse Width Modulation (PWM) mode for greater efficiency at high output loads and it automatically switches to Pulse Frequency Modulation (PFM) power save mode for greater efficiency at low output loads. The V_INT output voltage ripple is specified in the LARA-R2 series Data Sheet [1].

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Baseband Processor

PWR_ON

LARA-R2 series

V_BCKP

Power-on

Power

Management

Power-on

10k

1.6 System function interfaces

1.6.1 Module power-on

When the LARA-R2 series modules are in the not-powered mode (switched off, i.e. the VCC module supply is not applied), they can be switched on as following:

 Rising edge on the VCC input to a valid voltage for module supply, i.e. applying module supply: the modules

switch on if the VCC supply is applied, starting from a voltage value of less than 2.1 V, with a rise time from

2.3 V to 2.8 V of less than 4 ms, reaching a proper nominal voltage value within VCC operating range.

Alternately, in case for example the fast rise time on VCC rising edge cannot be guaranteed by the application, LARA-R2 series modules can be switched on from not-powered mode as following:

 RESET_N input pin is held low by the external application during the VCC rising edge, so that the modules

will switch on when the external application releases the RESET_N input pin from the low logic level after that the VCC supply voltage stabilizes at its proper nominal value within the operating range

 PWR_ON input pin is held low by the external application during the VCC rising edge, so that the modules

will switch on when the external application releases the PWR_ON input pin from the low logic level after that the VCC supply voltage stabilizes at its proper nominal value within the operating range

When the LARA-R2 series modules are in the power-off mode (i.e. properly switched off as described in section

1.6.2, with valid VCC module supply applied), they can be switched on as following:

 Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time period: the

modules start the internal switch-on sequence when the external application releases the PWR_ON pin from the low logic level after that it has been set low for an appropriate time period

 Rising edge on the RESET_N pin, i.e. releasing the pin from the low level, as that the pin is normally set high

by an internal pull-up: the modules start the internal switch-on sequence when the external application releases the RESET_N pin from the low logic level

 RTC alarm, i.e. pre-programmed alarm by AT+CALA command (see u-blox AT Commands Manual [2]).

As described in Figure 13, the LARA-R2 series PWR_ON input is equipped with an internal active pull-up resistor to the V_BCKP supply: the PWR_ON input voltage thresholds are different from the other generic digital interfaces. Detailed electrical characteristics are described in LARA-R2 series Data Sheet [1].

Figure 13: LARA-R2 series PWR_ON input description

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VCC

V_BCKP

PWR_ON

RESET_N

V_INT

Internal Reset

System State

BB Pads State

Internal Reset → Operationa l Operational

Tristate / Floating

Internal Reset

OFF

Start of interface

configuration

Module interfaces

are configured

Start-up

event

Figure 14 shows the module switch-on sequence from the not-powered mode, describing the following phases:

 The external supply is applied to the VCC module supply inputs, representing the start-up event.  The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value.  The PWR_ON and the RESET_N pins suddenly rise to high logic level due to internal pull-ups.  All the generic digital pins of the module are tri-stated until the switch-on of their supply source (V_INT).  The internal reset signal is held low: the baseband core and all the digital pins are held in the reset state. The

reset state of all the digital pins is reported in the pin description table of LARA-R2 series Data Sheet [1].

 When the internal reset signal is released, any digital pin is set in a proper sequence from the reset state to

the default operational configured state. The duration of this pins’ configuration phase differs within generic digital interfaces and the USB interface due to host / device enumeration timings (see section 1.9.2).

 The module is fully ready to operate after all interfaces are configured.

Figure 14: LARA-R2 series switch-on sequence description

The greeting text can be activated by means of +CSGT AT command (see u-blox AT Commands Manual [2]) to notify the external application that the module is ready to operate (i.e. ready to reply to AT commands) and the first AT command can be sent to the module, given that autobauding has to be disabled on the UART to let the module sending the greeting text: the UART has to be configured at fixed baud rate (the baud rate of the application processor) instead of the default autobauding, otherwise the module does not know the baud rate to be used for sending the greeting text (or any other URC) at the end of the internal boot sequence.

The Internal Reset signal is not available on a module pin, but the host application can monitor the V_INT

pin to sense the start of the LARA-R2 series module switch-on sequence.

Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage

driven by an external application should be applied to any generic digital interface of the module.

Before the LARA-R2 series module is fully ready to operate, the host application processor should not send

any AT command over the AT communication interfaces (USB, UART) of the module.

The duration of the LARA-R2 series modules’ switch-on routine can vary depending on the application /

network settings and the concurrent module activities.

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+ 125 hidden pages

u blox 1DIQN3NN System Integrator Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Contents

1 System description

1.1 Overview

1.2 Architecture

RF section

Baseband and power management section

1.3 Pin-out

1.4 Operating modes

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

1.5.1.1 VCC supply requirements

1.5.1.2 VCC current consumption in 2G connected-mode

1.5.1.3 VCC current consumption in 3G connected mode

1.5.1.4 VCC current consumption in LTE connected-mode

1.5.1.5 VCC current consumption in cyclic idle/active-mode (power saving enabled)

1.5.1.6 VCC current consumption in fixed active-mode (power saving disabled)

1.5.2 RTC supply input/output (V_BCKP)

1.5.3 Generic digital interfaces supply output (V_INT)

1.6 System function interfaces

1.6.1 Module power-on