Ubiquiti M11DB User Manual
Dual-Band 1x1 with 1 SS
802.11a/b/g/n/ac WLAN SoC
Model:1x1-DB
Device Specification
1 Introduction
1.1 General description
The Dual-Band 1x1 SOC model:1x1-DB with Qualcomm® VIVETM 802.11ac technology is a highly integrated wireless local area network (WLAN) system-on-chip (SoC) for 2.4 &5 GHz 802.11ac. The Dual-Band 1x1 SOC
model:
and physical layer (PHY) management and provides host offload of other high level networking tasks. It enables
high-performance 1x1 MIMO with 1 spatial streams for wireless applications demanding the highest robust link quality and maximum throughput and range. The DualBand 1x1 SOC integrates a multi-protocol MAC, PHY, analog-todigital/ digital-to-analog converters (ADC/ DAC), 1x1 radio transceivers, and PCIE interface in an all CMOS device
for low power consumption and small formfactor applications.
The Dual-Band 1x1 SOC model:1x1-DB implements half-duplex OFDM, Maximal Likelihood (ML) decoding,
LowDensity Parity Check (LDPC), Maximal Ratio Combining
(MRC), Space Time Block Code (STBC), and On-Chip One Time Programmable (OTP) memory to eliminate the
need for an external flash and to further reduce the external component count and BOM cost. The Dual-Band 1x1
SOC model:
802.11e quality of service (QoS).The Dual-Band 1x1 SOC supports up to one simultaneous spatial streams integrating one Tx and four Rx chains for high throughput and extended coverage. Tx chains combine PHY in-phase (I) and
quadrature (Q) signals, convert them to the desired frequency, and drive the RF signal through external power amplifiers (PAs). Rx chains receive from antennas through external LNAs. The frequency synthesizer supports 1-MHz
1x1-DB is a synthesizer WLAN radio
1x1-DB
supports 802.11 wireless MAC protocol, 802.11i security, Wi-Fi offload, error recovery, and
. It includes a CPU and memory for WLAN media access layer (MAC)
steps to match frequencies defined by IEEE 802.11a/b/g/n/ ac specifications. The Dual-Band 1x1 SOC model:1x1DB supports frame data transfer
to and from the host using a PCIE interface that supports interrupt generation and reporting and status reporting.
Other external interfaces include EEPROM and GPIOs.
1X1-2.4G, 1x1-5G
Dual-Band 1x1 with 1 SS 802.11ac/a/b/g/n WLAN SoC
model:1x1-DB
Device Specification
Introduction
General
ac
WLAN
1.2 Features
1x1 technology improves effective throughput and range over existing 802.11a/b/g/n/
products
Support for up to four spatial streams
Support for 48-MHz crystal
156-pin, 12 mm x 12 mm DRQFN package
Package footprint compatible with QCA9889
Supports 20 MHz at 2.4 & 5 GHz
Supports up to 64 QAM
TCP and UDP checksum offload
Dynamic bandwidth switching
Per-packet switching between 1SS/20 MHz
Maximal likelihood (ML) decoding
Supports spatial multiplexing, cyclic-delay diversity (CDD), low-density parity check (LDPC),
maximal ratio combining (MRC), Space Time Block Code (STBC)
AMSDU and AMPDU frame aggregation
802.11e-compatible bursting
Digital predistortion
Support for locationing (RSSI and RTT-based, 802.11REVmc compliant)
Supported Standards
802.11a/b/g/n/ac
Support for IEEE 802.11d, e, h, i, j, k, r, u, v time stamp, w, and z standards
CPU/Memory
Integrated CPU for Wi-Fi offload with memory
On-chip OTP memory
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