Turbo IC 29C512TI-3, 29C512TI-2, 29C512TI-1, 29C512TC-3, 29C512TC-2 Datasheet

HIGH SPEED CMOS

1 Megabit PROGRAMMABLE and ERASABLE ROM

64K X 8 BIT FLASH PEROM

DESCRIPTION:

The Turbo IC 29C512 is a 64K x 8 Flash programmable
and erasable read only memory (PEROM) fabricated with
Turbo IC’s proprietary, high reliability, high performance
CMOS technology. Its 512K bits of memory are organized
as 64K by 8 bits. The device offers access time of 120 ns
with power dissipation below 300 mW.

The 29C512 has a 128 bytes sector program operation en­abling the entire memory to be programmed typically in less
than 5 seconds. During a program operation, the address
and a complete sector (128 bytes) of data are internally
latched, freeing the address and data bus for other micro­processor operations. The programming process is auto­matically controlled by the device using an internal control
timer. Data polling on I/O7 or a Toggle bit can be used to
detect the end of a programming cycle. In addition, the
29C512 includes an user-optional software data write mode
offering additional protection against unwanted (false) write.

The 29C512 does not require a separate high voltage to
program the device . 5 volts is all that is required.

FEA TURES:

• 120 ns Access Time

• 5 Volt Only Reprogramming

• Sector Program Operation

Single Cycle Reprogram (Erase & Program)
512 Sectors (128 bytes/sector)
Internal Address and Data Latches for 128 Bytes

• Automatic Sector Programming Operation
Internal Control Timer

• Fast Progr am Times
Page Program Cycles: 10 ms Typical
Time to Rewrite Complete Memory: 5 s
Typical Byte Program Cycle Time: 80 µs

• Software Data Protection

• Low P ower Dissipation

50 mA Active Current
30 µA CMOS Standby Current

• Direct Microprocessor End of Program Detection
Data Polling

• High Reliability CMOS Technology
Endurance: 10,000 Cycles
Data Retention: 10 years

• CMOS and TTL Compatible Inputs and Outputs

• Single 5V ± 10% Pow er Supply for Read and Program-

ming Operations

• JEDEC Approved Byte Pinout

PIN CONFIGURA TIONS:

4

3

5

2

1

6
7
8
9
10
11
12
13

303132

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

A7
A6
A5
A4
A3
A2
A1
A0

I/O0

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A15

A12 NCNCVCCWENC

32 pins PLCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17

18

19

20

21

22

23

24

25

26

27

28

NC

NC
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1

VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32

31

30

29

28

27

26

25

24

23

22

21

20

19

OE
CE
I/O6
I/O4
GND
I/O1
A0

A1

I/O0

I/O2

I/O3

I/O5

I/O7

A10

A11

A8

A14

WE

NC

A15

A7

A6

A12

NC

VCC

NC

A13

A9

32 pins PDIP

32 pins TSOP

14

29
28
27
26
25
24
23
22

21

20

19

18

17

16

15

29

30

31

32

I/O4
I/O3

I/O2

GND

15

16

17

18

A2

A3

A5

A4

29C512

PRODUCT INTRODUCTION

Turbo IC, Inc.

CHIP ENABLE (CE)

The Chip Enable input must be low to enable all read/program operations
on the device. By setting CE high, the device is disabled and the power
consumption is extremely low with the standby current below 30 µA.

ADDRESSES (A0 - A15)

The Addresses are used to select an 8 bits memory location during a
program or read operation.

PIN DESCRIPTION

OUTPUT ENABLE (OE)

The Output Enable input activates the output buffers during the read op­erations.

WRITE ENABLE (WE)

The Write Enable input initiates the programming of data into the memory.

DATA INPUT/OUTPUT (I/O0-I/O7)

Data Input/Output pins are used to read data out of the memory or to
program Data into the memory.

DEVICE OPERA TION

READ
The 29C512 is accessed like a static RAM. Read operations are initiated

by both CE and OE on low and terminated by either CE or OE returning
high. The outputs are at the high impedance state whenever CE or OE
returns high. The two line control architecture gives designers flexibility in
preventing bus contention.

PROGRAM
A program cycle is initiated when CE and WE are low and OE is high. The

address is latched internally on the falling edge of the CE or WE, which­ever occurs last. The data is latched by the rising edge of CE or WE,
whichever occurs first. Once a programming cycle has been started, the
internal timer automatically generates the program sequence to the comple­tion of the program operation.

SECTOR PROGRAM OPERATION
The device is reprogrammed on a sector basis. When a byte of data within

a sector is to be changed, data for the entire sector must be loaded into the
device. Any b yte that is not loaded during the programming of its sector will
be erased to read FFh. The programming operation of the 29C512 allows
128 bytes of data to be serially loaded into the device and then simulta­neously written into memory during the internally generated program cycle.
After the first byte has been loaded, successive bytes of data must be
loaded until the full sector of 128 bytes is loaded. Each new byte to be
written must be loaded within 300 µs of the previously loaded byte. The
sector address defined by the addresses A7 - A15 is latched by the first
CE or WE falling edge which initiates a prog ram cycle and they sta y latched
until the completion of the program cycle. Any changes in the sector ad­dresses during the load-program cycle will not affect the initially latched
sector address. Addresses A0 - A6 are used to define which bytes will be
loaded within the 128 bytes sector. The bytes may be loaded in any order
that is convenient to the user . The content of a loaded byte may be altered
at any time during the loading cycle if the maximum allowed byte-load time
(300 µs) is not exceeded. All the 128 bytes of the page are serially loaded
and are programmed in a single 10 ms program cycle

DATA POLLING
The 29C512 features DAT A P olling to indicate the completion of a prog ram

cycle to the host system. During a program cycle , an attempted read of the
last byte loaded into the page will result in the complement of the loaded
byte on I/O7, i.e., loaded 0 would be read 1. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may
be started. DATA Polling may begin at any time during the programming
cycle.

TOGGLE BIT
In addition to DATA P olling the 29C512 provides another method for deter-

mining the end of a programming or erase cycle. During a program
or erase operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining
the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION
The 29C512 has three hardware features to protect the written content of

the memory against inadvertent programming:
a) Vcc threshold detector - If Vcc is below 3 V the program capabilities of

the chip is inhibited for whatever input conditions.
b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is
not able to initiate a program cycle.
c) Write inhibit - Holding OE at low , or CE at high, or WE at high inhibits the
program cycle.

SOFTWARE DATA PROTECTION
The 29C512 offers a software controlled data program protection feature.

The device is delivered to the user with the software data protection DIS­ABLED, i.e., the device will go to the program operation as long as Vcc
exceeds 3 V and CE, WE, and OE inputs are set at program mode levels.
The 29C512 can be automatically protected against an accidental write
operation during power-up or power-down without any external circuitry by
enabling the software data protection feature. This feature is enable after
the first program cycle which includes the software algorithm. After this
operation is done the program function of the device may be performed
only if every program cycle is preceded by the software algorithm. The
device will maintain its software protect f eature for the rest of its lif e, unless
the software algorithm for disabling the protection is implemented.

PRODUCT INTRODUCTION

29C512

Turbo IC, Inc.

SOFTWARE ALGORITHM
The 29C512 has an internal register for the software algorithm which en-

ables the memory to provide the user with additional features:
a) Software Data Protect Enable
A sequence of the three dummy data writes to the memory will activate

internal EEPROM fuses during the first page write cycle. These EEPROM
fuses will reject any write attempts of new pages of data, unless the three
dummy data writes are repeated at the beginning of any page writes.

The timing for the dummy data and addresses must be the same as for a
normal program operation. A violation of the three steps program protect
sequence in data or address timing and content will abort the procedure
and reset the device to the starting point condition.

Note: Software data protect enable procedure must be performed as part
of a standard program cycle. If no additional page data is added to the
three dummy data writes, the software data protect enable procedure will
be aborted. The data protect state will be activated at the end of the pro­gram cycle. 128 bytes of data must be loaded during a Software Data
Protection Enable cycle.

Table 1 shows the required procedure for enabling the software data pro­tect:

TABLE 1

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex A0 Hex
4-131 Page Write Address Sector Data (128 Bytes)

b) Software Data Protect Disable
The software algorithm of 29C512 includes a six step sequence dummy

data programming sequence to disable the software data protect feature
described in a). The six step sequence shown in Table 2 must be per­formed at the beginning of a program cycle. A violation of the six step
program sequence in data or address timing and content will abort the
procedure and reset the chip to the starting point condition. After a soft­ware data protect disable cycle including the six step sequence has been
performed, the 29C512 does not require the use of three dummy loads
described in a) for the following program cycle. The device is at the soft­ware data protect disabled state.

Note: When six step sequence of software data protect disable procedure
is performed, if no additional bytes of data is added after the six-step write
sequence, the software data protect disable procedure will be aborted.
The data protect state will be deactivated at the end of the program period.
128 bytes of data must be loaded during a Software Data Protection dis­able cycle.

Table 2 shows the required procedure for disabling the software data pro­tect:

TABLE 2

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 20 Hex
7-134 Page Write Address Sector Data (128 Bytes)

C) Software Chip Clear (optional)
The software algorithm of 29C512 includes a sequence of six step dummy

data writing to perform a chip clear operation. Table 3 shows the six step
write sequence to perform the software chip clear operation:

TABLE 3

STEP MODE ADD.A14-A0 DATA I/O 7-0

1 Page Write 5555 Hex AA Hex
2 Page Write 2AAA Hex 55 Hex
3 Page Write 5555 Hex 80 Hex
4 Page Write 5555 Hex AA Hex
5 Page Write 2AAA Hex 55 Hex
6 Page Write 5555 Hex 10 Hex

At the end of the six step program sequence shown in Table 3, the
device automatically activates its internal timer to control the chip erase
cycle; typically takes 20 msec. After a software chip clear operation has
been completed, all 512K bit locations of memory show high level at
read operation mode.

29C512

Turbo IC, Inc.

A.C. CHARACTERISTICS - READ OPERATION

29C5121 29C512-2 29C512-3

Symbol Parameters Min Max Min Max Min Max Unit
tacc Address to 120 150 200 ns

Output Delay

tce CE to Output 120 150 200 ns

Delay
toe OE to Output 70 80 90 ns
tdf OE to Output 0 40 0 50 0 60 ns

In High Z
toh Output Hold 0 0 0 ns

from Address

Changes, Chip

Enable or

Output Enable

Whichever

Occurs First

Symbol Parameter Condition Min Max Units

Icc Active Vcc CE=OE=Vil; All I/O 50 (C) mA

Current Open, Min Read or 70 (I) mA

Write Cycle Time

Isb1 CMOS CE=Vcc-0.3 V to 30 (C) µA

Standby Vcc+1 V 100 (I) µ A
Current

Isb2 TTL Standby CE=Vih, OE=Vil, 3 mA

Current All I/O Open, Other

Inputs=Vcc Max

Iil Input Vin=Vcc Max 1 µA

Leakage
Current

Iol Output 10 µA

Leakage
Current

Vil Input Low -0.1 -0.8 V

Voltage

Vih Input High 2 Vcc+0.3 V

Voltage

Vol Output Low Iol=2.1 mA 0.45 V

Voltage

Voh Output High Ioh=-0.45 mA 2.4 V

Voltage

(C) = COMMERCIAL
(I) = INDUSTRIAL
(M) = MILITARY

tacc

ADDRESS VALIDADDRESS

CE

OE

OUTPUT HIGH-Z

toe

tce

tdf

toh

OUTPUT VALID

HIGH-Z

A.C. TEST CONDITIONS

Output Load : 1 TTL Load and Cl=100 pF
Input Rise and Fall Times : < 10 ns
Input Pulse Level : 0.45 V to 2.4V

D.C. CHARACTERISTICS

ABSOLUTE MAXIMUM STRESS RANGES *

A.C. Read Wave Forms

RECOMMENDED OPERATING CONDITIONS
Temperature Range: Commercial: 0° C to 70° C

Industrial: -40° C to 85° C

Vcc Supply Voltage:5 V ± 10%

Endurance: 10,000 Cycles/Byte (Typical)
Data Retention: 10 Y ears

* “Absolute Maximum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation sec­tion of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

TEMPERATURE

Storage: -65° C to 150° C
Under Bias: -55° C to 125° C

ALL INPUT OR OUTPUT VOLTAGES

with respect to Vss +6 V to -0.3 V

PRODUCT INTRODUCTION

29C512

Turbo IC, Inc.

OE

ADDRESS

CE

WE

DATA

toes

tas

tcs tah

toeh

tch

twp

tds

tblc

twc

tdh

HIGH-Z

DATA VALID

HIGH-Z

VALID

OE

ADDRESS

CE

WE

DATA

toes

tas

tcs tah

toeh

tch

twp

tds

tblc

twc

tdh

HIGH-Z

DATA VALID

HIGH-Z

VALID

A.C. WRITE CHARACTERISTICS

Symbol Parameter Min Max Units
tas Address Set-up Time 20 n s
tah Address Hold Time 100 ns
tcs Write Set-up Time 0 ns
tch Write Hold Time 0 ns
tcw CE Pulse Width 100 ns
twp WE Pulse Width 100 ns
toes OE Set-up Time 10 ns
toeh OE Hold Time 10 ns
tds Data Set-up Time 50 ns
tdh Data Hold Time 0 ns
tblc Byte Load Cycle 0.2 300 µs
tlp Last Byte Loaded to Data

Polling Output 500 µs

twc Write Cycle Time 10 ms

A.C. Write W ave Forms WE-Controlled

A.C. Write Wa ve Forms CE-Contr olled

29C512

Turbo IC, Inc.

PAGE MODE WRITE CHARACTERISTICS

Symbol Parameter Min Max Unit

twc Write Cycle Time 10 ms
tas Address Set-up Time 20 ns
tah Address Hold Time 100 ns
tds Data Set-up Time 50 ns
tdh Data Hold Time 0 ns
twp Write Pulse Width 100 ns
tblc Byte Load Cycle Time 0.2 300 µ s
twph Write Pulse Width High 100 ns

OE

CE

WE

A0-A6

DATA

twp

twph

tah

tas

tds

tdh

BYTE-0

BYTE-1

BYTE-2

BYTE
ADDRESS

A7-A15

SECTOR
ADDRESS

//

//

//
//
//
//
//
//
//

BYTE- 126

BYTE-127

Page Mode Write Wave Forms (1,2,3)

Note: 1. A7 through A15 must be specify the sector address during each high to low transition of WE or CE.

2. OE must be high when WE and CE are both low.

3. All bytes that are not loaded within the sector being programmed will be erased to FF.

Turbo IC, Inc.

PRODUCT INTRODUCTION

29C512

DATA Polling Characteristics

Symbol Parameter Min Max Unit

tdh Data Hold Time 10 ns
toeh OE Hold Time 10 ns
toe OE to Output Delay (1) ns
twr Wr ite Recovery Time 0 ns

Note: 1. See toe Specification in AC Characteristics - Read Operation

DATA P olling Wave Forms

WE

CE

OE

A0-A15

An

An

An

//

//

//

//

//

//

I/O7

twr

tdh toe

toeh

An An

HIGH Z

Toggle Bit Characteristics

Symbol Parameter Min Max Unit

tdh Data Hold Time 10 ns
toeh OE Hold Time 10 ns
toe OE to Output Delay (1) ns
toeh OE High Pulse 150 ns

Note: 1. See toe Specification in AC Characteristics - Read Operation

Toggle Bit Wa ve Forms (1,2,3)

WE

CE

OE

//

//

//

//

I/O6

tdh

toe

HIGH Z

toeh

Note:

1. Toggling either OE or CE or both will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Turbo IC, Inc.

29C512

Turbo IC, Inc. 2153 O'Toole Ave., Suite G, San Jose, CA 95131 Phone: [phone] Fax: [phone]

See us at www.turbo-ic.com

Rev. 2.0-8/8/97

Part Numbers & Order Inf ormation

29C512PC-2

Speed

-1 120 ns

-2 150 ns

-3 200 ns

Temperature
C -Commercial
I -Industrial

Package
J -PLCC

P -PDIP

T -TSOP

64K x 8
PEROM

TURBO IC PRODUCTS AND DOCUMENTS

1. All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.

2. Turbo IC does not assume any responsibility for any damage to the user that may result from
accidents or operation under abnormal conditions.

3. Turbo IC does not assume any responsibility for the use of any circuitry other than what

embodied in a Turbo IC product. No other circuits, patents, licenses are implied.

4. Turbo IC products are not authorized for use in life support systems or other critical systems

where component failure may endanger life. System designers should design with error de­tection and

correction, redundancy and back-up features.

PRODUCT INTRODUCTION

29C512

Turbo IC, Inc.