TSC TS393 Technical data

TS393
Dual Voltage Comparator
Pin assignment:
1. Output
2. Input A (-)
3. Input A (+)
4. Gnd
5. Input B (+)
6. Input B (-)
7. Output B
8. Vcc
Supply Voltage Range -18 V to 18V
Dual Channel Comparator
General Description
Features
Output voltage compatible with DTL, ECL, TTL,
MOS and CMOS Logic Levels
Low input bias current -25nA
Low input offset current -5.0nA
Low input offset voltage --5.0mV(max)
Input common mode range to ground level
Differential lnput voltage range equal to power
supply voltage
Very low current drain independent of supply
voltage - 0.4mA
Wide single-supply range - 2.0Vdc to 36Vdc
Split-supply range ±1.0Vdc to ±18Vdc
Block Diagram
Ordering Information
Part No. Operating Temp. Package
TS393CD DIP-8
TS393CS
0 ~ +70
o
C
SOP-8
Schematic (each comparator)
TS393 1-6 2003/12 rev. A
Absolute Maximum Rating
Supply Voltage Vcc +36 or ±18 Vdc
Differential Input Voltage V
Input Common Mode Voltage Range
Input Current (note 2)
Output Short Circuit to Ground
Output Sink Current (note 1)
Power Dissipation @ Ta=25 oC
Derate above 25
o
C
36 Vdc
IDR
V
ICR
Iin
Isc
Isink
1/Rθja
-0.3 to 36
50
Continuous
20
570
5.7
Vdc
mA
mA
mW
mW/ oC
Operating Junction Temperature Range TJ 0 ~ +125 oC
Storage Temperature Range T
Lead Temperature 1.6mm(1/16”) from case for 10Sec. T
-65 ~ +150 oC
STG
260
LEAD
o
Electrical Characteris t ic s
(VCC = 5V, T
Characteristics Symbol Test condition Min Typ Max Unit
Input Offset Voltage (note 3) Vio Ta =25 oC
Input Offset Current
Input Offset Current (note 4)
Input Common Mode
Voltage Range (note 5)
Voltage Gain
Large Signal Response
Time
Response Time (note 6)
Input Differential Voltage
(note 7)
Output Sink Current
Output Saturation Voltage
Output Leakage Current
Supply Current
LOW
Ta ≤T
; unless otherwise specified.)
HIGH
T
LOW
Iio Ta =25 oC
T
LOW
IIB Ta =25 oC
T
LOW
V
Ta =25 oC
ICR
T
LOW
A
RL ≥15K, Vcc = 15Vdc.
VOL
Ta =25
-- Vin = TTL Logic Swing.
Vref = 1.4Vdc, VRL = 5Vdc.
RL 5.1K, Ta =25
t
VRL = 5Vdc, RK = 5.1K
TLH
Ta =25
VID All Vin ≥ Gnd or V-Supply
(if used)
I
Vin-1Vdc, Vin+=0Vdc,
SINK
V
1 Vdc, Ta =25 oC
O-
VOL Vin- ≥1Vdc, Vin+=0,
I
SINK
T
LOW
IOL Vin-=0V, Vin+1Vdc, P=5Vdc.
Ta =25
Vin-=0V, Vin+1V, V
T
LOW
Icc RL = ∞, Ta =25 oC
R
= ∞, VCC =30 V
L
Ta ≤T
Ta ≤T
Ta ≤T
Ta ≤T
o
C
o
C
HIGH
HIGH
HIGH
HIGH
o
C
4mA, Ta =25 oC
Ta ≤T
o
C
Ta ≤T
HIGH
HIGH
=30Vdc
O
--
--
--
--
--
--
0
0
50
±1.0
--
±5.0
--
25
--
--
--
200
±5.0
±50
±150
250
400
V
CC
V
CC
9.0
-1.5
-2.0
--
-- 300 -- nS
--
1.3 -- uS
-- -- VCC V
60 16 -- mA
--
--
--
--
--
--
150
--
0.1
--
0.4
--
400
700
--
1000
1.0
2.5
C
mV
nA
nA
Volts
V/mV
mV
nA
mA
TS393 2-6 2003/12 rev. A
Electrical Characteris t ic s ( C ont inues)
Note 1. The max. Output current may be as high as 20mA, independent of the magnitude of V
can cause excessive heating and eventual destruction.
V
CC
, output short circuits to
CC
Note 2. This magnitude of input current will only occur if the input leads are driven more negative than ground or the
negative supply voltage. This is due to the input PNP collector base junction becoming forward biased acting as
an input clamp diode. There is also a lateral PNP parasitic transistor action on the IC chip. This phenomena can
cause the output voltage of the comparators to go to the V
voltage level (or ground if overdrive is large) during
CC
the time the input is driven negative. This will not destroy the device and normal output states will recover when
the inputs become -0.3V of ground or negative supply.
Note 3. At output switch point, V
=1.4Vdc, RS=0 with V
O
from 5Vdc to 30Vdc, and over the full input common-mode
CC
Note 4. Due to the PNP transistor inputs, bias current will flow out of the inputs, this current is essentially constant
independent of the output state, therefore, no loading changes will exist on the input lines.
Note 5. Input common mode of either input should not be permitted to go more than 0.3V negative of ground or minus
supply. The upper limit of common mode range is V
- 1.5V but either or both inputs can betaken to as high as
CC
30volts without damage.
Note 6. Response time is specified with a 100mV step and 5.0mV of overdrive. With larger magnitudes of overdrive
faster response times are obtainable.
Note 7. The comparator will inhibit proper output state if one of the inputs is become greater than V
the other input
CC,
must remain within the common mode range. The low input state must not be less than -0.3volts of ground of
minus supply.
TS393 3-6 2003/12 rev. A
Applications Information
This dual comparator feature high gain, wide bandwidth characteristics. This gives the device oscillation tendencies if the outputs are capacitive coupled to the inputs via stray capacitance. This oscillation manifests itself during output transitions (V feedback (<10 mV) is also recommended. It is good design practice to ground all unused pins. Differential input voltages may be larger than supply voltage without damaging the comparator's inputs. Voltages more negative than -0.3V should not be used.
to VOH). To alleviate this situation input resistors<10K should be used. The addition of positive
OL
TS393 4-6 2003/12 rev. A
Electrical Characteris t ic s Curve
TS393 5-6 2003/12 rev. A
SOP-8 Mechanical Drawing
A
SOP-8 DIMENSION
MILLIMETERS INCHES
MIN MAX MIN MAX
o
0
o
7
o
16
DIM
9
PB
1
G
8
M
C
D
K
R
F
A 4.80 5.00 0.189 0.196
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 (typ) 0.05 (typ)
K 0.10 0.25 0.004 0.009
M 0o 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
DIP-8 Mechanical Drawing
A
SOP-8 DIMENSION
8
1
5
B
4
L
C
J
DIM
A 9.07 9.32 0.357 0.367
B 6.22 6.48 0.245 0.255
C 3.18 4.45 0.125 0.135
D 0.35 0.55 0.019 0.020
G 2.54 (typ) 0.10 (typ)
J 0.29 0.31 0.011 0.012
K 3.25 3.35 0.128 0.132
L 7.75 8.00 0.305 0.315
M - 10o - 10o
K
G
D
M
MILLIMETERS INCHES
MIN MAX MIN MAX
TS393 6-6 2003/12 rev. A
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