TriQuint Semiconductor Inc TQ9502MC, TQ9501MC Datasheet
T R I Q U I N T S E M I C O N D U C T O R , I N C .
1
DATACOM
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/9502
531/1063 Mbaud
Fibre Channel
Transmitter and
Receiver
Features
• Compliant with ANSI X3T11
Fibre Channel Standard
• Operates at 531.125 Mbaud
and 1.0625 Gigabaud
(1.25 Gigabaud max)
• Low power dissipation
(2.25 W, typical)
• Low jitter
• No external PLL components
• 10-bit TTL-compatible data bus
• Synchronous Data Bus Interface
•
Direct interface to TQ9303 ENDEC
• Single +5 V supply
• 48-pin MQuad package
TQ9501
Transmitter
2
TQ9303
ENDEC
TQ9502
Receiver
2
Data
10
Data
Data
32
Control
12
HOST
Optical Rx
or Copper
Interface
10
Optical Tx
or Copper
Interface
2
2
Fiber
Optic
Cable
Parity
4
Parity
4
Control
11
Data
32
Control
2
Control
2
2
TriQuint’s Fibre Channel transmitter (TQ9501) and receiver (TQ9502) are
part of the FC531/FC1063 (Fibre Channel 531 and 1063 Megabaud) chip
set. In addition to the transmitter and receiver, TriQuint offers the ENcoder/
DECoder (TQ9303 ENDEC). The TQ9501, TQ9502, TQ9303 and a gigabit
fiber optic module set provide a complete solution for Fibre Channel's FC0
and FC1 layers as well as partial support for the FC2 layer.
The TQ9501 and TQ9502 are designed in TriQuint's proprietary 0.7-micron
GaAs process, enabling the transmitter and receiver to run at higher speeds
and lower power than with conventional processes. The transmitter and
receiver data interface has been selected to be 10 bits in order to conserve
input/output power and to reduce pin count and package size. The transmitter performs the parallel-to-serial conversion and generates the internal
high-speed clock for the serial output. The receiver performs serial-toparallel conversion, recovers the clock and data from the serial input, and
detects the K28.5 character (Fibre Channel standard “SYNC” transmission
character).
The TQ9303 ENDEC implements 8b/10b encoding and decoding, ordered
set encoding and decoding, parity checking and generation, 32-bit CRC
checking and generation, and word synchronization as defined in the
Fibre Channel Physical and Signaling Interface Standard (FC-PH).
Fibre Channel provides a high-speed physical layer for Intelligent
Peripheral Interface (IPI) and Small Computer System Interface (SCSI)
upper-layer command sets, High-Performance Parallel Interface (HIPPI)
data link layer, and other user-defined command sets. Fibre Channel
replaces the SCSI, IPI and HIPPI physical interfaces with a higherspeed interface capable of driving longer distances.
TQ9501/TQ9502
2
For additional information and latest specifications, see our website: www.triquint.com
Fibre Channel is optimized for predictable transfers of
large blocks of data, such as those used in file
transfers between processors (super computer,
mainframe, super-mini, etc.), storage systems (disk
and tape), and output-only devices such as laser
printers and raster scan graphics terminals.
The Fibre Channel protocol is implemented in
hardware, making it simple, efficient and robust. The
lower-level physical interface is decoupled from the
higher-level protocol allowing the Fibre Channel to be
configured with various topologies, including point-topoint, multi-drop bus, ring, and cross point switch.
Fibre Channel supports distances up to 10 Km at baud
rates of 132.8125 Mbaud to 1.0625 Gbaud. Copper
media such as Coax and STP (Shielded Twisted Pair)
are used for shorter distances while fiber optic cables
are used for longer distances.
Applications for the TQ9501 and TQ9502 include serial
SCSI, IPI, HIPPI, point-to-point serial communication,
ATM and other networking applications.
Functional Description – TQ9501 Transmitter
The TQ9501 serializes a 10-bit TTL input into a
differential PECL output. The TQ9501 is composed of
an input register, a parallel-to-serial converter, a PLL
clock generator, a differential output buffer and a PECLto-TTL translator, as illustrated in Figure 1.
The self-contained PLL (Phase-Locked Loop) clock
generator requires no external components. It
generates an internal high-speed bit clock for the serial
output, an internal byte clock for the parallel-to-serial
converter and BYTECLK, based on REFCLK (REFerence
CLocK). BYTECLK is used by the TQ9303 ENDEC to
generate TXCLK.
TXD0..9 are latched into the input register on the rising
edge of TXCLK. The parallel-to-serial converter
serializes the data into a differential PECL buffer. TXD9
is sent first and TXD0 is sent last.
Figure 1. TQ9501 Transmitter
TXD0..9
TLX
LOOPEN
REFCLK
(25–31.25 MH
z
Parallelto-Serial
Converter
Register
TXCLK
BYTECLK
(50–62.5 MH
z
or 100–125 M
H
SIGDET
PLL Clock
Generator
PECL-to-TTL
Converter
10
10
2
TLY
TX
TY
SIG
SIGN
Bit
Clock
Byte
Clock
RATESEL
TriQuint offers two chip sets for Fibre Channel: the
TQ9501 and TQ9502 chip set for 531.125 Mbaud and
1.0625 Gbaud, and the GA9101 and GA9102 chip set
for the 265.625 Mbaud rate.
TQ9501/TQ9502
3
DATACOM
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
Figure 2. TQ9502 – Receiver
Mux
RX, RY
RLX, RLY
LOOPEN
REFCLK
(25–31.25 MHz)
2
2
2
10
10
Clock/Data
Recovery
(500–625 MBaud
or 1.0–1.25 GBaud)
X 40
Data
Clock
Serial-to-
Parallel
Converter
RX Clock
Generate
Register
CLKPOL
SYNC
RXD0..9
SYNCEN
RXCLK
(50–62.5 MH
z
or 100–125 M
H
RATESEL
The LOOPEN (LOOP ENable) pin selects between the
two differential output pairs, TLX and TLY, or TX and
TY. LOOPEN = 1 selects the differential output TLX and
TLY, setting TX = 0 and TY = 1. Conversely, LOOPEN =
0 selects TX and TY, setting TLX = 0 and TLY = 1. This
relationship is shown in Table 1.
Table 1. LOOPEN Configuration
LOOPEN Rx Input Tx Output
0 RX, RY TX,TY
1 RLX, RLY TLX, TLY
The PECL-to-TTL translator block is a differential PECLto-TTL translator. It is normally used for translating
PECL signals generated by optical receivers to TTL
signals to drive control circuitry.
TQ9501/TQ9502
4
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Functional Description – TQ9502 Receiver
The TQ9502 consists of a clock and data recovery
circuit, a multiplexer, and a serial-to-parallel converter
block, as shown in Figure 3. The multiplexer selects
between the RX and RY inputs or the RLX and RLY
inputs. Outputs RTX, RTY, RLTX and RLTY, not shown
on Figure 3, are provided for Fly-By
™
termination,
which allows termination resistors to be placed away
from the chip. The multiplexer output is selected by the
LOOPEN pin as shown in Table 1. The selected data
goes to the CDR (Clock/Data Recovery) block.
The clock and data recovery block has two modes:
clock recovery and frequency acquisition. In the clock
input, it automatically switches to the frequency
acquisition mode which causes the CDR to lock onto
the REFCLK signal. This prevents the PLL from drifting
away from the serial data rate and ensures that the
CDR will properly lock onto the input serial data when it
is reapplied.
The receiver synchronizes 1 ms after applying power,
REFCLK and data. The receiver synchronizes 200 µs
after applying valid data if power and REFCLK has
already been applied. The output of this block is latched
into the output register. When SYNCEN is high
(SYNCronization ENable), the serial-to-parallel
converter monitors the serial data for the K28.5
character. When it sees a K28.5, it realigns the 10-bit
register to the K28.5 character and drives SYNC high.
The clock generate block also detects SYNC going high,
and delays the phase of the output RXCLK to coincide
with the new alignment. Some bits may be lost during
the realignment. When SYNCEN is low, SYNC is driven
low and the serial-to-parallel converter ignores the
K28.5 character.
The output register takes in the 10-bit-wide output
from the Serial-to-Parallel Converter and drives the
RXD0..9 outputs. RXD0..9 are strobed on the rising
edge of RXCLK. CLKPOL = 1 results in a longer setup
time and shorter hold time than CLKPOL = 0. The first
serial bit is placed in RXD9 and the tenth bit is placed
in RXD0.
Fibre Channel Interface
Figure 3 illustrates a typical Fibre Channel physical
layer block diagram using the TQ9501, TQ9502 and
TQ9303 chip set. The interface between the host and
ENDEC operates at 26.5625 MHz with a data width of
32-bits for the transmit path and a separate 32-bits for
the receive path. The ENDEC performs the 8b/10b
encoding and decoding; ordered set encoding and
decoding; parity checking and generation; 32-bit CRC
checking and generation; and word synchronization.
The interface between the TQ9303 and the TQ9501/
TQ9502 operates at 531.25 or 106.250 MHz with an
encoded data width of 10-bits. The serial interface
operates from 531.125 Mbaud or 1.0625 Gbaud
respectively, which is connected to an optical, coaxial
or twisted pair interface.
For additional information on the ENDEC, please refer
to the TQ9303 data sheet.
TQ9501/TQ9502
5
DATACOM
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
Host
TQ9303 ENDEC
TQ9501 TX
TQ9502 RX
Out
In
Termination
Network
RTX
RTY
RLTX
RLTY
2
2
Optical,
Coaxial, or
Twisted Pair
Interface
Optical,
Coaxial, or
Twisted Pair
Interface
RLX, RLY
RX, RY
RXD0..9
RXCLK
SYNC
SYNCEN
CLKPOL
LOOPEN
RATESEL
SIGDET
TXD0..9
TXCLK
BYTECLK
TX, TY
TLX, TLY
SIG, SIGN
CTXD0..31
CTXC0,1
CTXP0..3
CTXRAWA,B
CTXRAW
CTXPENN
CTXPMODE
CTXPERR
CTXCERR
CTXCLK
CTXWREF
RESETN
CRXD0..31
CRXP0..3
CRXS0..5
RAWRX
RXPMODE
WRDSYNCN
RXCKPH0,1
BRXSYNC
BRXCLK
BRXD0..9
LOOPEN
REFCLK
RATESEL
BTXCKIN
BTXCKOUT
BTXD0..9
CRXCLK
REFCLK
Figure 3. System Block Diagram – Fibre Channel
Note that the fast edge rates of the TQ9303 TX bus
outputs can affect the stability of the TQ9501 PLL.
These edge rates can be effectively “slowed” by adding
some series resistance of from 90 to 250 ohms to the
TX data bus lines (TXD0..9) as shown in Figure 4.
Resistance should also be added to TXCLK to maintain
the correct timing relationship with the data lines. The
resistors should be placed near the TQ9303.
In cases where the line capacitance of the bus traces is
less than 3 pF, it may also be necessary to add from
1– 2 pf of capacitance to each trace near the TQ9501.
The purpose is to slow the edge rates enough to
prevent potential undershoot from disturbing the power
supplies in the PLL circuitry of the TQ9501.
Figure 4. Adding resistance and capacitance to
the TX data bus.
. . .
TQ9303
TQ9301
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