TriQuint Semiconductor Inc TQ1090MC500 Datasheet
T R I Q U I N T S E M I C O N D U C T O R , I N C .
1
SYSTEM TIMING
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
TQ1090
11-Output
Configurable
Clock Buffer
Figure 1. Block Diagram
Output Buffers
VCO
Phase
Detector
VDD
Q10
Q9
GND
Q8
Q7
VDD
TEST
VDD
Q0
GND
Q1
Q2
VDD
FBIN S1 REFCLK S0 GND GND GND
GND Q3 Q4 VDD Q5 Q6 GND
1
2
14
13
12
11 10
9
8765
4
3
22212019
18
17
16
15
27
28
252423
26
MUX
Divide Logic
÷ 2
Group A
Group C
Group B
S1 S0
TriQuint’s TQ1090 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 33 MHz to
45MHz, 65 MHz to 90 MHz and 130 MHz to 180 MHz. The outputs are
available at 1x, 2x and 4x, or at
1
/2x, 1x and 2x, or at 1/4 x, 1/2 x and
1x the reference clock frequency, f
REF
.
When one of the Group A outputs (Q0–Q4) is used as feedback to the PLL,
all Group A outputs will be at f
REF
, all Group B outputs (Q5–Q8) will be at
2x f
REF
and all Group C outputs (Q9,Q10) will be at 4x f
REF
. When one of the
Group B outputs is used as feedback to the PLL, all Group A outputs will
be at
1
/2 x f
REF
, all Group B outputs will be at f
REF
and all Group C outputs
will be at 2x f
REF
. When one of the Group C outputs is used as feedback to
the PLL, all Group A outputs will be at
1
/4 x f
REF
, all Group B outputs will be
at
1
/2 x f
REF
and all Group C outputs will be at f
REF
.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation
.
This completely self-contained PLL requires no external capacitors or
resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency
range from 260 MHz to 360 MHz. By feeding back one of the output clocks
to FBIN, the PLL continuously maintains frequency and phase synchronization between the reference clock (REFCLK) and each of the outputs.
Features
• Wide frequency range:
33 MHz to 45 MHz
65 MHz to 90 MHz and
130 MHz to 180 MHz
• Output configurations:
four outputs at f
REF
four outputs at 2x f
REF
two output at 4x f
REF
or
five outputs at
1
/2 x f
REF
three outputs at f
REF
two outputs at 2x f
REF
• Selectable Phase Shift:
–2t, –t, 0, +t (t = 1/f
vco
)
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay
–350 ps
±
500 ps (max) or
–350 ps
±
700 ps (max)
• TTL-compatible I/O with 30 mA
output drive
• Ideal for Power PC
™
designs
• 28-pin J-lead surface-mount
package
2
For additional information and latest specifications, see our website: www.triquint.com
TQ1090
Table 1. Frequency Mode Selection
Output Reference Clock ␣ Output Frequency Range
Test Feedback Mode Frequency Range Group A: Q0–Q4 Group B: Q5,Q08 Group c: Q9,Q10
0 Group A ÷8 35 MHz – 45 MHz 35 MHz – 45 MHz 65 MHz – 90 MHz 130 MHz – 180 MHz
0 Group B ÷4 65 MHz – 90 MHz 35 MHz – 45 MHz 65 MHz – 90 MHz 130 MHz – 180 MHz
0 Group C ÷2 130 MHz – 180 MHz 35 MHz – 45 MHz 65 MHz – 90 MHz 130 MHz – 180 MHz
The phase relationship of the Group A outputs to Group
B and C are controlled by the phase-select pins S0 and
S1. The phase difference can be varied from –2t, –t, 0
or +t, where t = 1/fvco.
TriQuint’s patented output buffer design delivers a very
low output-to-output skew of 150 ps (max). The
TQ1090’s symmetrical TTL outputs are capable of
sourcing and sinking 30 mA.
The Shift Select pins, S0 and S1, control the phase
shift of the Group A outputs (Q0 – Q4), relative to the
other outputs. The user can select from four
incremental phase shifts as shown in Table 2 (Phase
Selection). The phase shift increment (t) is calculated
using the following equation, where
n
is the divide
mode:
t =
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The test mode is outlined
in Table 3.
The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the TQ1090 are TTL-compatible with
30 mA symmetric drive and a minimum V
OH
of 2.4 V.
Power-Up/Reset Synchronization
After power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Functional Description
The core of the TQ1090 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock
(REFCLK) to the feedback clock (FBIN), maintaining a
zero frequency difference between the two. Since one
of the outputs is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps
+500 ps for the
TQ1090-MC500, and within –350 ps
+700 ps for the
TQ1090-MC700.
The internal Voltage-Controlled Oscillator (VCO), has an
operating range of 260 MHz to 360 MHz, as shown in
Table 1. The combination of the VCO and the Divide
Logic enables the TQ1090 to operate between 33 MHz
and 45 MHz, 65 MHz and 90 MHz, and from 130 MHz
to 180 MHz.
1
(f
REF
) (n)
TQ1090
3
SYSTEM TIMING
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
Table 2. Test Mode Selection
Group A Group B Group C
Test Mode Ref. Clock Outputs Q0–Q4 Outputs Q5–Q18 Outputs Q9–Q10
1 ÷2f
REF
f
REF
÷ 8f
REF
÷ 4f
REF
÷ 2
Figure 2. Top Layer Layout of Power Pins
(approx. 3.3x)
Layout Guidelines
Multiple ground and power pins on the TQ1090 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range. We
recommend bypassing each of the V
DD
supply pins to
the nearest ground pin, as close to the chip as possible.
Figure 2 shows the recommended power layout for the
TQ1090. The bypass capacitors should be located on
the same side of the board as the TQ1090. The V
DD
traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple
through-holes connect this small surface plane to an
inner-layer ground plane. The capacitors (C1–C5) are
0.1 mF. TriQuint’s test board uses X7R temperaturestable capacitors in 1206 SMD cases.
C4
C5
C1
C2
C3
Pin 1
Pin 15
Ground
Plane
V
DD
V
DD
V
DD
V
DD
V
DD
S0 S1 Phase Shift (Group A: Q0 – Q4)
00 +t
10 0
01 –t
1 1 –2t
Table 2. Phase Shift Selection
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