TriQuint Semiconductor Inc TQ1089MC700, TQ1089MC500 Datasheet

T R I Q U I N T S E M I C O N D U C T O R , I N C .

1

SYSTEM TIMING

PRODUCTS

For additional information and latest specifications, see our website: www.triquint.com

TQ1089

11-Output
Configurable
Clock Buffer

Figure 1. Block Diagram

Output Buffers

VCO

Phase

Detector

VDD

Q10

Q9

GND

Q8

Q7

VDD

TEST

VDD

Q0

GND

Q1

Q2

VDD

FBIN GND REFCLK GND GND GND GND

GND Q3 Q4 VDD Q5 Q6 GND

1

2

14

13

12

11 10

9

8765

4

3

22212019

18

17

16

15

27

28

252423

26

MUX

Divide Logic

÷ 2

Group A

Group B

TriQuint’s TQ1089 is a configurable clock buffer which generates 11
outputs, operating over a wide range of frequencies from 65 MHz to 90
MHz and from 130 MHz to 180 MHz. The outputs are available at either 1x
and 2x or at 1x and

1

/2 x the reference clock frequency, f

REF

. When one of
the Group A outputs (Q0–Q8) is used as feedback to the PLL, all Group A
outputs will be at f

REF

, and all Group B outputs (Q9, Q10) will be at 2x f

REF

. When one of the Group B outputs is used as feedback to the PLL, all
Group A outputs will be at

1

/2 x f

REF

and all Group B outputs will be at f

REF

.

A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. This completely self-contained PLL requires no external
capacitors or resistors. The PLL’s Voltage-Controlled Oscillator (VCO) has a
frequency range from 260 MHz to 360 MHz. By feeding back one of the
output clocks to FBIN, the PLL continuously maintains frequency and
phase synchronization between the reference clock (REFCLK) and each of
the outputs.

TriQuint’s patented output buffer design delivers a very low output-to­output skew of 150 ps (max). The TQ1089’s symmetrical TTL outputs are
capable of sourcing and sinking 30 mA.

Features

• Wide frequency range:
65 MHz to 90 MHz and
130 MHz to 180 MHz

• Output configurations:
eight outputs at f

REF

two outputs at 2x f

REF

or

nine outputs at

1

/2 x f

REF

one output at f

REF

• Low output-to-output skew:
150 ps (max) within a group

• Near-zero propagation delay
–350 ps

+ 500 ps (max) or

–350 ps

+700 ps (max)

• TTL–compatible with 30 mA
output drive

• 28–pin J–lead surface–mount
package

• Ideal for PowerPC

™

–based

designs

TQ1089

2

For additional information and latest specifications, see our website: www.triquint.com

In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The test mode is outlined
in Table 2.

The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the TQ1089 are TTL-compatible with 30
mA symmetric drive and a minimum V

OH

of 2.4 V.

Power Up/Reset Synchronization

After power up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.

Table 1. Frequency Mode Selection

Functional Description

The core of the TQ1089 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock
(REFCLK) to the feedback clock (FBIN), maintaining a
zero frequency difference between the two. Since one
of the outputs is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps

+500 ps for the

TQ1089–MC500, and within –350 ps

+700 ps for the

TQ1089–MC700.

The internal Voltage-Controlled Oscillator (VCO), has an
operating range of 260 MHz to 360 MHz, as shown in
Table 1. The combination of the VCO and the Divide
Logic enables the TQ1089 to operate between 65 MHz
and 90 MHz and from 130 MHz to 180 MHz.

Table 2. Test Mode Selection

Group A Group B

Test Mode Ref. Clock Outputs Q0–Q8 Outputs Q9, Q10

1 ÷ 2f

REF

f

REF

÷ 4f

REF

÷ 2␣

Output Reference Clock Output Frequency Range

Test Feedback Mode Frequency Range Group A: Q0–Q8 Group B: Q9,Q10

0 Group B ÷ 2 130 MHz – 180 MHz 65 MHz – 90 MHz 130 MHz – 180 MHz
0 Group A ÷ 4 65 MHz – 90 MHz 65 MHz – 90 MHz 130 MHz – 180 MHz

TQ1089

3

SYSTEM TIMING

PRODUCTS

For additional information and latest specifications, see our website: www.triquint.com

Layout Guidelines

Multiple ground and power pins on the TQ1089 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the V

DD

supply
pins to the nearest ground pin, as close to the chip
as possible.

Figure 2 shows the recommended power layout for the
TQ1089. The bypass capacitors should be located on
the same side of the board as the TQ1089. The V

DD

traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple through
holes connect this small surface plane to an inner-layer
ground plane. The capacitors (C1–C5) are 0.1 mF.
TriQuint’s test board uses X7R temperature-stable
capacitors in 1206 SMD cases.

C4

C5

C1

C2

C3

Pin 1

Pin 15

Ground

Plane

V

DD

V

DD

V

DD

V

DD

V

DD

Figure 2. Top Layer Layout of Power Pins

(Approx. 3.3x)