TriQuint Semiconductor Inc GA1087MC700, GA1087MC500 Datasheet
T R I Q U I N T S E M I C O N D U C T O R , I N C .
1
SYSTEM TIMING
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
GA1087
11-Output
Configurable
Clock Buffer
Output Buffers
VCO
Phase
Detector
VDD
Q10
Q9
GND
Q8
Q7
VDD
TEST
VDD
Q0
GND
Q1
Q2
VDD
FBIN GND REFCLK GND F1 F0 GND
GND Q3 Q4 VDD Q5 Q6 GND
1
2
14
13
12
11 10
9
8765
4
3
22212019
18
17
16
15
27
28
252423
26
MUX
Divide Logic
÷4, ÷5, or ÷6
Group B
Group A
TriQuint’s GA1087 is a configurable clock buffer which generates 11 outputs,
operating over a wide range of frequencies — from 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and
1
/2 x the
reference clock frequency, f
REF
. When one of the Group A outputs
(Q5–Q10) is used as feedback to the PLL, all Group A outputs will be at
f
REF
, and all Group B outputs (Q0–Q4) will be at 1/2 x f
REF
. When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
will be at 2x f
REF
and all Group B outputs will be at f
REF
.
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. Completely self-contained, this PLL requires no external
capacitors or resistors. The PLL’s voltage-controlled oscillator (VCO)
has a frequency range from 280 MHz to 420 MHz. By feeding back one
of the output clocks to FBIN, the PLL continuously maintains frequency
and phase synchronization between the reference clock (REFCLK) and
each of the outputs.
TriQuint’s patented output buffer design delivers a very low output-tooutput skew of 150 ps (max). The GA1087’s symmetrical TTL outputs
are capable of sourcing and sinking 30 mA.
Features
• Wide frequency range:
24 MHz to 105 MHz
• Output configurations:
five outputs at f
REF
five outputs at f
REF
/2 or
six outputs at 2x f
REF
four outputs at f
REF
• Low output-to-output skew:
150 ps (max) within a group
• Near-zero propagation delay:
–350 ps
+500 ps (max) or
–350 ps
+700 ps (max)
• TTL-compatible with 30 mA
output drive
• 28-pin J-lead
surface-mount package
GA1087
2
For additional information and latest specifications, see our website: www.triquint.com
Functional Description
The core of the GA1087 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock (REFCLK)
to the feedback clock (FBIN), maintaining a zero frequency
difference between the two. Since one of the outputs
(Q0–Q8) is always connected to FBIN, t
he PLL keeps
the propagation delay between the outputs
and the
reference clock within –350 ps
+500 ps for the
GA1087-MC500, and within –350 ps
+700 ps for the
GA1087-MC700.
The internal voltage-controlled oscillator (VCO) has an
operating range of 280 MHz to 420 MHz. The combination of the VCO and the Divide Logic enables the
GA1087 to operate between 24 MHz and 105 MHz.
The device features six divide modes: ÷4, ÷5, ÷6, ÷8,
÷10, and ÷12. The Frequency Select pins, F0 and F1,
and the output used as feedback to FBIN set the divide
mode as shown in Table 1.
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The various test modes are
outlined in Table 2. In the test mode, the frequency of
the reference clock is divided by 4, 5, or 6.
The maximum rise and fall time at the output pins is
1.4 ns. All outputs of the GA1087 are TTL-compatible
with 30 mA symmetric drive and a minimum VOH of 2.4 V.
Power Up/Reset Synchronization
After-power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Feedback: Any Group B Output (Q0 – Q4)
Select Pins Reference Clock Output Frequency Range
Test F0 F1 Mode Frequency Range Group A: Q5–Q10 Group B: Q0–Q4
010 ÷ 4 70 MHz – 105 MHz 70 MHz – 105 MHz 35 MHz – 52 MHz
000 ÷ 5 56 MHz – 84 MHz 56 MHz – 84 MHz
1
28 MHz – 42 MHz
001 ÷ 6 48 MHz – 70 MHz 48 MHz – 70 MHz 24 MHz – 35 MHz
0 1 1 Not Used N.A. N.A. N.A.
Select Pins Reference Clock Output Frequency Range
Test F0 F1 Mode Frequency Range Group A: Q5–Q10 Group B: Q0–Q4
010 ÷ 8 35 MHz – 52 MHz 70 MHz – 105 MHz 35 MHz – 52 MHz
000 ÷ 10 28 MHz – 42 MHz 56 MHz – 84 MHz
1
28 MHz – 42 MHz
001 ÷ 12 24 MHz – 35 MHz 48 MHz – 70 MHz 24 MHz – 35 MHz
0 1 1 Not Used N.A. N.A. N.A.
Notes: 1. This mode produces outputs with 40/60 duty cycle for Q5 – Q10 only.
Table 1. Frequency Mode Selection
Feedback: Any Group A Output (Q5 – Q10)
GA1087
3
SYSTEM TIMING
PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
Table 2. Test Mode Selection
Group B: Group A:
Test F0 F1 Mode Ref. Clock Outputs Q0–Q4 Outputs Q5–Q10
11 0 ÷ 4f
REF
f
REF
÷ 8f
REF
÷ 4␣ ␣
10 0 ÷ 5f
REF
f
REF
÷ 10 f
REF
÷ 5
10 1 ÷ 6f
REF
f
REF
÷ 12 f
REF
÷ 6
11 1 — — — —
Figure 2. Top Layer Layout of Power Pins
(approx. 3.3x)
C4
C5
C1
C2
C3
Pin 1
Pin 15
Ground
Plane
V
DD
V
DD
V
DD
V
DD
V
DD
Layout Guidelines
Multiple ground and power pins on the GA1087 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the V
DD
supply
pins to the nearest ground pin, as close to the chip as
possible.
Figure 2 shows the recommended power layout for the
GA1087. The bypass capacitors should be located on
the same side of the board as the GA1087. The V
DD
traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple through
holes connect this small surface plane to an inner-layer
ground plane. The capacitors (C1–C5) are 0.1 mF.
TriQuint’s test board uses X7R temperature-stable
capacitors in 1206 SMD cases.
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