TriQuint Semiconductor Inc GA1085MC1000 Datasheet

T R I Q U I N T S E M I C O N D U C T O R , I N C .

SYSTEMS TIMING

SYSTEM TIMING

PRODUCTS

1

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GA1085

11-Output
Configurable
Clock Buffer

Features

• Wide frequency range:
24 MHz to 105 MHz

• Output configurations:
Four outputs at f

REF

Four outputs at f

REF

/2

Two outputs at f

REF

/2
␣␣␣␣with adjustable phase
␣␣␣␣␣␣␣␣␣␣␣or
Five outputs at 2x f

REF

Three outputs at f

REF

Two outputs at f

REF

␣␣␣␣with adjustable phase

• Selectable Phase Shift: –2t, –t,
+t, and +2t (t = 1/f

VCO

)

• Low output-to-output skew: 150
ps (max) within a group

• Near-zero propagation delay:
–350 ps

+1000 ps (max)

• TTL-compatible with 30 mA
output drive

• 28-pin J-lead surface-mount
package

Figure 1. Block Diagram

Output Buffers

VCO

Phase

Detector

VDD

Q10

Q9

GND

Q8

Q7

VDD

TEST

VDD

Q0

GND

Q1

Q2

VDD

FBIN S1 REFCLK S0 F1 F0 GND

GND Q3 Q4 VDD Q5 Q6 GND

1

2

14

13

12

11 10

9

8765

4

3

22212019

18

17

16

15

27

28

252423

26

Phase
Select

MUX

Divide Logic
÷4, ÷5, or ÷6

Group

B

Group A

Group

C

TriQuint’s GA1085 is a configurable clock buffer which generates 11 outputs
and operates over a wide range of frequencies—from 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and

1

/2 x the reference

clock frequency, f

REF

. When one of the Group A outputs (Q4–Q8) is used as

feedback to the PLL, all Group A outputs will be at f

REF

, and all Group B

(Q0–Q3) and Group C (Q9, Q10) outputs will be at

1

/2 x f

REF

. When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
will be at 2x

REF

and all Group B and Group C outputs will be at f

REF

. The
Shift Select pins select the phase shift (–2t, –t, +t or +2t) for Group C
outputs (Q9, Q10) with respect to REFCLK. The phase shift increment (t)
is equivalent to the VCO’s period (1/f

VCO

).

A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or resistors.
The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency range from
280 MHz to 420 MHz. By feeding back one of the output clocks to FBIN,
the PLL continuously maintains frequency and phase synchron-ization
between the reference clock (REFCLK) and each of the outputs.

TriQuint’s patented output buffer design delivers a very low output-to-output
skew of 150 ps (max). The GA1085’s symmetrical TTL outputs are capable
of sourcing and sinking 30 mA.

GA1085

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2

Functional Description

The core of the GA1085 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock (REFCLK)
to the feedback clock (FBIN), maintaining a zero
frequency difference between the two. Since one of the
outputs (Q0–Q8) is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps

+1000 ps.

The internal Voltage-Controlled Oscillator (VCO) has an
operating range of 280 MHz to 420 MHz. The
combination of the VCO and the Divide Logic enables
the GA1085 to operate between 24 MHz and 105 MHz.
The device features six divide modes: ÷4, ÷5, ÷6, ÷8,
÷10, and ÷12. The Frequency Select pins, F0 and F1,
and the output used as feedback to FBIN set the divide
mode as shown in Table 1.

The Shift Select pins, S0 and S1, control the phase
shift of Q9 and Q10 relative to the other outputs. The
user can select from four incremental phase shifts as
shown in Table 2.

The phase-shift increment (t) is calculated using the
following equation:

where

n

is the divide mode.

In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The various test modes are
outlined in Table 3. In the test mode, the frequency of
the reference clock is divided by 4, 5, or 6.

The maximum rise and fall time at the output pins is

1.4 ns. All outputs of the GA1085 are TTL-compatible
with 30 mA symmetric drive and a minimum VOH of 2.4 V.

Power-Up/Reset Synchronization

After power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.

Table 1. Frequency Mode Selection

Feedback: Any Group B Output (Q0 – Q3)

Select Pins Reference Clock Output Frequency Range

Test F0 F1 Mode Frequency Range Group A: Q4–Q8 B: Q0–Q3, C: Q9–Q10

01 0 ÷ 4 70 MHz – 105 MHz 70 MHz – 105 MHz 35 MHz – 52 MHz
00 0 ÷ 5 56 MHz – 84 MHz 56 MHz – 84 MHz

1

28 MHz – 42 MHz

00 1 ÷ 6 48 MHz – 70 MHz 48 MHz – 70 MHz 24 MHz – 35 MHz
0 1 1 Not Used N.A. N.A. N.A.

Feedback: Any Group A Output (Q4 – Q8)

Select Pins Reference Clock Output Frequency Range

Test F0 F1 Mode Frequency Range Group A: Q4–Q8 B: Q0–Q3, C: Q9–Q10

01 0 ÷ 8 35 MHz – 52 MHz 70 MHz – 105 MHz 35 MHz – 52 MHz
00 0 ÷ 10 28 MHz – 42 MHz 56 MHz – 84 MHz

1

28 MHz – 42 MHz

00 1 ÷ 12 24 MHz – 35 MHz 48 MHz – 70 MHz 24 MHz – 35 MHz
0 1 1 Not Used N.A. N.A. N.A.

t =

1

(f ) (n)

REF

Note: 1. This mode produces outputs with 40/60 duty cycle for Q4 – Q8 only.

GA1085

SYSTEM TIMING

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3

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S0 S1 Phase Difference (Q9, Q10)

0 0 +2t

01 +t

10 –t

1 1 –2t

Table 2. Phase Shift Selection

Table 3. Test Mode Selection

Group A: Groups B, C:

Test F0 F1 Mode Ref. Clock Outputs Q4–Q8 Q0–Q3, Q9, Q10

11 0 ÷ 4f

REF

f

REF

÷ 4f

REF

÷ 8␣ ␣

10 0 ÷ 5f

REF

f

REF

÷ 5f

REF

÷ 10

10 1 ÷ 6f

REF

f

REF

÷ 6f

REF

÷ 12

11 1 — — — —

Layout Guidelines

Multiple ground and power pins on the GA1085 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the V

DD

supply
pins to the nearest ground pin, as close to the chip as
possible.

Figure 2 shows the recommended power layout for the
GA1085. The bypass capacitors should be located on
the same side of the board as the GA1085. The V

DD

traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple
through-holes connect this small surface plane to an
inner-layer ground plane. The capacitors (C1–C5) are

0.1 µF. TriQuint’s test board uses X7R temperature­stable capacitors in 1206 SMD cases.

Figure 2. Top Layer Layout of Power Pins

(magnified approximately 3.3x)

C4

C5

C1

C2

C3

Pin 1

Pin 15

Ground

Plane

V

DD

V

DD

V

DD

V

DD

V

DD