TRIPATH TECHNOLOGY TA2021-100 Datasheet

TECHNICAL INFORMATION

Stereo 100W (4
using DPP

CONFIDENTIAL INFORMATION – July 1999

TM

Technology (Tornado) TA2021-100

) Class-T Digital Audio Amplifier Driver

ΩΩΩΩ

General Description

The TA2021-100 Tornado is a 100W (4Ω), two channel Amplifier Driver IC which uses
Tripath’s proprietary Digital Power Processing
both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.

Applications

! Computer/PC Multimedia
! Video CD Players
! Cable Set Top Products
! DVD Players/Receivers
! Battery Powered Sound

Reinforcement

Benefits

! Fully Integrated Solution with

FET’s for low system cost

! Improved efficiency versus Class-AB
! Signal fidelity equal to high

quality Class-AB amplifiers

! High dynamic range compatible

with digital media such as CD,
DVD and Internet audio

! Smaller power supply due to

efficient operation

! Integrated volume control reduces

system cost and noise

! Optional control/status through

industry-standard digital serial bus
simplifies system design

TM

technology. Class-T amplifiers offer

Features

! Class-T architecture
! Integrated FET’s
! Proprietary Digital Power Processing
! “Audiophile” Sound Quality

! 0.1 % THD+N @ 100Wrms, 4
! 0.08% IHF-IM

! High Power

! 90Wrms @ 8

! High Efficiency

! 90% @90Wrms @ 8
! 85% @100Wrms @ 4

! Two modes of control/status operation:

! 1. Through analog pins

! 2. Through I
! Low Noise Floor (<150uV)
! Integrated volume control with 124dB range

controlled via I

! Programmable “Mute on Silence” feature for auto

power down

! Bridgeable, single-ended outputs
! Mute and Sleep inputs
! Headphone/Line outputs
! Turn-on & turn-off pop suppression
! Over-current & temperature protection
! Over and under-voltage protection
! Supports 100kHz BW Super Audio CD and DVD-

Audio (See App Note for specifics)

! 32-pin SSIP (Staggered Single In Line Package)

, 10% THD+N

Ω

Ω

Ω

2

C digital serial bus

2

C bus or DC input

Ω

1

TECHNICAL INFORMATION

Absolute Maximum Ratings

SYMBOL PARAMETER Value UNITS

Vs Supply Voltage (Vspos & V sneg) +/-50 V
V5 Positive 5 V Bias Supply 6 V
VGG Internally generated voltage 12 V
T

STORE

T

A

Notes: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Operating Conditions

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

Vs Supply Voltage (Vspos & V sneg) +/- 25 +/- 35 +/- 45 V
V5 Positive 5 V Bias Supply 4.5 5 5.5 V
VGG Internally Generated Voltage 10 11 12 V

Storage Temperature Range -40 to 150 ºC
Operating Free-air Temperature Range -20 to +80 ºC

Damage will occur to the device if VN10 is not supplied or falls below the recommended
operating voltage when V

is within its recommended operating range.

S

Note: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.

Electrical Characteristics

TA = 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

I

q

Quiescent Current +35V
(no load) -35V

+5V

VN12

I

S

I5
IVGG

Source Current @ P

= 100W, RL = 4ΩV

OUT

@ 10% THD+N V
Source Current for 5V Bias Supply @ P

Source Current for VGG Supply @ P

OUT

= 100W, RL = 4

OUT

= +35V

SPOS

= -35V

SNEG

= 100W, RL = 4

Ω

Ω

Vu Under Voltage (Vspos & Vsneg) 25 V
Vo Over Voltage (Vspos & Vsneg) 45 V
V

IH

V

IL

High-level Input Voltage (MUTE & SLEEP) 3.5 V
Low-level Input Voltage (MUTE & SLEEP) 1 V

IDDMUTE Mute Supply Current +35V

(no load) -35V
+5V

VGG

V

OH

High-level Output Voltage (HMUTE/SDA, OVERLO AD /SCL &

3.5 V

PSMUTE)

V

OL

Low-level Output Voltage (HMUTE/SDA, OVERLOAD/S CL &
PSMUTE)

V

TOC

A

V

Over Current Sense Voltage Threshold 1.2 V
Gain Ratio V

OUT/VIN

, RIN = 0

Ω

Voffset Offset Voltage, no load, MUTE = Logic low mV

mA
mA
mA
mA

A
A

mA
mA

mA
mA
mA
mA

1V

V/V

2

TECHNICAL INFORMATION

Minimum and maximum limits are guaranteed but may not be 100% tested.

Performance Characteristics – Single Ended

Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS

P

OUT

THD + N Total Harm oni c Distortion Plus
IHF-IM IHF Intermodulation Distortion
SNR Signal-to-Noise Ratio
CS Channel Separation

PSRR Power Supply Rejection Ratio Input Referenced, 30kHz Bandwidth 65 dB

η

e

NOUT

Output Power
(continuous RMS/Channel)

Noise

Power Efficiency

THD+N = 0.1%, R
THD+N = 10%, R

= 4W/Channel, RL = 4

P

OUT

19kHz, 20kHz, 1:1 (IHF), R
P

= 1W/Channel

OUT

A Weighted, R

= 100W/Channel

P

OUT

0dBr = __W, R

= 90W/Channel, RL = 8

P

OUT

= 8

Ω

L

= 4

R

Ω

L

= 8

Ω

L

= 4

R

Ω

L

= 4Ω,

L

= 4Ω, f = 1kHz

L

Ω

L

= 4

Ω

Ω

Output Noise Voltage A Weighted, no signal, input shorted,

DC offset nulled to zero

100

90

125

.02 %

0.08 %
110 dB

80 dB

90 %

150

W
W
W
W

V

µ

Minimum and maximum limits are guaranteed but may not be 100% tested.

Notes:

1) VP1=VP2=+35V, VN1=VN2=-35V, V5 = +5V, VGG = +11V referenced to PGND

3

TECHNICAL INFORMATION

Serial Bus Timing

Unless otherwise specified, _____________

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS

t

CL

SCL (Clock) Period

s

µ

t

SETUP

t

STABLE

t

START

t

STOP

Data In Set-up Time to SCL Low
Data Out Stable after SCL Low
SDA Low Set-up Time to SCL Low (Start Conditi on)
SDA High Hold Time after SCL Hi gh (Stop Condition)

OVERLOAD/SCL

HMUTE/SDA

(Data In)

HMUTE/SDA

(Data Out)

t

START

t

SETUP

s

µ

s

µ

s

µ

s

µ

t

CL

t

STOP

t

STABLE

4

TECHNICAL INFORMATION

Pin Description

Pin Function Description

1,13 VB2,VB1 Bootstrapped voltages supply drive to gates of high-side FET’s

2 VGG Regulated output of onboard switching regulator
3 PGND Power ground

4,12 VP2,VP1 Positive power supply connections

5 SW12V Switching node
6,11 VS2,VS1 Source voltage for high side FET’s
7,10 OUT2,OUT1 Power FET outputs

8,9 VN2,VN1 Negative power supply connections

14 SWFB Feedback for onboard regulator
15 SLEEP When set to logic high, both amplifiers are muted and in low power (idle)

16 PSMUTE A logic high output indicates the amplifiers are muted
17 OVRLD/SCL Dual function pin:

18 HMUTE/SDA Dual function pin:

19 MUTE When set to logic high, both amplifiers are muted. When set to logic low or

20 MIS/ADDR Dual function pin:

21 V5 5V power supply

22 AGND Analog Ground
23,24 INP1,INP2 Inputs for channels 1 and 2
25,26 AUXOUT1,AUXOUT2 Auxiliary outputs that provide a low impedance, buffered audio output

27 V2BG Bandgap reference

28 DCVOL When control/status of the device is via analog pins, the voltage level on this

29,31 FDBKN1,FDBKN2 Feedback for channels 1 and 2
30,32 GNDKELVIN1

GNDKELVIN2

mode. When low (grounded), both amplifiers are fully operational. If left
floating, the device stays in the mute mode. Ground if not used.

OVRLD – A logic high output indicates that the level of the input signal has
overloaded the amplifiers, signifying increased distortion
SCL – When tied to V5 through a pull-up resistor, this pin becomes the serial
clock line of the serial control bus

HMUTE – A logic high output indicates that the output stages of both
amplifiers are shut off and muted.
SDA – When OVRLD/SCL is tied to V5 through a pull up resistor, this pin
becomes the serial data line of the serial control bus

grounded both amplifiers are fully operational. Ground if not used.

MIS – When control/status of the device is via analog pins, the voltage level
ion this pint sets the Mute-in –silence threshold
ADDR – When OVRLD/SCL is tied to V5 through a pull up resistor, the voltage
on this pin selects the chip address of the device for the serial control bus

where the signal level is set by the volume control

pin sets the output signal volume

Kelvin connection to speaker ground channels 1 and 2

5

TECHNICAL INFORMATION

32-pin SSIP Package

(Top View)

1

VB2

2

VGG

3

PGND

4

VP2

5

SW12

6

VS2

7

OUT2

8

VN2

9

VN1

10

OUT1

11

VS1

12

VP1

13

VB1

14

SWFB

MUTE

INP1
INP2

V2BG

15
16
17
18
19
20

V5

21

GA

22
23
24
25
26
27
28
29
30
31
32

SLEEP

PSMUTE

OVRLD/SCL

HMUTE/SDA

MIS/ADDR

AUXOUT1

AUXOUT2

DCVOL

FDBKN1

GNDKELVIN1

FDBKN2

GNDKELVIN2

6

TECHNICAL INFORMATION

Test/Application Circuit

TA2021-100

25
26

C

IN

INP1

23

R

IN

29
12

11

V5

15

SLEEP

10

13

19

OVRLD/SCL

HMUTE/SDA

C

IN

PSMUTE

R

IN

MUTE

INP2

16

17

18

24

30

31

32

FDBKN1

VP1

VS1

VN1

9

OUT1

VB1

GNDKELVIN1

FDBKN2

VP2

4

6

VS2

8

VN2

OUT2

7

VB2

1

GNDKELVIN2

AUXOUT1
AUXOUT2

Positive Supply Star

L

F

C

F

R

G

Negative Supply Star
Positive Supply Star

L

F

C

F

R

G

R

D

R

L

C

D

R

D

R

L

C

D

+5V

V5

21

MIS/ADDR 19

27

V2BG

28

DCVOL

24

AGND

Note - Heavy Lines Indicate High-Current Paths

SW-FB14

SW12

5

VGG

2

3PGND

VB1 VB2

Negative Supply Star

VN

Power Supply Ground Star

7