Trinamic TMC8462-EVAL User Manual

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Evaluation Board for TRINAMIC’s EtherCAT Slave Controller

EVALUATION BOARD

TMC8462-EVAL

Document Revision V1.00 • 2018-May -28

The TMC8462-EVAL is designed for evaluating all features of the TMC8462-BA EtherCAT Slave Controller. It can be used as bus interface module for EtherCAT applications.

Features

•

TMC8462-BA EtherCAT Slave Controller

• Board supply voltage: 5V to 35V

• Dual RJ45 TPC connector

• SPI PDI interface

•

SPI interface for TRINAMIC’s MultiFunction and Control IO Block (MFC IO)

•

Access to all chip functions via pin headers and connectors

•

Interface to TRINAMIC’s evaluation board concept

•

CAD design ﬁles available for download on www.trinamic.com

Applications

• Laboratory Automation

• Drives

• Semiconductor Handling

• Robotics

• Factory Automation

• Connected Sensors

Simpliﬁed Block Diagram

Read entire documentation.

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Contents

1 Getting Started 3

1.1 First Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Evaluation Board Sections and Components 5

2.1 Evaluation Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Evaluation Board Pin Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Evaluation Board Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Evaluation Board Design Files 10

4 Example XML File 10

5 Revision History 13

5.1 Document Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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1 Getting Started

You need

• TMC8462-EVAL

• TRINAMIC’s Landungsbruecke or Startrampe

•

Firmware for Landungsbruecke or Startrampe with simple implementation of the ESM (EtherCAT State Machine)

• Eselsbruecke connector board

•

Power Supply 5V-35V for the evaluation board itself

• Latest TMCL-IDE

• RJ45 TPC cable

•

EtherCAT master system (Beckhoﬀ TwinCAT, SOEM, Omron, Ancosys...)

• Additional cables you need for your setup

Precautions

•

Do not mix up connections or short-circuit pins.

•

Do not exceed the maximum rated supply supply voltage!

• START WITH POWER SUPPLY OFF!

Foto eines kompletten Kits! Landungsbruecke+Eval+Kabel

Figure 1: TMC8462-EVAL kit

NOTICE

The Landungsbruecke operates on USB Power Supply. All other voltages are generated from the evaluation board supply 5V-35V. The kit works only when both supplies are connected.

1.1 First Start-Up

Make sure that the latest version of the TMCL-IDE is installed. The TMCL-IDE can be downloaded from www.trinamic.com/support/software/tmcl-ide/.

2. Open the TMCL-IDE and connect the Landungsbruecke or Startrampe via USB to the computer. For Windows 8 and higher is no driver needed, on Windows 7 machines the TMCL-IDE is installing the driver automatically.

Verify that the Landungsbruecke or Startrampe is using the latest ﬁrmware version. The ﬁrmware version is shown in the connected device tree. The latest ﬁrmware is always available online at

https://www.trinamic.com/support/eval-kits/details/landungsbruecke/ or https://www.trinamic.com/support/eval-kits/details/startrampe/

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Figure 2: Firmware Version

The TMCL-IDE needs room to show all important information and to provide a good overview. Therefore, arrange the main window related to your needs. We recommend using full screen.

Figure 3: Landungsbruecke Dialogue

The TMCL-IDE includes a dialogue for diagnostic tasks for the controller board. Further, the dialogue provides an overview of the connected evaluation board (controller and/or driver). The TMC8462-EVAL should appear under "controller" by automatic detection. In case it does not appear, the evaluation board can also be selected manually. A window should pop up immediately after connecting the evaluation kit the ﬁrst time. The window shows the general status of the connected evaluation board. The second tab of the dialogue oﬀers the possibility to choose basic settings or to reset the module.

If not yet done also connect your Ethernet TPC cables into the RJ45 bus connections of the TMC8462EVALto connect to other EtherCAT slaves and your EtherCAT master system.

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Figure 4: Top view of TMC8462-EVAL

2 Evaluation Board Sections and Components

Figure 4 top view of the TMC8462-EVAL shows the main connectors (green), signal pin headers (light blue), and jumper options (red). The on-chip reset circuit takes care for proper power-on reset. The tactile switch S1 in the upper right corner triggers a manual reset of the ESC and the PHYs.

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2.1 Evaluation Board Connectors

Connector ID Description

Power supply connector for the evaluation board. Connect Ground and Supply here (5V-35V). Type: AKL320-02 by RIA

Left side 44-pin connector with control signals going to TRINAMIC’s Landungsbruecke or Startrampe controller board or a users own controller board. The Eselsbruecke connector board ﬁts onto this connector. Type:

HLE-122-02-F-DV by Samtec

Right side 44-pin connector with conﬁgurable MFC IO singnals of TMC8462BA. Type: HLE-122-02-F-DV by Samtec

Double RJ45 twisted pair copper (TPC) connector to connect the TMC8462EVAL to the EtherCAT bus. 10/100BaseT with integrated transformers. Type:

7499021125 by Wuerth Elektronik

Table 1: Board connectors

Please check the online available design ﬁles and schematic data for the connectors’ signal connections and pinning.

2.2 Evaluation Board Pin Headers

There are 5 pin header groups on the TMC8462-EVAL– J4 to J8.

Pin Header ID Description

J4 General control signals

J5 MFC IO 16x low-voltage/digital IOs

J6 MFC IO 3x high-voltage IOs, pin group 1 using VIO1

J7 MFC IO 3x high-voltage IOs, pin group 2 using VIO2

J7 MFC IO 2x high-voltage IOs, pin group 3 using VIO3

Table 2: Pin header groups

J4 contains various control and debug signals. The distributed clocks synchronization output trigger signals and input latch signals are available along with some PDI debug signals. Using a 2-pin jumper bridge across pin 5 and pin 6 (RESET_OUT to RST_IN) enables using the internal reset signal of the ESC. Thereby, the EtherCAT master or the local host can issue a TMC8462-BA device reset by writing a special character sequence into ESC registers 0x0040 or 0x0041.

Pin # Description Pin # Description

1 SYNC_OUT0 2 LATCH_IN0

3 SYNC_OUT1 4 LATCH_IN1

5 RESET_OUT 6 RST_IN

7 +3.3V (= TMC8462-BA SW0 output) 8 MFC_NES_EXT

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Pin # Description Pin # Description

9 PDI_SOF 10 GND

11 PDI_EOF 12 +3.3V (= TMC8462-BA SW0 output)

13 CLK_16MHZ_OUT 14 +5V (from LDO U1)

15 GND 16 GND

Table 3: Pin header J4 pinning – general control signals

J5 allows access to all 16 low-voltage MFC IOs. They are using VCCIO = +3.3V. The actual function of these 16 MFC IOs is deﬁned by the conﬁguration of the MFC IO block’s crossbar matrix and functional sub-blocks.

Pin # Description Pin # Description

1 GND 2 +3.3V (= TMC8462-BA SW0 output)

3 MFCIO08 4 MFCIO00

5 MFCIO09 6 MFCIO01

7 MFCIO10 8 MFCIO02

9 MFCIO11 10 MFCIO03

11 MFCIO12 12 MFCIO04

13 MFCIO13 14 MFCIO05

15 MFCIO14 16 MFCIO06

17 MFCIO15 18 MFCIO07

19 GND 20 +3.3V (= TMC8462-BA SW0 output)

Table 4: Pin header J5 pinning – MFC IO 16x low-voltage/digital IOs

J6, J7, and J8 allow access to all 8 high-voltage MFC IOs. The voltage at these pins is conﬁgurable and can be up to the supply voltage. The 8 high-voltage MFC IOs are divided into three groups where each group has its own supply voltage. On the TMC8462-EVAL VIO1 and VIO2 are the same and directly driven by VOUT . VIO2 can be selected using The actual function of these 8 MFC IOs is deﬁned by the conﬁguration of the MFC IO block’s crossbar matrix and functional sub-blocks.

Pin # Description

1 VOUT (= TMC8462-BA SW1 output, conﬁgurable)

2 MFCHVIO00

3 MFCHVIO01

4 MFCHVIO02

5 GND

Table 5: Pin header J6 pinning – MFC IO 3x high-voltage IOs, pin group 1 using VIO1

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Pin # Description

1 VIO2 (= selectable and conﬁgurable)

2 MFCHVIO03

3 MFCHVIO04

4 MFCHVIO05

5 GND

Table 6: Pin header J7 pinning – MFC IO 3x high-voltage IOs, pin group 2 using VIO2

Pin # Description

1 VOUT (= TMC8462-BA SW1 output, conﬁgurable)

2 MFCHVIO06

3 MFCHVIO07

4 GND

Table 7: Pin header J8 pinning – MFC IO 2x high-voltage IOs, pin group 3 using VIO3

2.3 Evaluation Board Jumper Settings

Jumper ID Default Connection Pins Description

JP1 2-3

JP1 selects the voltage used for bank 2 of the high voltage IOs VIO2. The default setting selects VOUT of the conﬁgurable buck regulator of TMC8462-BA. The VOUT itself can further be selected with JP2. The second option of JP1 is to used a dedicated ﬁxed 5V voltage regulator output.

JP2 1-2

JP2 selects the conﬁguration for the output voltage of the conﬁgurable internal buck regulator of TMC8462-BA. The default setting ("ﬁxed") uses a voltage divider conﬁguration for VOUT = 5V. The second option ("VAR") allows directly controlling VOUT with the potentiometer R23.

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Jumper ID Default Connection Pins Description

JP3 1-2

JP3 selects the conﬁguration of the two SPI control interfaces of TMC8462-BA (PDI SPI interface and MFC IO SPI interface). The default setting conﬁgures the interfaces to be two separate SPI buses with individual control and data signals. The second option is to physically share the PDI SPI bus and also allow access to the MFC IO SPI via the second chip select line.

JP4 1-2

JP4 selects the EtherCAT operation mode of TMC8462-BA. With the default setting, the EtherCAT slave controller operates in standard mode. TMC8462-BA thereby expects a controller including an EtherCAT State Machine (ESM) implementation at the PDI interface. The second option is to start-up the ESC in so-called PDI- or device-emulation mode, which allows operation without an external controller. State changes are then directly executed in hardware in the ESC.

JP5 2-3

JP5 selects the actual source of the low active (not) emergency switch input MFC_NES. MFC_NES has a weak internal pull down and must be driven high for normal operation. The default setting of JP5 conﬁgures the source of MFC_NES coming from pin header J4 at pin 8. The second option is that MFC_NES is driven by pin 23 of the 44-pin connector J2, for example by a connected TRINAMIC Landungsbruecke controller board.

Table 8: Board jumper options and defaults

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3 Evaluation Board Design Files

All design ﬁles for our evaluation boards are available for free. We oﬀer the original ECAD ﬁles, Gerber data, the BOM, and PDF copies of schematic and layout.

The ﬁles are available on the evaluation board website at

https://www.trinamic.com/support/eval-kits/

Note

If ﬁles are missing on the website or something is wrong please send us a note.

4 Example XML File

The following example XML ﬁle is used as default conﬁguration for the TMC8462-EVAL. This XML ﬁle is available for download from the evaluation board’s webpage. Besides the standard ESI/XML conﬁguration it includes the following blocks:

•

The MFC IO conﬁguration vector, which is deﬁned as category 1 data to be automatically loaded in the ESC Parameter RAM at 0x0580-0x05E1. It is all zero in this conﬁguration.

• DC mode conﬁguration example

• ESC conﬁguration <ConﬁgData> with general/start-up PDI and interface conﬁguration

1 <?xml v er sio n ="1. 0"? >

< Eth erC ATI nfo x mln s:x si=" h ttp : //www.w 3.or g /20 01/ X MLSch ema - ins tan ce"

3 x si: noN a mes pac e Sch ema L oca tio n = " Eth erC ATI nfo . x sd " Ver sio n ="1.6">

< V e ndo r >

5 < Id># x28 6 </I d >

< Na me>Tr ina mi c M ot ion C ont rol Gmb H & amp ; C o . KG</ Nam e >

7 < I mag eDa ta1 6 x1 4 > 424 dd 6 020 000 0 000 0000 360 0 000 028 0 000 001 0 000 000 0 e00 0 000 0

100 180 0 0 0 0 000 00 a00 2 000 013 0 b00 001 3 0b0 000 0 000 000 0 000 000

9 ...

b3b 3 b3b 3b3 b 3b3 b3 b 3 b3b 3 b3b 3b3 b 3b3 b3b 3 aca cac 1 c1c 1c

11 < / Ima geD a ta 1 6x1 4 >

</Ve nd or >

13 < Des cri pti ons >

< G r oup s >

15 < G ro up>

< Ty pe>Tr ina mic EVA L < /Ty pe>

17 < Na me LcI d ="1033 " > EVAL B oar ds </ N am e >

< Na me LcI d ="1031 " > EVAL B oar ds </ N am e >

19 </Gr ou p >

</Gr ou ps >

21 < Dev ic es >

< D e vic e Phy sic s =" Y Y ">

23 < Ty pe P rod uct Cod e ="# x 2 64 830 54" R evi sio nNo = "#x0 001 012 8 " >

TMC84 62 - EVA L D efa ult < / Type >

25 < Na me LcI d ="1033 " > T M C8462 - EVAL D efa ult < / Name>

< Na me LcI d ="1031 " > T M C8462 - EVAL D efa ult < / Name>

27 < In fo>

< Sta teM ach ine >

29 < Tim eo ut >

< Pre opT ime out >2000 < / Pre opT ime o ut>

31 < Saf eop OpT i m e o ut>9000 < / Saf e opO pTi meo ut >

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< Bac kTo Ini t Tim eou t > 5000 </ Ba c kTo Ini tTi meo u t >

33 < Bac kTo S afe opT ime out >200</ B a ckT oSa feo p Tim eou t >

</Ti meo ut >

35 < / Sta teM ach ine >

< Mai lb ox >

37 < Tim eo ut >

< Req ues tTi meo u t >10 0 </Re que stT ime o ut>

39 < Res pon seT i m e o ut>2000 < / Res p ons eTi meo ut >

</Ti meo ut >

41 < / Mai lb ox >

</Info >

43 < Gro upT ype > T rin ami cEV AL </ Gr oup Typ e >

45 <Dc >

< O p Mod e >

47 < Na me>Sy nch ro n < / Na me>

< De sc>Fr ee Run / SM-Sy nch ron < / D e sc>

49 < Ass ign Act iva t e >#x 0 </As sig nAc tiv a te>

</Op Mo de >

51 < OpM ode >

< Na me>D C </ N ame >

53 < De sc>DC-Sy nch ron < / Desc >

< Ass ign Act iva t e >#x300 < / Ass i g n A cti vat e >

55 < Cyc leT ime Syn c 0 Facto r ="1" >0</ C ycl eTi meS ync 0 >

< Shi ftT ime Syn c 0 >0< / S hif tTi meS ync 0 >

57 < Cyc leT ime Syn c 1 Facto r ="1" >0</ C ycl eTi meS ync 1 >

< Shi ftT ime Syn c 1 >0< / S hif tTi meS ync 1 >

59 < / OpMod e >

</D c >

< E e pro m >

63 < Byt e S ize >2048 < / Byt eSi ze>

<!-- G ene ral / Start -up ESC C onf igu rat ion - ->

65 < Con fig Dat a > 05 0 E 034 EC4 090 0 000 000 < / Con fig Dat a >

67

69

71 < C at ego ry >

< Ca tNo > 1 </ C atN o >

73 < Da ta>

000 0 000 000 0 000 0 000 000 0 000 000 0 000 0000 000 0 000 000 0 000 000 0 0

75 0 000 0 000 000 0 000 000 0 000 0 000 000 0 000 000 0 000 00 0 0 000 0 000 000 0

000 0 000 000 0 000 0 000 000 0 000 000 0 000 0000 000 0 000 000 0 000 000 0 0

77 0 000 000 0 000 000 0 000 000 0 000 000 0 00

</Data >

79 < / Cat ego ry >

</Ee pr om >

< Ima geD ata 16x 1 4 >42 4 d d60 200 0 000 0 000 003 6 000 000 2 800 000 0 100 0000 00e 0 000 000

83 100 180 0 0 0 0 000 00 a00 2 000 013 0 b00 001 3 0b0 000 0 000 000 0 000 000

...

85 b3b 3 b3b 3b 3 b 3b3 b 3b3 b3b 3 b3b 3b3 b 3b3 b3b 3 aca ca c 1 c1c 1 c

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</Im age Dat a 16x 14>

87 </De vi ce >

</De vic es >

89 </De scr ipt ion s >

</Et her CAT Inf o >

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5 Revision History

5.1 Document Revision

Version Date Author Description

1.00 2018-02-26 SK Initial release.

Table 9: Document Revision