TRENTON SLE Technical Reference Manual (Chassis Plans)

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SLE

S5891-xxx

TECHNICAL REFERENCE

Pentium

PROCESSOR-BASED

III

SBC

Page 2

Page 3

WARRANTY The product is warranted against material and manufacturing defects for two years from

date of delivery. Buyer agrees that if this product proves defective Chassis Plans, LLC is only obligated to repair, replace or refund the purchase price of this product at Chassis Plans’ discretion. The warranty is void if the product has been subjected to alteration, neglect, misuse or abuse; if any repairs have been attempted by anyone other than Chassis Plans, LLC; or if failure is caused by accident, acts of God, or other causes beyond the control of Chassis Plans, LLC Chassis Plans, LLC reserves the right to make changes or improvements in any product without incurring any obligation to similarly alter products previously purchased.

In no event shall Chassis Plans, LLC be liable for any defect in hardware or software or loss or inadequacy of data of any kind, or for any direct, indirect, incidental or consequential damages arising out of or in connection with the performance or use of the product or information provided. Chassis Plans, LLC’s liability shall in no event exceed the purchase price of the product purchased hereunder. The foregoing limitation of liability shall be equally applicable to any service provided by Chassis Plans, LLC

ETURN POLICY Products returned for repair must be accompanied by a Return Material Authorization

(RMA) number, obtained from Chassis Plans prior to return. Freight on all returned items must be prepaid by the customer, and the customer is responsible for any loss or damage caused by common carrier in transit. Items will be returned from Chassis Plans via Ground, unless prior arrangements are made by the customer for an alternative shipping method

To obtain an RMA number, call us at (858) 571-4330. We will need the following information:

Return company address and contact Model name and model # from the label on the back of the board Serial number from the label on the back of the board Description of the failure

An RMA number will be issued. Mark the RMA number clearly on the outside of each box, include a failure report for each board and return the product(s) to:

Chassis Plans, LLC 8295 Aero Place, Suite 200 San Diego, CA 92123 Attn: Repair Department (858) 571-4330

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TRADEMARKS IBM, PC, VGA, EGA, OS/2 and PS/2 are trademarks or registered trademarks

of International Business Machines Corp. AMI and AMIBIOS are trademarks of American Megatrends Inc. Intel and Pentium are registered trademarks of Intel Corporation. ServerSet is a trademark of ServerWorks. MS-DOS and Microsoft are registered trademarks of Microsoft Corp. PICMG and the PICMG logo are registered trademarks of the PCI Industrial

Computer Manufacturers Group.

All other brand and product names may be trademarks or registered trademarks

of their respective companies.

IABILITY

DISCLAIMER

This manual is as complete and factual as possible at the time of printing; however, the information in this manual may have been updated since that time. Chassis Plans, LLC reserves the right to change the functions, features or specifications of their products at any time, without notice.

E-mail: Support@chassisplans.com Web: www.ChassisPlans.com

Chassis Plans, LLC 8295 Aero Place Suite 200 • San Diego, California 92123 Sales: (858) 571-4330 • Fax: (858) 571-6146

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SLE Technical Reference

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SBC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3

SBC Processor Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Bus Speed - ISA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

Bus Speed - PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

Bus Speed - System & Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

System & Memory Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

DMA Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

BIOS (Flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

DRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

Error Checking and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

PCI Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Symmetric Multiprocessing (SMP) . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Super VGA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

System Hardware Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

PCI 10/100Base-T Ethernet Interfaces (Dual) . . . . . . . . . . . . . . . . . 1-8

PCI SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

PCI Enhanced IDE Interfaces (Dual) . . . . . . . . . . . . . . . . . . . . . . . .1-9

Floppy Drive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Enhanced Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

PS/2 Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Power Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

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SLE Technical Reference

Table of Contents

Specifications (continued)

Temperature/Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Mean Time Between Failures (MTBF) . . . . . . . . . . . . . . . . . . . . . 1-11

UL Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

Ethernet LEDs and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14

System BIOS Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

ISA/PCI Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

ISA Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

ISA Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

ISA Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

PCI Local Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

PCI Local Bus Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

PCI Local Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

PCI Local Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

PCI Local Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . .2-14

PICMG Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . 2-18

System BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

BIOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Password Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

BIOS Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Running AMIBIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

BIOS Setup Utility Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

BIOS Setup Utility Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

Security Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Change Supervisor Password . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Disabling Supervisor Password. . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Change User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

Clear User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Boot Sector Virus Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Exit Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

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SLE Technical Reference

Advanced Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Chipset Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

PCI Plug and Play Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

Boot Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

Table of Contents

SuperIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

IDE Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

IDE Device Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Floppy Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17

Boot Settings Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19

Event Log Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

Remote Access Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29

Boot Device Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

Hard Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Removable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

ATAPI CDROM Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Appendix A - BIOS Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

BIOS Beep Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

BIOS Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

ISA BIOS NMI Handler Messages . . . . . . . . . . . . . . . . . . . . . . . . A-5

Bootblock Initialization Code Checkpoints . . . . . . . . . . . . . . . . . . A-6

Bootblock Recovery Code Checkpoints. . . . . . . . . . . . . . . . . . . . . A-7

Post Code Checkpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

DIM Code Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13

Additional Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14

Declaration of Conformity

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SLE Technical Reference

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SLE Technical Reference

HANDLING PRECAUTIONS

OLDER-SIDE

COMPONENTS

_______________________________________________________________________

WA R NI N G : This product has components which may be damaged by electrostatic discharge. _______________________________________________________________________

To protect your single board computer (SBC) from electrostatic damage, be sure to observe the following precautions when handling or storing the board:

• Keep the SBC in its static-shielded bag until you are ready to perform your

installation.

• Handle the SBC by its edges.

• Do not touch the I/O connector pins. Do not apply pressure or attach labels

to the SBC.

• Use a grounded wrist strap at your workstation or ground yourself

frequently by touching the metal chassis of the system before handling any components. The system must be plugged into an outlet that is connected to an earth ground.

• Use antistatic padding on all work surfaces.

• Avoid static-inducing carpeted areas.

This SBC has components on both sides of the PCB. It is important for you to observe the following precautions when handling or storing the board to prevent solder-side components from being damaged or broken off:

• Handle the board only by its edges.

• Store the board in padded shipping material or in an anti-static board rack.

• Do not place an unprotected board on a flat surface.

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SLE Technical Reference

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SpecificationsSLE Technical Reference

Chapter 1 Specifications

INTRODUCTION The SLE full-featured PCI/ISA processors are single board computers (SBCs) which

feature dual Intel Pentium III (FC-PGA) microprocessors, ServerWorks ServerSet III LE chipset, 133MHz system and memory buses, Intel 69030 video interface, 2GB SDRAM, PCI Local Bus, cache, floppy controller, dual EIDE (Ultra DMA/33) interfaces, PCI Ultra3 SCSI controller, dual PCI 10/100Base-T Ethernet controllers, two

MODELS

serial ports, parallel port, speaker port and mouse/keyboard port on a single ISA-size card. These single-slot, high performance SBCs plug into PICMG backplanes and provide full PC compatibility for the system expansion slots.

Model #

Model Name Speed



PCI/ISA passive

S5891-603-xM S5891-602-xM S5891-601-xM

S5891-407-xM S5891-406-xM S5891-405-xM S5891-404-xM S5891-403-xM S5891-402-xM S5891-401-xM

where xM indicates memory size (0M = 0MB memory,

8M =8MB memory, etc.)

FEATURES • Intel Pentium III (FC-PGA) microprocessors

• 1.4GHz, 1.26GHz or 1.13GHz with 512K cache

• 1.0BGHz, 933MHz, 866MHz, 800EBMHz, 733MHz, 667MHz or

600EBMHz with 256K cache

• ServerWorks ServerSet III LE chipset with 133MHz system and memory buses

• Dual microprocessors using Symmetric Multiprocessing (SMP)

• PCI Local Bus operating in 64-bit/66MHz, 64-bit/33MHz or 32-bit/33MHz

mode

SLE/1.4 SLE/1.26 SLE/1.13

SLE/1.0B SLE/933 SLE/866 SLE/800EB SLE/733 SLE/667 SLE/600EB

1.4GHz

1.26GHz

1.13GHz

1.0GHz 933GHz 866GHz 800GHz 733GHz 667GHz 600MHz

• Super VGA on-board video interface (Intel 69030)

• PCI Local Bus supports off-board PCI option cards, dual PCI 10/100Base-T

Ethernet controllers and on-board PCI Ultra3 SCSI controller (QLogic

ISP10160A)

• DRAM error checking and correction (ECC) support

• Compatible with PCI Industrial Computer Manufacturers Group (PICMG) 1.0

Specification

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Specifications SLE Technical Reference

FEATURES (CONTINUED)

• Supports up to 2GB of Synchronous DRAM (SDRAM) on-board

• Floppy drive and dual PCI EIDE Ultra DMA/33 drive interfaces

• Two serial ports and one parallel port

• Automatic or manual peripheral configuration

• Watchdog timer

• System hardware monitor

• Shadow RAM for System BIOS and peripherals increases system speed and

performance

• Full PC compatibility

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SBC BLOCK DIAGRAM

SpecificationsSLE Technical Reference

Chassis Plans 1-3

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Specifications SLE Technical Reference

SBC PROCESSOR BOARD LAYOUT

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PROCESSORS • Two Intel Pentium III microprocessors

• 1.4GHz, 1.26GHz or 1.13GHz with 512K cache

• 1.0BGHz, 933MHz, 866MHz, 800EBMHz, 733MHz, 667MHz or

600EBMHz with 256K cache

• Processors use the Socket 370 Flip Chip Pin Grid Array (FC-PGA) packaging

BUS INTERFACES ISA and PCI Local Bus compatible

DATA PATH DRAM/Memory - 64-bit

ISA Bus - 16-bit

PCI Bus - 32-bit or 64-bit

Video - 32-bit

US SPEED - ISA 8.33MHz

BUS SPEED - PCI 33MHz or 66MHz

SpecificationsSLE Technical Reference

US SPEED -

133MHz Front Side Bus

SYSTEM & MEMORY

SYSTEM & MEMORY BUSES

The ServerWorks ServerSet III LE chipset supports the system and memory buses at 133MHz, which provides a higher bandwidth path for transferring data between main memory/chipset and the processors.

DMA CHANNELS The SBC is fully PC compatible with seven DMA channels, each supporting type F

transfers.

NTERRUPTS The SBC is fully PC compatible with interrupt steering for PCI plug and play compati-

bility.

BIOS (FLASH) The BIOS is an AMIBIOS with built-in advanced CMOS setup for system parameters,

peripheral management for configuring on-board peripherals, PCI-to-PCI bridge support and PCI interrupt steering. The BIOS chip is a boot block Flash device - 28F002BX or 28F004BT. The BIOS may be upgraded from floppy disk by pressing <Ctrl> + <Home> immediately after reset or power-up with the floppy disk in drive A:. Custom BIOSs are available.

CACHE MEMORY The Pentium III processors include integrated on-die, 256K or 512K 8-way set

associative level two (L2) cache. The L2 cache implements the Advanced Transfer Cache architecture with a 256-bit wide bus. The processors also include a 16K level one (L1) instruction cache and 16K L1 data cache. These cache arrays run at the full speed of the processor core.

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Specifications SLE Technical Reference

DRAM MEMORY The DRAM interface consists of two dual in-line memory module (DIMM) sockets and

supports auto detection of memory up to 2GB of Synchronous DRAM (SDRAM). The System BIOS automatically detects memory type, size and speed.

The SBC uses industry standard 72-bit wide gold finger DIMM SDRAM modules in two 168-pin DIMM sockets. ______________________________________________________________________

NOTE: Memory can be installed in one or both DIMM sockets. If only one DIMM module is used, it must be populated in the top DIMM socket (Bank 0 - BK0). If two modules are used, they must be the same DIMM type, but may be different sizes (see table below). EDO DIMMs and unbuffered SDRAM DIMMs are not supported. All DIMMs must have gold contacts. ______________________________________________________________________

The SBC supports DIMM memory modules which are PC-133 compliant and have the following features:

• 168-pin DIMMs with gold-plated contacts

• 133MHz SDRAM

• ECC (72-bit) memory

• 3.3 volt

RROR CHECKING

AND CORRECTION

PCI LOCAL BUS INTERFACE

• Registered configuration

The following DIMM sizes are supported:

DIMM

Size

64MB 128MB 256MB 512MB

1GB

DIMM Type ECC

Registered Registered Registered Registered Registered

8M x 72 16M x 72 32M x 72

64M x 72

128M x 72

All memory components and DIMMs used with the SBC must be PC-133 compliant, which means that they comply with IBM's PC133 SDRAM Registered DIMM Design Specification.

The memory interface supports ECC modes via BIOS setting for multiple-bit error detection and correction of all errors confined to a single nibble.

The SBC is fully compliant with the PCI Local Bus 2.1 Specification. The SBC supports two independent PCI Bus interfaces: a 32-bit Primary PCI Bus interface (33MHz) and a 64-bit Secondary (33/66MHz) Bus interface. Both Primary and Secondary PCI Bus interfaces provide a sixteen deep I/O cache and a four deep request queue for PCI to memory cycles. Both the interfaces provide a four deep quad word write posting for PCI master cycles to memory. The I/O cache supports the MESI protocol of processor bus, thereby keeping the I/O cache data always coherent with the rest of the system.

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NIVERSAL SERIAL

BUS (USB)

SpecificationsSLE Technical Reference

The Primary PCI interface is 32 bits wide and runs at 33MHz. This bus supports the on-board SCSI, video and dual Ethernet interfaces.

The Secondary PCI interface is 64 bits wide and runs at 33/66MHz. This interface provides a sixteen-entry I/O cache and is routed off-board to drive PICMG compliant PCI/ISA passive backplanes.

The SBC supports PCI-to-PCI bridge technology, a pipelined snoop ahead feature and improved PCI to DRAM write-back policy. The PCI Local Bus interfaces to standard PCI option cards in the backplane and to the on-board PCI Ultra3 SCSI controller and dual PCI 10/100Base-T Ethernet controllers. The PCI Local Bus interface to the backplane is compliant with the PCI Industrial Computer Manufacturers Group (PICMG) 1.0 Specification.

The SBC supports two USB 1.0 ports for serial transfers at 12 or 1.5Mbit/sec. The Universal Serial Bus (USB) is an interface allowing for connectivity to many standard PC peripherals via an external port.

SYMMETRIC MULTIPROCESSING (SMP)

SUPER VGA INTERFACE

YSTEM

HARDWARE MONITOR

The dual Pentium III processor-based design allows the operating system to assign tasks on demand to the next available processor. SMP uses applications which are divided into threads which can run concurrently on any available processor. This improves performance of the application itself as well as the total throughput of the system.

The Intel 69030 HiQVideo video interface integrates 4MB of high-speed SDRAM frame buffer memory into the chip.

By embedding SDRAM and graphics controller logic on the same die, the 69030 delivers uncompromising performance. The increase in the frame buffer bandwidth enables the 69030 to support high-color, high-resolution graphics modes and real-time video acceleration. The interface supports pixel resolutions up to 1280 x 1024 x True Color non-interlaced. Software drivers for enhanced performance and resolution are available for most popular operating systems.

The system hardware monitoring system monitors system voltages, temperature and fan speeds.

The circuitry is based on National Semiconductor's LM80. The LM80 monitors seven system voltages, two fan speeds and the board ambient temperature. All of the voltages, fan speeds and temperature measurements have associated programmable watchdog limits. When any of these programmed limits are exceeded, the monitor software can be used to notify the SBC. In addition, the externally available OS# signal can be used to notify external hardware of any over-temperature condition.

Fan speed monitoring can be configured to monitor two system fans.

The LM80 also monitors an external chassis intrusion switch via the system hardware monitor connector (P18).

A general purpose output (GPO) is also provided at the system hardware monitor connector. This signal can be used to provide a user-defined function.

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Specifications SLE Technical Reference

The following system voltages are monitored by the LM80:

• -12 volts

• 3.3 volts provided by the on-board voltage regulator for components on the

SBC

• 3.3 volts backplane power used by the option slots

• +5 volts

• +12 volts

• VCC_CORE, voltage provided by on-board VRM

• 1.5 volt, VTT voltage used by processor's GTL+ bus

PCI 10/100B ETHERNET INTERFACES (DUAL)

PCI SCSI I

NTERFACE

ASET

The dual PCI Ethernet interfaces are implemented using two Intel 82559 Ethernet controllers and operate in 10Base-T and 100Base-TX Fast Ethernet modes. The interfaces are compliant with IEEE 802.3 and PCI Local Bus 2.1 Specifications.

The main components of each interface are:

• Intel 82559 for 10/100-Mb/s media access control (MAC) with SYM, a

serial ROM port and a PCI Bus Master interface

• Serial ROM for storing the Ethernet address and the interface configuration

and control data

• Integrated RJ-45/Magnetics module connector on the SBC's I/O bracket for

direct connection to the network. The connector requires a category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category 3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection.

• Link status and activity LEDs on the I/O bracket for status indication (See

Ethernet LEDs and Connectors later in this chapter.)

Software drivers are supplied for most popular operating systems.

The SCSI interface supports Ultra3 SCSI data transfer using QLogic's ISP10160A SCSI controller, which supports SCSI data transfer up to 160MB per second. The interface is Ultra3 LVD, which may be used with high performance drives, such as Ultra 160 drives, to get maximum performance. The Ultra3 features of this channel are double-edge clocking, domain validation and cyclical redundancy checking.

Active termination is provided with terminator voltage protected by self-resetting fuses. Two jumpers (JU9 and JU9A) are provided to disable the termination (see the Configu- ration Jumpers section later in this chapter). Software drivers are available for most popular operating systems.

The QLogic Fast!UTIL Configuration Utility allows you to view and/or change the default configuration settings for the Ultra3 SCSI adapter. You may press <Alt> + <Q> to invoke the configuration utility.

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PCI ENHANCED IDE INTERFACES (DUAL)

FLOPPY DRIVE INTERFACE

Dual high performance PCI Bus Master EIDE interfaces are capable of supporting two IDE disk drives each in a master/slave configuration. The interfaces support Ultra DMA/33 with synchronous DMA mode transfers up to 33MB per second.

The SBC supports two floppy disk drives. Drives can be 360K to 2.88MB, in any combination.

SERIAL INTERFACE Two high-speed FIFO (16C550) serial ports with independently programmable baud

rates are supported. The IRQ for each serial port has BIOS selectable addressing.

ENHANCED PARALLEL INTERFACE

PS/2 MOUSE INTERFACE

The SBC provides a PC/AT compatible bidirectional parallel port and supports enhanced parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode is IEEE 1284 compliant. The IRQ for the parallel port has BIOS selectable addressing.

The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by using either the PS/2 mouse header or the bracket mounted mouse/keyboard mini DIN connector. The mouse may be connected directly to the mini DIN connector or to the "mouse" side of the "Y" adapter. Mouse voltage is protected by a self-resetting fuse.

EYBOARD

INTERFACE

The SBC is compatible with an AT-type keyboard. The keyboard connection can be made by using either the keyboard header or the "keyboard" side of the "Y" adapter plugged into the bracket mounted mouse/keyboard mini DIN connector. Keyboard voltage is protected by a self-resetting fuse.

WATCHDOG TIMER The watchdog timer is a hardware timer which resets the SBC if the timer is not

refreshed by software periodically. The timer is typically used to restart a system in which an application becomes hung on an external event. When the application is hung, it no longer refreshes the timer. The watchdog timer then times out and resets the SBC.

The watchdog timer has two levels of enable. First, the watchdog timer jumper must be moved to the "enabled" position, which puts the watchdog timer under software control.

The second level involves software control of the watchdog's timer retriggering. The SouthBridge (U8) General Purpose Port Register (GPM) at I/O address C52(h) must be set to a 0B(h), which blocks the triggering clock to the watchdog timer circuit, thus scheduling a hardware reset in about 1.5 seconds.

To refresh the watchdog timer, the software in the application must toggle bit 3 of the GPM register. First, a 0F(h) must be written to the GPM register to clear the watchdog timer delay; then the register must be set to a 0B(h), which schedules a system reset in

1.5 seconds. The toggling of bit 3 as specified must occur within a period of less than

1.5 seconds to insure that a system reset is not issued.

A set of watchdog timer software code and sample programs are available from Technical Support.

OWER FAIL

DETECTION

A hardware reset is issued when on-board +5V voltage drops below 4.75 volts. In addition, if the 3.3V Monitor jumper (JU15) is enabled, a reset is issued if 3.3V is below tolerance. (See the Configuration Jumpers section later in this chapter.)

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BATTERY A built-in lithium battery is provided, for ten years of data retention for CMOS memory.

______________________________________________________________________

CAUTION: There is a danger of explosion if the battery is incorrectly replaced. Replace it only with the same or equivalent type recommended by the manufacturer. Dispose of used batteries according to the manufacturer's instructions. ______________________________________________________________________

POWER REQUIREMENTS

+5V Typical

1.26GHz

1.0GHz

1.0GHz 866MHz 733MHz 667MHz

+12V @ 500 mAmps Rev. L-07 and later +12V @ 600 mAmps Rev. K-06 and earlier

-12V @ < 100 mAmps

______________________________________________________________________

CAUTION: When configuring an SLE-based system with processor speeds of 1.0GHz or greater, the system integrator needs to ensure adequate power delivery. These highspeed processors can require the on-board voltage regulators (VRMs) to supply greater than 20 Amps to each processor. The input source voltage of the VRMs is the +5 volts that is sourced to the SBC through both the PCI and ISA card edge fingers. Even with VRM efficiency of 90%, this translates into a +5V current requirement in excess of 14 Amps.

With this high +5V current requirement, along with the 5-volt +/- 5% tolerance requirement, it is important that the power delivery system is adequate to provide a reliable +5 volts. An inadequate power delivery system will result in the +5V rail on the SLE SBC to drop below 4.75 volts under high current conditions, resulting in random system resets.

14.95 Amps

14.02 Amps

13.6 Amps

11.4 Amps

10.5 Amps

7.8 Amps

Rev. L-07 and later Rev. K-06 and earlier

The single most important item in the power delivery system is the power supply. The integrator should choose a power supply that will minimize the DC voltage drop from the supply to the system backplane when delivering high currents. The gauge of the power supply's wires, number of wires and the type of connectors used are key items to consider. Most of today's high wattage (400W) power supplies will address all of these issues.

______________________________________________________________________

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TEMPERATURE/ ENVIRONMENT

MEAN TIME BETWEEN FAILURES (MTBF)

ECOGNITION This SBC is a UL recognized product listed in file #E208896.

UL R

Operating Temperature: 0º C. to 50º C. for 1.26GHz and above

0º C. to 45º C. for 1.0GHz 0º C. to 50º C. for 933MHz 0º C. to 60º C. for 866MHz and below

Storage Temperature: - 40º C. to 70º C.

Humidity: 5% to 90% non-condensing

148,000 POH (Power-On Hours) at 40° C., per Bellcore

This board was investigated and determined to be in compliance under the Bi-National Standard for Information Technology Equipment. This included the Electrical Business Equipment, UL 1950, Third Edition, and CAN/CSA C22.22 No. 950-95.

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CONFIGURATION JUMPERS

The setup of the configuration jumpers on the SBC is described below. * indicates the default value of each jumper. ______________________________________________________________________

NOTE: For two-position jumpers (3-post), "TOP" is toward the memory sockets; "BOTTOM" is toward the edge fingers. ______________________________________________________________________

Jumper

JU8 Password Clear

JU9/JU9A SCSI Termination - Channel 0

Description

Install for one power-up cycle to reset the password to the default (null password). Remove for normal operation. *

These two jumpers may be used to enable or disable on-board active termination for the Ultra3 SCSI interface - Channel 0.

JU9

Enable active termination Install * Install * Disable active termination Remove Remove Enable upper byte only Remove Install

JU9A

JU10/JU11 System Flash ROM Operational Modes

The Flash ROM has two programmable sections: the Boot Block for “flashing” in the BIOS and the Main Block for the executable BIOS and PnP parameters. Normally only the Main Block is updated when a new BIOS is flashed into the system.

JU10

Program All (Boot and Main) Top Top Normal PnP (Program Main Block) Top * Bottom * Write Protect Bottom Bottom

JU12 CMOS Clear

Install to clear. Remove to operate. * __________________________________________________

NOTE: The CMOS Clear jumper works on power-up. To clear the CMOS, power down the system, install the jumper, then turn the power back on. CMOS is cleared during the POST routines. Wait for AMIBIOS to display a "CMOS Checksum Bad" message; then power down the system again and remove the jumper before the next power-up. __________________________________________________

JU11

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CONFIGURATION JUMPERS (CONTINUED)

Jumper

JU15 3.3V Monitor Enable

JU16 Watchdog Timer

Description

Install to enable the 3.3V monitor. Remove to disable the monitor. *

NOTE: On SBCs with revision L-07 and later, the position of this jumper is horizontal; on earlier revisions it is vertical. __________________________________________________

NOTE: JU15 enables the 3.3 volt monitor, which monitors the 3.3V power plane of the backplane. This voltage is routed to the SBC via the PICMG connector. The monitor generates a RESET to the SBC if 3.3V is below tolerance. If your system does not supply 3.3V to the backplane, this jumper must be removed (disabled). __________________________________________________

Install on the TOP to enable watchdog timer operation. Install on the BOTTOM for normal reset operation. *

SpecificationsSLE Technical Reference

JU19 SCSI Activity LED Enable

Install to light the hard drive LED for SCSI drive activity. * Remove if you do not have a SCSI drive (i.e., the SCSI controller is not being used).

W7 Spread Spectrum Enable

Install to enable spread spectrum for the processor oscillator, which may reduce EMI levels at some frequencies. * Remove to disable.

NOTE: The W7 jumper is included on SBCs with revision J-05 and later. Revisions of H-04 and earlier do not have this jumper.

On revisions L-07 and later, the default for W7 is "enabled"; on earlier revisions, the default was "disabled."

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ETHERNET LEDS

AND CONNECTORS

Each Ethernet interface has two LEDs for status indication and an RJ-45 network connector.

LED/Connector

Link/Activity LED Green LED which indicates the link status

Off The Ethernet interface did not find a valid link on the

On (solid) The Ethernet interface has a valid link on the network

On (flashing) Indicates network transmit or receive activity.

Speed LED Amber LED which identifies the connection speed.

Off Indicates a 10Mb/s connection.

On Indicates a 100Mb/s connection.

RJ-45 Network Connector

Description

network connection. Transmit and receive are not possible.

connection and is ready for normal operation. The Speed LED identifies connection speed.

The RJ-45 network connector requires a category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category 3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection.

SYSTEM BIOS SETUP UTILITY

The System BIOS is an AMIBIOS with a ROM-resident setup utility. The BIOS Setup Utility allows you to select the following categories of options:

• Main Menu

• Advanced Setup

• Chipset Setup

• PCIPnP Setup

• Boot Setup

• Security Setup

• Exit

Each of these options allows you to review and/or change various setup features of your system. Details are provided in the following chapters of this manual.

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CONNECTORS ______________________________________________________________________

NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB. ______________________________________________________________________

P1 - PCI 10/100Base-T Ethernet Connector

8 pin shielded RJ-45 connector, Pulse #J0035D21B

Signal

TD+

TD-

RX+

RX-

P2 - CPU Fan 2

3 pin single row header, Molex #22-23-2031

Signal

Gnd

+12V

FanTach

P3 - Floppy Drive Connector

34 pin dual row header, Amp #103308-7

Signal

Gnd

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34

Signal N-RPM NC D-Rate0 P-Index N-Motoron 1 N-Drive Sel2 N-Drive Sel1 N-Motoron 2 N-Dir N-Stop Step N-Write Data N-Write Gate P-Track 0 P-Write Protect N-Read Data N-Side Select Disk Chng

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CONNECTORS (CONTINUED)

P4A - Keyboard Header

5 pin single row header, Amp #640456-5

Signal

Kbd Clock

Kbd Data

Key

Kbd Gnd

Kbd Power (+5V fused) with self-resetting fuse

P5 - Speaker Port Connector

4 pin single row header, Amp #640456-4

Signal

Speaker Data

Key

Gnd

+5V

P6 - Serial Port 1 Connector

10 pin dual row header, Amp #103308-1

Signal

Carrier Detect

Receive Data-I

Transmit Data-O

Data Terminal Ready-O

Signal Gnd

P7 - Serial Port 2 Connector

10 pin dual row header, Amp #103308-1

Signal

Carrier Detect

Receive Data-I

Transmit Data-O

Data Terminal Ready-O

Signal Gnd

P8 - Parallel Port Connector

26 pin dual row header, Amp #103308-6

Signal

Strobe

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Signal

Data Set Ready-I

Request to Send-O

Clear to Send-I

Ring Indicator-I

Signal

Data Set Ready-I

Request to Send-O

Clear to Send-I

Ring Indicator-I

Signal

Auto Feed XT

Error

Init

Slct In

Gnd

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CONNECTORS (CONTINUED)

SpecificationsSLE Technical Reference

P8 - Parallel Port Connector (continued)

Signal

Pin 11

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

ACK

Busy

Paper End

Slct

P9 - PS/2 Mouse and Keyboard Connector

6 pin mini DIN, Kycon #KMDG-6S-BS-PS

Signal

Ms Data

Kbd Data

Gnd

Power (+5V fused) with self-resetting fuse

Ms Clock

Kbd Clock

P9A - PS/2 Mouse Header

6 pin single row header, Amp #640456-6

Signal

Ms Data

Reserved

Kbd Gnd

Kbd Power (+5V fused) with self-resetting fuse

Ms Clock

Reserved

Pin 12 14 16 18 20 22 24 26

Signal Gnd Gnd Gnd Gnd Gnd Gnd Gnd NC

P10 - External Reset Connector

2 pin single row header, Amp #640456-2

Signal

External Reset In (Low Active)

Gnd

P11 - Primary IDE Hard Drive Connector

40 pin dual row header, 3M #30340-6002HB

1 3 5 7 9

Signal Reset Data 7 Data 6 Data 5 Data 4

8 10

Signal Gnd Data 8 Data 9 Data 10 Data 11

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CONNECTORS (CONTINUED)

P11 - Primary IDE Hard Drive Connector (continued)

Signal

Pin 11

Data 3

Data 2

Data 1

Data 0

Gnd

DRQ 0

IOW

IOR

IORDY

DACK 0

IRQ 14

Add 1

Add 0

CS 1P

IDEACTP

P11A - Secondary IDE Hard Drive Connector

40 pin dual row header, 3M #30340-6002HB

Signal

Reset

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

Gnd

DRQ 1

IOW

IOR

IORDY

DACK 1

IRQ 15

Add 1

Add 0

CS 1S

IDEACTS

Pin 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

Signal Data 12 Data 13 Data 14 Data 15 NC Gnd Gnd Gnd SELPDP Gnd NC Gnd Add 2 CS 3P Gnd

Signal Gnd Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 NC Gnd Gnd Gnd SELPDS Gnd NC Gnd Add 2 CS 3S Gnd

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CONNECTORS (CONTINUED)

P12 - Hard Drive LED Connector

4 pin single row header, Amp #640456-4

(This connector is used for both IDE and SCSI drives. See JU19 in the Configuration Jumpers section.)

Signal

+5V Pull-up

Light

+5V Pull-up

P13 - PCI Ultra3 SCSI Controller Connector - Channel 0

50/68 pin high density connector, Amp #749069-7

SpecificationsSLE Technical Reference

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Signal SCD12 SCD13 SCD14 SCD15 SCDPH SCD0 SCD1 SCD2 SCD3 SCD4 SCD5 SCD6 SCD7 SCDPL Gnd DIFSENSE TERMPWR TERMPWR NC Gnd SCATN Gnd SCBSY SCACK SCRST SCMSG SCSEL SCCD SCREQ SCIO SCD8 SCD9 SCD10 SCD11

Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Signal SCD#12 SCD#13 SCD#14 SCD#15 SCDPH# SCD#0 SCD#1 SCD#2 SCD#3 SCD#4 SCD#5 SCD#6 SCD#7 SCDPL# Gnd Gnd TERMPWR TERMPWR NC Gnd SCATN# Gnd SCBSY# SCACK# SCRST# SCMSG# SCSEL# SCCD# SCREQ# SCIO# SCD#8 SCD#9 SCD#10 SCD#11

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CONNECTORS (CONTINUED)

P15 - PCI SVGA Interface Connector

15 pin VGA Ultra Compact connector, Kycon #K31-E15S-N

Signal

EEDI

HSYNC

VSYNC

EECS

Pin Signal

6Gnd

1Red

7Gnd

2 Green

8Gnd

3Blue

9+5V

4NC

10 Gnd

5Gnd

P16 - PCI 10/100Base-T Ethernet Connector

8 pin shielded RJ-45 connector, Pulse #J0035D21B

Signal

TD+

TD-

RX+

RX-

P17 - Universal Serial Bus (USB) Connector

8 pin dual row header, Molex #702-46-0821 (+5V fused with self-resetting fuses)

Signal

+5V-USB0

USB0-

USB0+

Gnd-USB0

P18 - System Hardware Monitor Connector

4 pin single row header, Amp #640456-4

Signal

Gnd

GPO (General Purpose Output)

CI (Chassis Intrusion Input)

OS# (Temperature Sense Output)

2 4 6 8

Signal +5V-USB1 USB1USB1+ Gnd-USB1

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CONNECTORS (CONTINUED)

P19 - CPU Fan 1

3 pin single row header, Molex #22-23-2031

Signal

Gnd

+12V

FanTach

SpecificationsSLE Technical Reference

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Chapter 2 ISA/PCI Reference

ISA BUS PIN NUMBERING

62-pin ISA Bus Connector

ISA/PCI ReferenceSLE Technical Reference

Component Side of Board

36-pin ISA Bus Connector

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ISA BUS PIN ASSIGNMENTS

The following tables summarize pin assignments for the Industry Standard Architecture (ISA) Bus connectors.

I/O Pin Signal Name I/O I/O Pin Signal Name I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

IOCHK# D7 D6 D5 D4 D3 D2 D1 D0 CHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

I I/O I/O I/O I/O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

Gnd RESDRV +5V IRQ9

-5V DRQ2

-12V NOWS# +12V Gnd SMWTC# SMRDC# IOWC# IORC# DAK3# DRQ3 DAK1# DRQ1 REFRESH# BCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DAK2# T-C BALE +5V OSC Gnd

Ground O Power I Power I Power I Power Ground O O I/O I/O O I O I I/O O I I I I I O O O Power O Ground

I/O Pin Signal Name I/O I/O Pin Signal Name I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 MRDC# MWTC# D8 D9 D10 D11 D12 D13 D14 D15

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18

M16# IO16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DAK0# DRQ0 DAK5# DRQ5 DAK6# DRQ6 DAK7# DRQ7 +5V Master16# Gnd

I I I I I I I O I O I O I O I Power I Ground

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ISA BUS SIGNAL DESCRIPTIONS

The following is a description of the ISA Bus signals. All signal lines are TTLcompatible.

AEN (O)

Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O channel to allow DMA transfers to take place. When this line is active, the DMA controller has control of the address bus, the data-bus Read command lines (memory and I/O), and the Write command lines (memory and I/O).

BALE (O) (Buffered)

Address Latch Enable (BALE) is provided by the bus controller and is used on the system board to latch valid addresses and memory decodes from the microprocessor. It is available to the I/O channel as an indicator of a valid microprocessor or DMA address (when used with AEN). Microprocessor addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced high during DMA cycles.

BCLK (O)

BCLK is the system clock. The clock has a 50% duty cycle. This signal should only be used for synchronization. It is not intended for uses requiring a fixed frequency.

CHRDY (I)

I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O device to lengthen I/ O or memory cycles. Any slow device using this line should drive it low immediately upon detecting its valid address and a Read or Write command. Machine cycles are extended by an integral number of clock cycles. This signal should be held low for no more than 2.5 microseconds.

D[15::0] (I/O)

Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor, memory, and I/O devices. D15 is the most-significant bit and D0 is the least-significant bit. All 8-bit devices on the I/O channel should use D[7::0] for communications to the microprocessor. The 16-bit devices will use D[15::0]. To support 8-bit devices, the data on D[15::8] will be gated to D[7::0] during 8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit devices will be converted to two 8-bit transfers.

DAK[7::5]#, DAK[3::0]# (O)

DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA requests DRQ[7::5] and DRQ[3::0]. They are active low.

DRQ[7::5], DRQ[3::0] (I)

DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests used by peripheral devices and the I/O channel microprocessors to gain DMA service (or control of the system). They are prioritized, with DRQ0 having the highest priority and DRQ7 having the lowest. A request is generated by bringing a DRQ line to an active level. A DRQ line must be held high until the corresponding DMA Request Acknowledge (DAK) line goes active. DRQ[3::0] will perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers.

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IO16# (I)

I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be driven with an open collector or tri-state driver capable of sinking 20 mAmps.

IOCHK# (I)

I/O Channel Check (IOCHK#) provides the system board with parity (error) information about memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable system error.

IORC# (I/O)

I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven by the system microprocessor or DMA controller, or by a microprocessor or DMA controller resident on the I/O channel. This signal is active low.

IOWC# (I/O)

I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by any microprocessor or DMA controller in the system. This signal is active low.

IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)

Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from low to high. The line must be held high until the microprocessor acknowledges the interrupt request (Interrupt Service routine).

LA[23::17] (I/O)

These signals (unlatched) are used to address memory and I/O devices within the system. They give the system up to 16MB of addressability. These signals are valid when BALE is high. LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles. These decodes should be latched by I/O adapters on the falling edge of BALE. These signals also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.

M16# (I)

M16# Chip Select signals the system board if the present data transfer is a 1<N>wait-state, 16bit, memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven with an open collector or tri-state driver capable of sinking 20 mAmps.

Master16# (I)

Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#. Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it to control the system address, data, and control lines (a condition known as tri-state). After Master16# is low, the I/O microprocessor must wait one system clock period before driving the address and data lines, and two clock periods before issuing a Read or Write command. If this signal is held low for more than 15<N>microseconds, system memory may be lost because of a lack of refresh.

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NOWS# (I)

The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit device without wait cycles, NOWS# is derived from an address decode gated with a Read or Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait states, NOWS# should be driven active on system clock after the Read or Write command is active gated with the address decode for the device. Memory Read and Write commands to a 8-bit device are active on the falling edge of the system clock. NOWS# is active low and should be driven with an open collector or tri-state driver capable of sinking 20 mAmps.

OSC (O)

Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This signal is not synchronous with the system clock. It has a 50% duty cycle.

REFRESH# (I/O)

The REFRESH# signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.

RESDRV (O)

Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a low line-voltage outage. This signal is active high.

SA[19::0] (I/O)

Address bits SA[19::0] are used to address memory and I/O devices within the system. These twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory. SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge of BALE. These signals are generated by the microprocessor or DMA Controller. They also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.

SBHE# (I/O)

System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus, D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8].

SMRDC# (O), MRDC# (I/O)

These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active only when the memory decode is within the low 1MB of memory space. MRDC# is active on all memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in the system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When a microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid on the bus for one system clock period before driving MRDC# active. Both signals are active low.

SMWTC# (O), MWTC# (I/O)

These signals instruct the memory devices to store the data present on the data bus. SMWTC# is active only when the memory decode is within the low 1MB of the memory space. MWTC# is active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB of memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have the address lines valid on the bus for one system clock period before driving MWTC# active. Both signals are active low.

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T-C (O)

Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached.

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I/O ADDRESS MAP*

ISA/PCI ReferenceSLE Technical Reference

Hex Range Device

INTERRUPT ASSIGNMENTS*

000-01F

020-03F

040-05F

060-06F

070-07F

080-09F

0A0-0BF

0C0-0DF

0F0

0F1

0F8-0FF

1F0-1F8

200-207

278-27F

2F8-2FF

300-31F

360-36F

378-37F

380-38F

3A0-3AF

3B0-3BF

3C0-3CF

3D0-3DF

3F0-3F7

3F8-3FF

Interrupt Description

DMA Controller 1 Interrupt Controller 1, Master Timer 8042 (Keyboard) Real-time Clock, NMI (non-maskable interrupt) Mask DMA Page Register Interrupt Controller 2 DMA Controller 2 Clear Math Coprocessor Busy Reset Math Coprocessor Math Coprocessor

Fixed Disk Game I/O Parallel Printer Port 2 Serial Port 2 Prototype Card Reserved Parallel Printer Port 1 SDLC, Bisynchronous 2 Bisynchronous 1 Monochrome Display and Printer Adapter Reserved Color/Graphics Monitor Adapter Diskette Controller Serial Port 1

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Timer Output 0 Keyboard (Output Buffer Full) Interrupt 8 through 15 Serial Port 2 Serial Port 1 Parallel Port 2 Diskette Controller Parallel Port 1 Real-time Clock Interrupt Software Redirected to INT 0AH (IRQ2) Unassigned Unassigned PS/2 Mouse Coprocessor Fixed Disk Controller Unassigned (may be assigned by the system to the secondary IDE)

* These are typical parameters, which may not reflect your current system.

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PCI LOCAL BUS OVERVIEW

The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards and processor/memory systems.

The "local bus" moves peripheral functions with high bandwidth requirements closer to the system’s processor bus and can produce substantial performance gains with graphical user interfaces (GUI’s) and other high bandwidth functions (i.e., full motion video, SCSI, LAN’s, etc.).

The PCI Local Bus accommodates future system requirements and is applicable across multiple platforms and architectures.

The PCI component and add-in card interface is processor independent, enabling an efficient transition to future processor generations, by bridges or by direct integration, and use with multiple processor architectures. Processor independence allows the PCI Local Bus to be optimized for I/O functions, enables concurrent operation of the local bus with the processor/memory subsystem, and accommodates multiple high performance peripherals in addition to graphics. Movement to enhanced video and multimedia displays and other high bandwidth I/O will continue to increase local bus bandwidth requirements. A transparent 64-bit extension of the 32-bit data and address buses is defined, doubling the bus bandwidth and offering forward and backward compatibility of 32-bit (132MB/s peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals.

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PCI LOCAL BUS SIGNAL DEFINITION

The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for a master to handle data and addressing, interface control, arbitration and system functions. The diagram below shows the pins in functional groups, with required pins on the left side and optional pins on the right side.

Required Pins:

Address & Data:

AD[31::00]

C/BE[3::0]#

PAR

Interface Control:

FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL

Error Reporting:

PERR# SERR#

Arbitration (masters only):

REQ# GNT#

System:

CLK RST#

PCI

COMPLIANT

DEVICE

Optional Pins:

64-bit Extension

AD[63::32]

C/BE[7::4]#

PAR 64 REQ64# ACK64#

Interface Control:

LOCK# INTA# INTB# INTC# INTD#

Cache Support:

SBO# SDONE

JTAG (IEEE 1149.1):

TDI TDO TCK TMS TRST#

PCI Pin List

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PCI LOCAL BUS PIN NUMBERING

Component Side of Board

5-volt/32-bit PCI Connector

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PCI LOCAL BUS PIN ASSIGNMENTS

The PCI Local Bus pin assignments shown below are for the PCI option slots on the backplane.

The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The following bus pin assignments are for the 5-volt connector. The 3.3-volt connector bus pin assignments are the same with the following exceptions:

* The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which

connector is being used.

† Pins B12, B13, A12 and A13 are Gnd (ground) on the 5-volt connector, but

are Connector Keys on the 3.3-volt connector.

†† Pin B49 is Gnd (ground) on the 5-volt connector, but is M66EN on the 3.3-

volt connector.

††† Pins B50, B51, A50 and A51 are Connectors Keys on the 5-volt connector,

but are Gnd (ground) on the 3.3-volt connector.

I/O Pin Signal Name I/O Pin Signal Name

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35

-12V TCK Gnd TDO +5V +5V INTB# INTD# PRSNT1# Reserved PRSNT2# Gnd

†

Gnd † Reserved Gnd CLK Gnd REQ# +V (I/O) * AD31 AD29 Gnd AD27 AD25 +3.3V C/BE3# AD23 Gnd AD21 AD19 +3.3V AD17 C/BE2# Gnd IRDY#

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35

TRST# +12V TMS TDI +5V INTA# INTC# +5V Reserved +V (I/O) * Reserved Gnd

†

Gnd † Reserved RST# +V (I/O) * GNT# Gnd Reserved AD30 +3.3V AD28 AD26 Gnd AD24 IDSEL +3.3V AD22 AD20 Gnd AD18 AD16 +3.3V FRAME# Gnd

32-bit connector

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PCI LOCAL BUS PIN ASSIGNMENTS (CONTINUED)

I/O Pin Signal Name I/O Pin Signal Name

B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B50 B51

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

+3.3V DEVSEL# Gnd LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 Gnd AD12 AD10 Gnd

††

Connector Key Connector Key †††

AD8 AD7 +3.3V AD5 AD3 Gnd AD1 +V (I/O) * ACK64# +5V +5V

†††

A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

TRDY# Gnd STOP# +3.3V SDONE SBO# Gnd PAR AD15 +3.3V AD13 AD11 Gnd AD9

Connector Key ††† Connector Key †††

C/BE0# +3.3V AD6 AD4 Gnd AD2 AD0 +V (I/O) * REQ64# +5V +5V 32-bit connector end

5-volt key 5-volt key

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PCI LOCAL BUS PIN ASSIGNMENTS (CONTINUED)

The following pin assignments apply only to backplanes with 64-bit PCI option slots.

I/O Pin Signal Name I/O Pin Signal Name

B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94

Connector Key Connector Key

Reserved Gnd C/BE6# C/BE4# Gnd AD63 AD61 +V (I/O) * AD59 AD57 Gnd AD55 AD53 Gnd AD51 AD49 +V (I/O) * AD47 AD45 Gnd AD43 AD41 Gnd AD39 AD37 +V (I/O) * AD35 AD33 Gnd Reserved Reserved Gnd

A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94

Connector Key Connector Key

Gnd C/BE7# C/BE5# +V (I/O) * PAR 64 AD62 Gnd AD60 AD58 Gnd AD56 AD54 +V (I/O) * AD52 AD50 Gnd AD48 AD46 Gnd AD44 AD42 +V (I/O) * AD40 AD38 Gnd AD36 AD34 Gnd AD32 Reserved Gnd Reserved

64-bit spacer 64-bit spacer

64-bit connector start

64-bit connector end

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PCI LOCAL BUS SIGNAL DESCRIPTIONS

The PCI Local Bus signals are described below and may be categorized into the following functional groups:

• System Pins

• Address and Data Pins

• Interface Control Pins

• Arbitration Pins (Bus Masters Only)

• Error Reporting Pins

• Interrupt Pins (Optional)

• Cache Support Pins (Optional)

• 64-Bit Bus Extension Pins (Optional)

• JTAG/Boundary Scan Pins (Optional)

A # symbol at the end of a signal name indicates that the active state occurs when the signal is at a low voltage. When the # symbol is absent, the signal is active at a high voltage.

The following are descriptions of the PCI Local Bus signals.

ACK64# (optional)

Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64bits. ACK64# has the same timing as DEVSEL#.

AD[31::00]

Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. During the address phase, AD[31::00] contain a physical address (32 bits). During data phases, AD[07::00] contain the least significant byte (lsb) and AD[31::24] contain the most significant byte (msb).

AD[63::32] (optional)

Address and Data are multiplexed on the same pins and provide 32additional bits. During an address phase (when using the DAC command and when REQ64# is asserted), the upper 32bits of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and indeterminate. During a data phase, an additional 32bits of data are transferred when REQ64# and ACK64# are both asserted.

C/BE[3::0]#

Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, these pins define the bus command; during the data phase they are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0# applies to byte0 (lsb) and C/BE3# applies to byte 3 (msb).

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C/BE[7::4]# (optional)

Bus Command and Byte Enables are multiplexed on the same pins. During an address phase (when using the DAC command and when REQ64# is asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to byte7.

CLK

Clock provides timing for all transactions on PCI and is an input to every PCI device.

DEVSEL#

Device Select, when actively driven, indicates that the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.

FRAME#

Cycle Frame is an interface control pin which is driven by the current master to indicate the beginning and duration of an access. When FRAME# is asserted, data transfers continue; when it is deasserted, the transaction is in the final data phase.

GNT#

Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master has its own GNT#.

IDSEL

Initialization Device Select is used as a chip select during configuration read and write transactions.

INTA#, INTB#, INTC#, INTD# (optional)

Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative true), using open drain output drivers. PCI defines one interrupt for a single function and up to four interrupt lines for a multi-function device or connector.

Interrupt A is used to request an interrupt. For a single function device, only INTA# may be used, while the other three interrupt lines have no meaning.

Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have meaning on a multi-function device.

IRDY#

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY# indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is prepared to accept data.

LOCK#

Lock indicates an operation that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked.

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PAR

Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. The master drives PAR for address and write data phases; the target drives PAR for read data phases.

PAR64 (optional)

Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#. The master drives PAR64 for address and write data phases; the target drives PAR64 for read data phases.

PERR#

Parity Error is for the reporting of data parity errors during all PCI transactions except a Special Cycle. There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed.

PRSNT1# and PRSNT2#

PRSNT1# and PRSNT2# are related to the connector only, not to other PCI components. They are used for two purposes: indicating that a board is physically present in the slot and providing information about the total power requirements of the board.

REQ#

Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master has its own REQ#.

REQ64# (optional)

Request 64-bit Transfer, when actively driven by the current bus master, indicates it desires to transfer data using 64 bits. REQ64# has the same timing as FRAME#. REQ64# has meaning at the end of reset.

RST#

Reset is used to bring PCI-specific registers, sequencers and signals to a consistent state.

SBO# (optional)

Snoop Backoff is an optional cache support pin which indicates a hit to a modified line when asserted. When SBO# is deasserted and SDONE is asserted, it indicates a "clean" snoop result.

SDONE (optional)

Snoop Done is an optional cache support pin which indicates the status of the snoop for the current access. When deasserted, it indicates the result of the snoop is still pending. When asserted, it indicates the snoop is complete.

SERR#

System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. If an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required.

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STOP#

Stop indicates that the current target is requesting the master to stop the current transaction.

TCK (optional)

Test Clock is used to clock state information and test data into and out of the device during operation of the TAP (Test Access Port).

TDI (optional)

Test Data Input is used to serially shift test data and test instructions into the device during TAP (Test Access Port) operation.

TDO (optional)

Test Data Output is used to serially shift test data and test instructions out of the device during TAP (Test Access Port) operation.

TMS (optional)

Test Mode Select is used to control the state of the TAP (Test Access Port) controller in the device.

TRDY#

Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. During a read, TRDY# indicates that valid data is present on AD[31::00]. During a write, it indicates that the target is prepared to accept data.

TRST# (optional)

Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional in the IEEE Standard Test Access Port and Boundary Scan Architecture.

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PICMG EDGE CONNECTOR PIN ASSIGNMENTS

The pin assignments shown below are for the PICMG portion of the edge connector on the processor board. These pin assignments match those of the PICMG connector of the processor slot on the backplane.

I/O Pin Signal Name I/O Pin Signal Name

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

-12V NC Gnd NC +5V +5V INTB# INTD# REQ3# REQ1# GNT3# Gnd Gnd CLKS0 Gnd CLKS1 Gnd REQ0# +5V AD31 AD29 Gnd AD27 AD25 BKPL3.3V C/BE3# AD23 Gnd AD21 AD19 NC AD17 C/BE2# Gnd IRDY# NC DEVSEL# Gnd LOCK# PERR# NC SERR# NC C/BE1# AD14 Gnd AD12 AD10 M66EN

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

NC +12V NC NC +5V INTA# INTC# +5V CLKS2 +5V CLKS3 Gnd Gnd GNT1# RST# +5V GNT0# Gnd REQ2# AD30 NC AD28 AD26 Gnd AD24 GNT2# NC AD22 AD20 Gnd AD18 AD16 NC FRAME# Gnd TRDY# Gnd STOP# NC SDONE SBO# Gnd PAR AD15 NC AD13 AD11 Gnd AD9

32-bit connector start

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PICMG EDGE CONNECTOR PIN ASSIGNMENTS (CONTINUED)

ISA/PCI ReferenceSLE Technical Reference

I/O Pin Signal Name I/O Pin Signal Name

B50 B51

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

Connector Key Connector Key

AD8 AD7 NC AD5 AD3 Gnd AD1 +5V ACK64# +5V +5V

A50 A51

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

Connector Key Connector Key

C/BE0# NC AD6 AD4 Gnd AD2 AD0 +5V REQ64# +5V +5V 32-bit connector end

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PICMG EDGE CONNECTOR PIN ASSIGNMENTS (CONTINUED)

The following pin assignments apply only to SBCs with 64-bit PICMG connectors.

I/O Pin Signal Name I/O Pin Signal Name

B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94

Connector Key Connector Key

NC Gnd C/BE6# C/BE4# Gnd AD63 AD61 +5V AD59 AD57 Gnd AD55 AD53 Gnd AD51 AD49 +5V AD47 AD45 Gnd AD43 AD41 Gnd AD39 AD37 +5V AD35 AD33 Gnd NC NC Gnd

A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94

Connector Key Connector Key

Gnd C/BE7# C/BE5# +5V PAR 64 AD62 Gnd AD60 AD58 Gnd AD56 AD54 +5V AD52 AD50 Gnd AD48 AD46 Gnd AD44 AD42 +5V AD40 AD38 Gnd AD36 AD34 Gnd AD32 NC Gnd NC

64-bit spacer 64-bit spacer

64-bit connector start

64-bit connector end

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Chapter 3 System BIOS

BIOS OPERATION Sections 3 through 7 of this manual describe the operation of the American Megatrends

AMIBIOS and the BIOS Setup Utility. Refer to Running AMIBIOS Setup later in this chapter for standard Setup screens, options and defaults. The available Setup screens, options and defaults may vary if you have a custom BIOS.

When the system is powered on, AMIBIOS performs the Power-On Self Test (POST) routines. These routines are divided into two phases:

1) System Test and Initialization. Test and initialize system boards for normal operations.

2) System Configuration Verification. Compare defined configuration with hardware actually installed.

If an error is encountered during the diagnostic tests, the error is reported in one of two different ways. If the error occurs before the display device is initialized, a series of beeps is transmitted. If the error occurs after the display device is initialized, the error message is displayed on the screen. See BIOS Errors later in this section for more information on error handling.

The following are some of the Power-On Self Tests (POST’s) which are performed when the system is powered on:

• CMOS Checksum Calculation

• Keyboard Controller Test

• CMOS Shutdown Register Test

• 8254 Timer Test

• Memory Refresh Test

• Display Memory Read/Write Test

• Display Type Verification

• Entering Protected Mode

• Memory Size Calculation

• Conventional and Extended Memory Test

• DMA Controller Tests

• Keyboard Test

• System Configuration Verification and Setup

AMIBIOS checks system memory and reports it on both the initial AMIBIOS screen and the AMIBIOS System Configuration screen which appears after POST is completed. AMIBIOS attempts to initialize the peripheral devices and if it detects a fault, the screen displays the error condition(s) which has/have been detected. If no errors are detected, AMIBIOS attempts to load the system from a bootable device, such as a floppy disk or hard disk. Boot order may be specified by the Boot Device Priority option on the Boot Setup Menu as described in the Boot Setup chapter later in this manual.

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Normally, the only POST routine visible on the screen is the memory test. The following screen displays when the system is powered on:

Press DEL to run Setup

Initial Power-On Screen

You have two options:

• Press <Del> to access the BIOS Setup Utility.

This option allows you to change various system parameters such as date and time, disk drives, etc. The Running AMIBIOS Setup section of this manual describes the options available.

You may be requested to enter a password before gaining access to the BIOS Setup Utility. (See Password Entry later in this section.)

If you enter the correct password or no password is required, the BIOS Setup Utility Main Menu displays. (See Running AMIBIOS Setup later in this section.)

• Allow the bootup process to continue without invoking the BIOS Setup Utility.

In this case, after AMIBIOS loads the system, you may be requested to enter a password. (See Password Entry later in this section.)

Once the POST routines complete successfully, a screen displays showing the current configuration of your system, including processor type, base and extended memory amounts, floppy and hard drive types, display type and peripheral ports.

Password Entry

The system may be configured so that the user is required to enter a password each time the system boots or whenever an attempt is made to enter the BIOS Setup Utility. The password function may also be disabled so that the password prompt does not appear under any circumstances.

The Password Check option in the Security Menu allows you to specify when the password prompt displays: Always or only when Setup is attempted. This option is available only if the supervisor and/or user password(s) have been established. The supervisor and user passwords may be changed using the Change Supervisor Password and Change User Password options on the Security Menu. If the passwords are null, the password prompt does not display at any time. See the Security Setup section of this chapter for details on setting up passwords.

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When password checking is enabled, the following password prompt displays:

Enter CURRENT Password:

Type the password and press <Enter>. _______________________________________________________________________

NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted. In this case, the password prompt does not display. To set up passwords, you may use the Change Supervisor Password and Change User Password options on the Security Menu of the BIOS Setup Utility. (See the Security Setup section later in this chapter.)

_______________________________________________________________________

If an incorrect password is entered, the following screen displays:

Enter CURRENT Password: X Enter CURRENT Password:

You may try again to enter the correct password. If you enter the password incorrectly three times, the system responds in one of two different ways, depending on the value specified in the Password Check option on the Security Menu:

1) If the Password Check option is set to Setup, the system does not let you enter Setup, but does continue the booting process. You must reboot the system manually to retry entering the password.

2) If the Password Check option is set to Always, the system locks and you must reboot. After rebooting, you will be requested to enter the password.

Once the password has been entered correctly, you are allowed to continue.

BIOS Errors

If an error is encountered during the diagnostic checks performed when the system is powered on, the error is reported in one of two different ways:

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1) If the error occurs before the display device is initialized, a series of beeps is transmitted.

2) If the error occurs after the display device is initialized, the screen displays the error message. In the case of a non-fatal error, a prompt to press the <F1> key may also appear on the screen.

Explanations of the beep codes and BIOS error messages may be found in Appendix A - BIOS Messages.

As the POST routines are performed, test codes are presented on Port 80H. These codes may be helpful as a diagnostic tool and are listed in Appendix A - BIOS Messages.

If certain non-fatal error conditions occur, you are requested to run the BIOS Setup Utility. The error messages are followed by this screen:

Press F1 to Run SETUP Press F2 to load default values and continue

Press <F1>. You may be requested to enter a password before gaining access to the BIOS Setup Utility. (See Password Entry earlier in this section.)

If you enter the correct password or no password is required, the BIOS Setup Utility Main Menu displays.

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RUNNING AMIBIOS SETUP

AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives, display type and other user-defined parameters. The Setup parameters reside in the Read Only Memory Basic Input/Output System (ROM BIOS) so that they are available each time the system is turned on. The BIOS Setup Utility stores the information in the complementary metal oxide semiconductor (CMOS) memory. When the system is turned off, a backup battery retains system parameters in the CMOS memory.

Each time the system is powered on, it is configured with these values, unless the CMOS has been corrupted or is faulty. The BIOS Setup Utility is resident in the ROM BIOS so that it is available each time the computer is turned on. If, for some reason, the CMOS becomes corrupted, the system is configured with the default values stored in this ROM file.

As soon as the system is turned on, the power-on diagnostic routines check memory, attempt to prepare peripheral devices for action, and offer you the option of pressing <Del> to run the BIOS Setup Utility.

If certain non-fatal errors occur during the Power-On Self Test (POST) routines which are run when the system is turned on, you may be prompted to run the BIOS Setup Utility by pressing <F1>.

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BIOS SETUP UTILITY MAIN MENU

When you press <F1> in response to an error message received during the POST routines or when you press the <Del> key to enter the BIOS Setup Utility, the following screen displays:

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Boot Security Exit

AMIBIOS Version : 07.00.xx BIOS Build Date : 11/05/01 BIOS ID : 0AAXX017

Processor Type : Pentium III(tm) Processor Speed : 866MHz

System Memory : 256MB

System Time [10:22:35] System Date [Mon 01/01/1990]

←→ Select Screen ↑↓ Select Item

+- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit

BIOS SETUP UTILITY MAIN MENU OPTIONS

BIOS Setup Utility Main Menu

When you display the BIOS Setup Utility Main Menu, the format is similar to the sample shown above. The data displayed on the top portion of the screen details parameters detected by AMIBIOS for your processor board and may not be modified. The system time and date displayed on the bottom portion of the screen may be modified.

The descriptions for the system options listed below show the values as they appear if you have not changed them yet. Once values have been defined, they display each time the BIOS Setup Utility is run.

System Time/System Date

These options allow you to set the correct system time and date. If you do not set these parameters the first time you enter the BIOS Setup Utility, you will receive a "Run SETUP" error message when you boot the system until you set the correct parameters.

The Setup screen displays the system options:

System Time [10:22:35] System Date [Mon 01/01/1990]

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There are three fields for entering the time or date. Use the <Tab> key or the <Enter> key to move from one field to another and type in the correct value for the field.

If you enter an invalid value in any field, the screen will revert to the previous value when you move to the next field. When you change the value for the month, day or year field, the day of the week changes automatically when you move to the next field.

BIOS SETUP UTILITY OPTIONS

The BIOS Setup Utility allows you to change system parameters to tailor your system to your requirements. Various options which may be changed are listed below. Further explanations of these options and available values may be found in later chapters of this manual, as noted below. _______________________________________________________________________

NOTE: Do not change the values for any option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________

Use the Right Arrow key to display the desired menu. The following menus are available:

• Select Advanced to make changes to Advanced Setup parameters as described in the Advanced Setup chapter of this manual. The following options may be modified:

• SuperIO Configuration

• OnBoard Floppy Controller

• Serial Port1 Address/Serial Port2 Address

• Parallel Port Address

• Parallel Port Mode

• Parallel Port IRQ

• IDE Configuration

• OnBoard PCI IDE Controller

• Primary IDE Master/Primary IDE Slave

Secondary IDE Master/Secondary IDE Slave

• Ty pe

• LBA/Large Mode

• Block (Multi-Sector Transfer)

• PIO Mode

• DMA Mode

• S.M.A.R.T.

• 32Bit Data Transfer

• ARMD Emulation Type

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• Hard Disk Write Protect

• ATA(PI) Detect Time Out (Sec)

• Floppy Configuration

• Floppy A/Floppy B

• Diskette Write Protect

• Floppy Drive Seek

• Boot Settings Configuration

• Quick Boot

• Quiet Boot

• AddOn ROM Display Mode

• Bootup Num-Lock

• Bootup CPU Speed

• PS/2 Mouse Support

• Typematic Rate

• System Keyboard

• Primary Display

• Parity Check

• Boot To OS/2

• Wait For ‘F1’ If Error

• Hit ‘DEL’ Message Display

• Internal Cache

• System BIOS Cacheable

• Event Log Configuration

• Event Logging

• ECC Event Logging

• Clear All Event Logs

• Vi ew Event L og

• Mark All Events as Read

• Remote Access Configuration

• Remote Access

• Serial Port Number

• Serial Port Mode

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• Select Chipset to make changes to Chipset Setup parameters as described in the Chipset Setup chapter of this manual. The following options may be modified:

• Video and Adapter ROM Shadow

• Memory Scrubbing

• Memory Timing Control

• Act to Deact

• Act to Read/Write

• RAS Precharge Time

• RAS Cycle Time

• Write to Deact

• SDRAM CAS Latency

• ISA IO Cycle Delay

• Allow Cards to Trap Int19

• Memory Hole

• Select PCIPnP to make changes to PCI Plug and Play Setup parameters as

described in the PCI Plug and Play Setup chapter of this manual. The following options may be modified:

• OnBoard LAN1

• OnBoard LAN2

• OnBoard VGA

• OnBoard SCSI

• Plug & Play O/S

• Reset Config Data

• PCI Latency Timer

• Allocate IRQ to PCI VGA

• Palette Snooping

• PCI IDE BusMaster

• OffBoard PCI/ISA IDE Card

• OffBoard PCI IDE Primary IRQ

• OffBoard PCI IDE Secondary

• USB Function

• Legacy USB Support

• IRQs 3, 4, 5, 7, 9, 10, 11, 14 and 15

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• DMA Channels 0, 1, 3 5, 6 and 7

• Reserved Memory Size

• Reserved Memory Address

• Select Boot to make changes to Boot Setup parameters as described in the

Boot Setup chapter of this manual. The following options may be modified:

• Boot Device Priority

• Hard Disk Drives

• Removable Devices

• ATAPI CDROM Drives

• Select Security to establish or change the supervisor or user password or to

enable boot sector virus protection. These functions are described later in this chapter. The following options may be modified:

• Change Supervisor Password

• User Access Level

• Password Check

• Change User Password

• Unattended Start

• Password Check

• Clear User Password

• Boot Sector Virus Protection

• Select Exit to save or discard changes you have made to AMIBIOS param-

eters or to load the Optimal or Failsafe default settings. These functions are described later in this chapter. The following options are available:

• Exit Saving Changes

• Exit Discarding Changes

• Load Optimal Defaults

• Load Failsafe Defaults

• Discard Changes

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SECURITY SETUP When you select Security from the BIOS Setup Utility Main Menu, the following Setup

screen displays:

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Boot |Security| Exit

Supervisor Password : Not Installed User Password : Not Installed

> Change Supervisor Password > Change User Password > Clear User Password Boot Sector Virus Protection [Disabled]

←→ Select Screen ↑↓ Select Item

Enter Change F1 General Help F10 Save and Exit ESC Exit

ECURITY SETUP

OPTIONS

HANGE

SUPERVISOR PASSWORD

Security Setup Screen

When you display the Security Setup screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter>. _______________________________________________________________________

NOTE: The values on this screen do not necessarily reflect the values appropriate for your SBC. Refer to the explanations below for specific instructions about entering correct information. _______________________________________________________________________

The Security Setup options allow you to establish, change or clear the supervisor or user password and to enable boot sector virus protection.

This option allows you to establish a supervisor password, change the current password or disable the password prompt by entering a null password. The password is stored in CMOS RAM.

If you have signed on under the user password, this option is not available.

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The Change Supervisor Password feature can be configured so that a password must be entered each time the system boots or just when a user attempts to enter the BIOS Setup Utility. _______________________________________________________________________

NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted. In this case, the "Enter CURRENT Password" prompt is bypassed when you boot the system, and you must establish a new password. _______________________________________________________________________

If you select the Change Supervisor Password option, the following window displays:

Enter New Password

This is the message which displays before you have established a password, or if the last password entered was the null password. If a password has already been established, you are asked to enter the current password before being prompted to enter the new password.

Type the new password and press <Enter>. The password cannot exceed six (6) characters in length. The screen displays an asterisk (*) for each character you type.

After you have entered the new password, the following window displays:

Confirm New Password

Re-key the new password as described above.

If the password confirmation is miskeyed, AMIBIOS Setup displays the following message:

Passwords do not match!

[Ok]

No retries are permitted; you must restart the procedure.

If the password confirmation is entered correctly, the following message displays:

Password installed.

[Ok]

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Press the <Enter> key to return to the Security screen. Installed displays on the screen next to the Supervisor Password option, indicating the password has been accepted. This setting will remain in effect until the supervisor password is either disabled or discarded upon exiting the BIOS Setup Utility.

If you have created a new password, be sure to select Exit, then Exit Saving Changes to save the password. The password is then stored in CMOS RAM. The next time the system boots, you are prompted for the password. _______________________________________________________________________

NOTE: Be sure to keep a record of the new password each time it is changed. If you forget it, use the Password Clear jumper to reset it to the default (null password). See the Specifications chapter of this manual for details. _______________________________________________________________________

If a password has been established, the following options and their default values are added to the screen:

User Access Level [Full] Password Check [Setup]

User Access Level

This option allows you to define the level of access the user will have to the system.

The Setup screen displays the system option:

User Access Level [Full]

Four options are available:

• Select No Access to prevent user access to the BIOS Setup Utility.

• Select View Only to allow access to the BIOS Setup Utility for viewing, but

to prevent the user from changing any of the fields.

• Select Limited to allow the user to change only a limited number of options, such as Date and Time.

• Select Full to allow the user full access to change any option in the BIOS Setup Utility.

Password Check

This option determines when a password is required for access to the system.

The Setup screen displays the system option:

Password Check [Setup]

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Two options are available:

• Select Setup to have the password prompt appear only when an attempt is made to enter the BIOS Setup Utility program.

• Select Always to have the password prompt appear each time the system is powered on.

ISABLING THE

SUPERVISOR PASSWORD

HANGE USER

PASSWORD

To disable password checking so that the password prompt does not appear, you may create a null password by selecting the Change Supervisor Password function and pressing <Enter> without typing in a new password. You will be asked to enter the current password before being allowed to enter the null password. After you press <Enter> at the Enter New Password prompt, the following message displays:

Password uninstalled.

[Ok]

The Change User Password option is similar in functionality to the Change Supervisor Password and displays the same messages. If you have signed on under the user

password, the Change Supervisor Password function is not available for modification.

If a user password has been established, the following options and their default values are added to the screen:

Unattended Start [Disabled] Password Check [Setup]

Unattended Start

This option specifies whether or not the system should complete the bootup process without requiring a password.

The Setup screen displays the system option:

Unattended Start [Disabled]

Two options are available:

• Select Disabled to prevent the system from booting without a password. The keyboard remains locked until a password is entered. A password is required to boot from a diskette.

• Select Enabled to allow the system to complete the bootup process without a password.

Password Check

This option determines when a password is required for access to the system.

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For details, refer to the description for Password Check under the Change Supervisor Password heading earlier in this section.

CLEAR USER PASSWORD

BOOT SECTOR VIRUS PROTECTION

This option allows you to clear the user password. It disables the user password by entering a null password.

If you select the Clear User Password option, the following window displays:

Clear User Password?

[Ok] [Cancel]

You have two options:

• Select Ok to clear the user password.

• Select Cancel to leave the current user password in effect.

This option allows you to request AMIBIOS to issue a warning when any program or virus issues a Disk Format command or attempts to write to the boot sector of the hard disk drive.

The Setup screen displays the system option:

Boot Sector Virus Protection [Disabled]

Available options are:

Disabled Enabled

_______________________________________________________________________

NOTE: You should not enable boot sector virus protection when formatting a hard drive. _______________________________________________________________________

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EXIT MENU When you select Exit from the BIOS Setup Utility Main Menu, the following screen

displays:

BIOS SETUP UTILITY

Main Advanced Chipset PCIPnP Boot Security |Exit|

> Exit Saving Changes > Exit Discarding Changes > Load Optimal Defaults > Load Failsafe Defaults > Discard Changes

Exit system setup saving the changes.

←→ Select Screen ↑↓ Select Item

Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

Exit Menu Screen

When you display the Exit Menu screen, the format is similar to the sample shown above. Highlight the option you wish to select and press <Enter>.

EXIT MENU OPTIONS

When you are running the BIOS Setup Utility program, you may either save or discard changes you have made to AMIBIOS parameters, or you may load the Optimal or Failsafe default settings.

Exit Saving Changes

The features selected and configured in the Setup screens are stored in the CMOS when this option is selected. The CMOS checksum is calculated and written to the CMOS. Control is then passed back to the AMIBIOS and the booting process continues, using the new CMOS values.

If you select the Exit Saving Changes option, the following window displays:

Save configuration changes and exit now?

[Ok] [Cancel]

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You have two options:

• Select Ok to save the system parameters and continue with the booting process.

• Select Cancel to return to the BIOS Setup Utility screen.

Exit Discarding Changes

When the Exit Discarding Changes option is selected, the BIOS Setup Utility exits

without saving the changes in the CMOS. Control is then passed back to AMIBIOS and the booting process continues, using the previous CMOS values.

If you select the Exit Discarding Changes option, the following window displays:

Discard changes and exit setup now?

[Ok] [Cancel]

You have two options:

• Select Ok to continue the booting process without writing any changes to the CMOS.

• Select Cancel to return to the BIOS Setup Utility screen.

Load Optimal or Failsafe Defaults

Each AMIBIOS Setup option has two default settings (Optimal and Failsafe). These settings can be applied to all AMIBIOS Setup options when you select the appropriate configuration option from the BIOS Setup Utility Main Menu.

You can use these configuration options to quickly set the system configuration parameters which should provide the best performance characteristics, or you can select a group of settings which have a better chance of working when the system is having configuration-related problems.

Load Optimal Defaults

This option allows you to load the Optimal default settings. These settings are best-case values which should provide the best performance characteristics. If CMOS RAM is corrupted, the Optimal settings are loaded automatically.

If you select the Load Optimal Defaults option, the following window displays:

Load Optimal Defaults?

[Ok] [Cancel]

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You have two options:

• Select Ok to load the Optimal default settings.

• Select Cancel to leave the current values in effect.

Load Failsafe Defaults

This option allows you to load the Failsafe default settings when you cannot boot your computer successfully. These settings are more likely to configure a workable computer. They may not provide optimal performance, but are the most stable settings. You may use this option as a diagnostic aid if your system is behaving erratically. Select the Failsafe settings and then try to diagnose the problem after the computer boots.

If you select the Load Failsafe Defaults option, the following window displays:

Load Failsafe Defaults?

[Ok] [Cancel]

You have two options:

• Select Ok to load the Failsafe default settings.

• Select Cancel to leave the current values in effect.

Discard Changes

When the Discard Changes option is selected, the BIOS Setup Utility resets any parameters you have changed back to the values at which they were set when you entered the Setup Utility. Control is then passed back to the BIOS Setup Utility screen.

If you select the Discard Changes option, the following window displays:

Discard Changes?

[Ok] [Cancel]

You have two options:

• Select Ok to reset any parameters you have changed back to the values at which they were set when you entered the BIOS Setup Utility. This option then returns you to the BIOS Setup Utility screen.

• Select Cancel to return to the BIOS Setup Utility screen without discarding any changes you have made.

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Chapter 4 Advanced Setup

ADVANCED SETUP When you select Advanced from the BIOS Setup Utility Main Menu, the following

Setup screen displays:

BIOS SETUP UTILITY

Main |Advanced| Chipset PCIPnP Boot Security Exit

Setup Warning Setting items on this screen to incorrect values may cause the system to malfunction!

> SuperIO Configuration > IDE Configuration > Floppy Configuration > Boot Settings Configuration > Event Log Configuration > Remote Access Configuration

Configure SuperIO Chipset Smc78X

←→ Select Screen ↑↓ Select Item

Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

Advanced Setup Screen

When you display the Advanced Setup screen, the format is similar to the sample shown above, allowing you to continue to subscreens designed to change parameters for each of the Advanced Setup options. Highlight the option you wish to change and press <Enter> to proceed to the appropriate subscreen. _______________________________________________________________________

NOTE: The values on the Advanced Setup subscreens do not necessarily reflect the values appropriate for your SBC. Refer to the explanations following each screen for specific instructions about entering correct information. _______________________________________________________________________

DVANCED SETUP

OPTIONS

_______________________________________________________________________

NOTE:Do not change the values for any Advanced Setup option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________

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SuperIO Configuration

The options on the SuperIO Configuration subscreen allow you to set up or modify parameters for your on-board peripherals. The following options may be modified:

• OnBoard Floppy Controller

• Serial Port1 Address/Serial Port2 Address

• Parallel Port Address

• Parallel Port Mode

• Parallel Port IRQ

IDE Configuration

The options on the IDE Configuration subscreens allow you to set up or modify parameters for your IDE controller and hard disk drive(s). The following options may be modified:

• OnBoard PCI IDE Controller

• Primary IDE Master/Primary IDE Slave

• Ty pe

• LBA/Large Mode

• Block (Multi-Sector Transfer)

• PIO Mode

• DMA Mode

• S.M.A.R.T.

• 32Bit Data Transfer

• ARMD Emulation Type

• Secondary IDE Master/Secondary IDE Slave

• (see options above)

• Hard Disk Write Protect

• ATA(PI) Detect Time Out (Sec)

Floppy Configuration

The options on the Floppy Configuration subscreen allow you to set up or modify parameters for your floppy disk drive(s). The following options may be modified:

• Floppy A/Floppy B

• Diskette Write Protect

• Floppy Drive Seek

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Boot Settings Configuration

The options on the Boot Settings Configuration subscreen allow you to set up or modify parameters for boot procedures. The following options may be modified:

• Quick Boot

• Quiet Boot

• AddOn ROM Display Mode

• Bootup Num-Lock

• Bootup CPU Speed

• PS/2 Mouse Support

• Typematic Rate

• System Keyboard

• Primary Display

• Parity Check

• Boot To OS/2

• Wait For ‘F1’ If Error

• Hit ‘DEL’ Message Display

• Internal Cache

• System BIOS Cacheable

Event Log Configuration

The options on the Event Log Configuration subscreen allow you to set up or modify parameters for using the event log, which allows you to log errors and other events which occur in the system. The following options may be modified:

• Event Logging

• ECC Event Logging

• Clear All Event Logs

Remote Access Configuration

The options on the Remote Access Configuration subscreen allow you to set up or modify parameters for configuring remote access type and parameters. The following options may be modified:

• Remote Access

• Serial Port Number

• Serial Port Mode

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Saving and Exiting

When you have made all desired changes to Advanced Setup, you may make changes to other Setup options by using the right and left arrow keys to access other menus. When you have made all of your changes, you may save them by selecting the Exit menu, or you may press <Esc> at any time to exit the BIOS Setup Utility without saving the changes.

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SUPERIO CONFIGURATION

When you select SuperIO Configuration from the Advanced Setup Menu, the following Setup screen displays:

SuperIO Chipset Smc78X

|Advanced|

Configure Smc78X Serial Ports and Parallel Port _______________________________________________

OnBoard Floppy Controller [Enabled] Serial Port1 Address [3F8/IRQ4] Serial Port2 Address [2F8/IRQ3] Parallel Port Address [378]

Parallel Port Mode [Normal] Parallel Port IRQ [7]

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

SUPERIO CONFIGURATION OPTIONS

SuperIO Configuration Screen

When you display the SuperIO Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

The descriptions for the system options listed below show the values as they appear if you have not run the BIOS Setup Utility program yet. Once values have been defined, they display each time the BIOS Setup Utility is run.

OnBoard Floppy Controller

The on-board floppy drive controller may be enabled or disabled using this option.

The Setup screen displays the system option:

OnBoard Floppy Controller [Enabled]

Available options are:

Disabled Enabled

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Serial Port1 Address/Serial Port2 Address

Each of these options enables the specified serial port on the SBC and establishes the base I/O address and the number of the interrupt request for the port.

The Setup screen displays the system option:

Serial Port1 Address [3F8/IRQ4] Serial Port2 Address [2F8/IRQ3]

Available options are:

Disabled 3F8/IRQ4 3E8/IRQ4 2F8/IRQ3 2E8/IRQ3

_______________________________________________________________________

NOTE: The values available for each on-board serial port may vary, depending on the setting previously selected for the other on-board serial port and any off-board serial ports. If an I/O address is assigned to another serial port, AMIBIOS automatically omits that address from the values available. _______________________________________________________________________

If the system has off-board serial ports which are configured to specific starting I/O ports via jumper settings, AMIBIOS configures the on-board serial ports to avoid conflicts.

AMIBIOS checks the ISA Bus for serial ports. Any off-board serial ports found on the ISA Bus are left at their assigned addresses. Serial Port1, the first on-board serial port, is configured with the first available address and Serial Port2, the second on-board serial port, is configured with the next available address. The default address assignment order is 3F8H, 2F8H, 3E8H, 2E8H. Note that this same assignment order is used by AMIBIOS to place the active serial port addresses in lower memory (BIOS data area) for configuration as logical COM devices.

For example, if there is one off-board serial port on the ISA Bus and its address is set to 2F8H, Serial Port1 is assigned address 3F8H and Serial Port2 is assigned address 3E8H. Configuration is then as follows:

COM1 - Serial Port1 (at 3F8H) COM2 - off-board serial port (at 2F8H) COM3 - Serial Port2 (at 3E8H)

Parallel Port Address

This option enables the parallel port on the SBC and establishes the base I/O address for the port.

The Setup screen displays the system option:

Parallel Port Address [378]

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Available options are:

Disabled 378 278 3BC

AMIBIOS checks the ISA Bus for off-board parallel ports. Any parallel ports found on the ISA Bus are left at their assigned addresses. The on-board Parallel Port is automatically configured with the first available address not used by an off-board parallel port.

Parallel Port Mode

This option specifies the parallel port mode. ECP and EPP are both bidirectional data transfer schemes which adhere to the IEEE P1284 specifications.

The Setup screen displays the system option:

Parallel Port Mode [Normal]

Three options are available:

• Select Normal to use normal parallel port mode.

• Select EPP to allow the parallel port to be used with devices which adhere

to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data transfer driven by the host device.

• Select ECP to allow the parallel port to be used with devices which adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve transfer rates of approximately 2.5MB/second. ECP provides symmetric bidirectional communication.

Parallel Port IRQ

This option specifies the interrupt request (IRQ) which is used by the parallel port.

The Setup screen displays the system option:

Parallel Port IRQ [7]

Available options are:

5 7

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IDE CONFIGURATION

When you select IDE Configuration from the Advanced Setup Menu, the following Setup screen displays:

BIOS SETUP UTILITY

|Advanced|

IDE Configuration _____________________________________________

OnBoard PCI IDE Controller [Both]

> Primary IDE Master [Hard Disk] > Primary IDE Slave [ATAPI CDROM] > Secondary IDE Master [Not Detected] > Secondary IDE Slave [Not Detected]

Hard Disk Write Protect [Disabled] ATA(PI) Detect Time Out (Sec) [3.5x]

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

IDE C

ONFIGURATION

OPTIONS

IDE Configuration Screen

When you display the IDE Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

Some of the options on this screen allow you to continue to subscreens designed to change parameters for that particular option. Highlight the option you wish to change and press <Enter> to proceed to the appropriate subscreen.

OnBoard PCI IDE Controller

This option specifies whether or not the on-board integrated drive electronics (IDE) controllers are to be used.

The Setup screen displays the system option:

OnBoard PCI IDE Controller [Both]

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Available options are:

Disabled Both

Primary IDE Master/Primary IDE Slave Secondary IDE Master/Secondary IDE Slave

The SBC has an enhanced IDE (EIDE) interface which can support up to four IDE disk drives through a primary and secondary controller in a master/slave configuration. This EIDE interface allows disk drives greater than 528MB to be used. Each of the four drives may be a different type.

Devices attached to the primary and secondary controllers are detected automatically by AMIBIOS and displayed on the IDE Configuration screen.

The Setup screen displays the system options:

Primary IDE Master [Hard Disk] Primary IDE Slave [ATAPI CDROM]

Secondary IDE Master [Not Detected] Secondary IDE Slave [Not Detected]

To view and/or change parameters for any IDE device, press <Enter> to proceed to the IDE Device Setup screen, which is described later in this section.

Hard Disk Write Protect

This option allows you to disable or enable device write protection. Write protection will be effective only if the device is accessed through the BIOS.

The Setup screen displays the system option:

Hard Disk Write Protect [Disabled]

Available options are:

Disabled Enabled

ATA(PI) Detect Time Out (Sec)

This option allows you to select the time-out value (in seconds) for detecting an ATA/ ATAPI device.

The Setup screen displays the system option:

ATA(PI) Detect Time Out (Sec) [3.5x]

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Available options are:

0 5 10 15

2.0x

2.5x

3.0x

3.5x

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IDE DEVICE SETUP When you select one of the IDE devices from the IDE Configuration screen, a Setup

screen similar to the following displays:

BIOS SETUP UTILITY

|Advanced|

Primary IDE Master _____________________________________________ Device : Hard Disk Vendor : ST33210A Size : 3.2GB LBA Mode : Supported Block Mode: 16Sectors PIO Mode : 4 Async DMA : MultiWord DMA-2 Ultra DMA : Ultra DMA-2 S.M.A.R.T.: Supported _____________________________________________ Type [Auto} LBA/Large Mode [Auto] Block (Multi-Sector Transfer) [Auto] PIO Mode [Auto] DMA Mode [Auto] S.M.A.R.T. [Auto] 32Bit Data Transfer [Disabled] ARMD Emulation Type [Auto]

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

IDE DEVICE SETUP OPTIONS

IDE Device Screen

When you display the IDE Device subscreen, the format is similar to the sample shown above. The data displayed on the top portion of the screen details the parameters detected by AMIBIOS for the specified device and may not be modified. The data displayed on the bottom portion of the screen may be modified.

The drive information which displays the first time the BIOS Setup Utility is run indicates the drive(s) on your system which AMIBIOS detected upon initial bootup.

The following options are available for each of the four IDE devices on the primary and secondary IDE controllers:

Type

This option allows you to specify what type of device is on the IDE controller.

The Setup screen displays the system option:

Type [Auto]

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Available options are:

Auto Not Installed CDROM ARMD

If Not Installed is selected, the other options on the bottom portion of this screen do not display. If CDROM is selected, the ARMD Emulation Type option is not available.

LBA/Large Mode

This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the specified IDE drive. Data is accessed by block addresses rather than by the traditional cylinder-head-sector format. This allows you to use drives larger than 528MB.

The Setup screen displays the system option:

LBA/Large Mode [Auto]

Two options are available:

• Select Auto to enable LBA mode and translate the physical parameters of the drive to logical parameters. LBA Mode must be supported by the drive and the drive must have been formatted with LBA Mode enabled.

• Select Disabled to have AMIBIOS use the physical parameters of the hard disk and do no translation to logical parameters. The operating system which uses the parameter table will then see only 528MB of hard disk space even if the drive contains more than 528MB.

Block (Multi-Sector Transfer) Mode

This option supports transfer of multiple sectors to and from the specified IDE drive. Block mode boosts IDE drive performance by increasing the amount of data transferred during an interrupt.

If Block Mode is set to Disabled, data transfers to and from the device occur one sector at a time.

The Setup screen displays the system option:

Block (Multi-Sector Transfer) [Auto]

Available options are:

Disabled Auto

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PIO Mode

IDE Programmed I/O (PIO) Mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode increases, the cycle time decreases.

Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the IDE drive being configured. If you select a specific value for the PIO mode, you must make absolutely certain that you are selecting the PIO mode supported by the IDE drive being configured.

The Setup screen displays the system option:

PIO Mode [Auto]

Available options are:

Auto 0 1 2 3 4

DMA Mode

This option allows you to select DMA Mode for the device.

The Setup screen displays the system option:

DMA Mode [Auto]

Available options are:

Auto SWDMA0 (SingleWord DMA 0 - 2) SWDMA1 SWDMA2 MWDMA0 (MultiWord DMA 0 - 2) MWDMA1 MWDMA2 UDMA0 (UltraDMA 0 - 4) UDMA1 UDMA2 UDMA3 UDMA4

S.M.A.R.T.

This option allows AMIBIOS to use the SMART (Self-Monitoring Analysis and Reporting Technology) protocol for reporting server system information over a network.

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The Setup screen displays the system option:

S.M.A.R.T. [Auto]

Available options are:

Auto Disabled Enabled

32Bit Data Transfer

Hard disk drives connected to the SBC via the ISA Bus transfer data 16 bits at a time. An IDE drive on the PCI Local Bus can use a 32-bit data path.

If the 32Bit Data Transfer parameter is set to Enabled, AMIBIOS enables 32-bit data transfers. If the host controller does not support 32-bit transfer, this feature must be set to Disabled.

The Setup screen displays the system option:

32Bit Data Transfer [Disabled]

Available options are:

Disabled Enabled

ARMD Emulation Type

This option specifies the type of ARMD (ATAPI Removable Media Device) emulation used for a non-disk device attached to the specified IDE device.

If the option is set to Auto, AMIBIOS automatically determines the proper emulation type and will support particular storage devices with ATAPI interface.

If CDROM is selected in the Typ e field, this option is not available for modification.

The Setup screen displays the system options:

ARMD Emulation Type [Auto]

Available options are:

Auto Floppy Hard Disk

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FLOPPY CONFIGURATION

When you select Floppy Configuration from the Advanced Setup Menu, the following Setup screen displays:

BIOS SETUP UTILITY

|Advanced|

Floppy Configuration _____________________________________________

Floppy A [1.44 MB 3-1/2”] Floppy B [Disabled]

Diskette Write Protect [Disabled] Floppy Drive Seek [Disabled]

Select the floppy drive type.

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

FLOPPY CONFIGURATION OPTIONS

Floppy Configuration Screen

When you display the Floppy Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

The drive information which displays the first time the BIOS Setup Utility is run indicates the drive(s) on your system which AMIBIOS detected upon initial bootup.

Floppy A/Floppy B

The floppy drive(s) in your system can be configured using these options. The Disabled option can be used for diskless workstations.

The Setup screen displays the system options:

Floppy A [1.44 MB 3-1/2"] Floppy B [Disabled]

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Available options are:

Disabled 360 KB 5-1/4"

1.2 MB 5-1/4" 720 KB 3-1/2"

1.44MB 3-1/2"

2.88MB 3-1/2"

Diskette Write Protect

This option allows you to disable or enable device write protection. Write protection will be effective only if the device is accessed through the BIOS.

The Setup screen displays the system option:

Diskette Write Protect [Disabled]

Available options are:

Disabled Enabled

Floppy Drive Seek

This option causes the system to have the floppy drive(s) seek during bootup. The default for this option is Disabled to allow a fast boot and to decrease the possibility of damage to the heads.

The Setup screen displays the system option:

Floppy Drive Seek [Disabled]

Available options are:

Disabled Enabled

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BOOT SETTINGS CONFIGURATION

When you select Boot Settings Configuration from the Advanced Setup Menu, the following Setup screen displays:

BIOS SETUP UTILITY

|Advanced|

Boot Settings Configuration _____________________________________________

Quick Boot [Disabled] Quiet Boot [Disabled] AddOn ROM Display Mode [Force BIOS] _____________________________________________

BootUp Num-Lock [On] BootUp CPU Speed [High] PS/2 Mouse Support [Enabled] Typematic Rate [Fast] System Keyboard [Present] Primary Display [VGA/EGA] Parity Check [Enabled] Boot To OS/2 [No] Wait For ‘F1’ If Error [Enabled] Hit ‘DEL’ Message Display [Enabled] Internal Cache [Write-Back] System BIOS Cacheable [Enabled]

Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

BOOT SETTINGS CONFIGURATION OPTIONS

Boot Settings Configuration Screen

When you display the Boot Settings Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

Quick Boot

This option allows you to have the AMIBIOS boot quickly when the computer is powered on or go through more complete testing. If you set the Quick Boot option to Enabled, the BIOS skips certain tests while booting and decreases the time needed to boot the system.

The Setup screen displays the system option:

Quick Boot [Disabled]

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Available options are:

Disabled Enabled

Quiet Boot

This option specifies what will be displayed on the screen while the system is performing the POST routines when the computer is powered on or a soft reboot is performed.

The Setup screen displays the system option:

Quiet Boot [Disabled]

Two options are available:

• Select Disabled to display normal POST messages.

• Select Enabled to display the OEM logo instead of the POST messages.

AddOn ROM Display Mode

This option specifies the system display mode which is set at the time the AMIBIOS post routines initialize an optional option ROM.

The Setup screen displays the system option:

AddOn ROM Display Mode [Force BIOS]

Two options are available:

• Select Force BIOS to use the display mode currently being used by AMIBIOS.

• Select Keep Current to use the current display mode.

BootUp Num-Lock

This option enables you to turn off the Num-Lock option on the enhanced keyboard when the system is powered on. If Num-Lock is turned off, the arrow keys on the numeric keypad can be used, as well as the other set of arrow keys on the enhanced keyboard.

The Setup screen displays the system option:

BootUp Num-Lock [On]

Available options are:

Off On

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BootUp CPU Speed

The Setup screen displays the system option:

BootUp CPU Speed [High]

Available options are:

Low High

PS/2 Mouse Support

This option indicates whether or not a PS/2-type mouse is supported.

The Setup screen displays the system option:

PS/2 Mouse Support [Enabled]

Available options are:

Disabled Enabled

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Typematic Rate

The Setup screen displays the system option:

Typematic Rate [Fast]

Available options are:

Slow Fast

System Keyboard

This option indicates whether or not a keyboard is attached to the computer.

The Setup screen displays the system option:

System Keyboard [Present]

Available options are:

Absent Present

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Primary Display

This option specifies the type of display monitor in the system. The Absent option can be used for network file servers.

The Setup screen displays the system option:

Primary Display [VGA/EGA]

Available options are:

Absent VGA/EGA Color 40 x 25 Color 80 x 25 Monochrome

Parity Check

This option allows you to enable parity checking of all system memory.

The Setup screen displays the system option:

Parity Check [Enabled]

Available options are:

Disabled Enabled

Boot To OS/2

This option should be set to Ye s if you are running the IBM OS/2 operating system and using more than 64MB of system memory on the SBC.

The Setup screen displays the system option:

Boot To OS/2 [No]

Available options are:

No Ye s

Wait For ’F1’ If Error

Before the system boots up, the AMIBIOS executes the Power-On Self Test (POST) routines, a series of system diagnostic routines. If any of these tests fail but the system can still function, a non-fatal error has occurred. The AMIBIOS responds with an appropriate error message followed by:

Press F1 to RESUME

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If this option is set to Disabled, a non-fatal error does not generate the "Press F1 to RESUME" message. The AMIBIOS still displays the appropriate message, but continues the booting process without waiting for the <F1> key to be pressed. This eliminates the need for any user response to a non-fatal error condition message. Non-fatal error messages are listed in Appendix A - BIOS Messages.

The Setup screen displays the system option:

Wait For ’F1’ If Error [Enabled]

Available options are:

Disabled Enabled

Hit ’DEL’ Message Display

The "Hit DEL to run Setup" message displays when the system boots up. Disabling this option prevents the message from displaying.

The Setup screen displays the system option:

Hit ’DEL’ Message Display [Enabled]

Available options are:

Disabled Enabled

Internal Cache

This option specifies the caching algorithm used for L1 internal cache memory.

The Setup screen displays the system option:

Internal Cache [Write-Back]

Four options are available:

• Select Disabled to disable both L1 internal cache memory on the SBC and L2 secondary cache memory.

• Select Write-Thru to use the write-through caching algorithm.

• Select Write-Back to use the write-back caching algorithm.

• Select Reserved.

System BIOS Cacheable

The System BIOS, which is in the F000H memory segment, is automatically shadowed to RAM for faster execution. This option indicates that this memory segment can be read from or written to cache memory.

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The Setup screen displays the system option:

System BIOS Cacheable [Enabled]

Available options are:

Disabled Enabled

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EVENT LOG CONFIGURATION

When you select Event Log Configuration from the Advanced Setup Menu, the following Setup screen displays:

BIOS SETUP UTILITY

|Advanced|

Event Log Configuration _____________________________________________

Event Log Area : Space Available Event Log Data : Valid

Event Logging [Enabled] ECC Event Logging [Disabled] Clear All Event Logs [No]

> View Event Log

> Mark All Events As Read

ENABLED: Allow logging of events.

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

EVENT LOG CONFIGURATION OPTIONS

Event Log Configuration Screen

When you display the Event Log Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

Event Logging

This option allows logging of events.

The Setup screen displays the system option:

Event Logging [Enabled]

Available options are:

Disabled Enabled

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ECC Event Logging

This option allows logging of error checking and correction (ECC) events.

The Setup screen displays the system option:

ECC Event Logging [Disabled]

Available options are:

Disabled Enabled

Clear All Event Logs

This option specifies whether or not the event logs should be cleared on the next boot.

The Setup screen displays the system option:

Clear All Event Logs [No]

Available options are:

No Ye s

View Event Log

When you select this option, a window similar to the following displays showing events which have been logged:

View Event Log

Pre-Boot Error:

CMOS Checksum Error

Pre-Boot Error:

CMOS System Options Not Set

Pre-Boot Error:

CMOS Checksum Error

When you have finished viewing the Event Log, press <Esc> to continue.

Mark All Events As Read

After you have reviewed the events in the event log, you may select this option, which allows you to mark all event log entries as having been read.

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The following window displays:

Mark All Event Log Records As Read?

[Ok] [Cancel]

Selecting Ok marks all entries currently in the event log file as having been read. The next time you select the View Event Log option, only the new, unmarked events are displayed.

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REMOTE ACCESS CONFIGURATION

When you select Remote Access Configuration from the Advanced Setup Menu, the following Setup screen displays:

BIOS SETUP UTILITY

|Advanced|

Configure Remote Access Type and Parameters _____________________________________________

Remote Access [Disabled]

Serial Port Number [COM1] Serial Port Mode [115200 8,n,1]

←→ Select Screen ↑↓ Select Item

+- Change Option F1 General Help F10 Save and Exit ESC Exit

REMOTE ACCESS CONFIGURATION OPTIONS

Remote Access Configuration Screen

When you display the Remote Access Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press <Enter> to display the available settings. Select the appropriate setting and press <Enter> again to accept the highlighted value.

Remote Access

This option allows you to use a terminal connected to the serial port of the SBC to control changes to the BIOS settings.

The Setup screen displays the system option:

Remote Access [Disabled]

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Available options are:

Disabled Serial (ANSI)

If this option is set to Disabled, the Serial Port Number and Serial Port Mode options are not available.

Serial Port Number

This option specifies the serial port on which remote access is to be enabled.

If the Remote Access option is set to Disabled, this option is not available.

The Setup screen displays the system option:

Serial Port Number [COM1]

Available options are:

COM1 COM2

Serial Port Mode

This option specifies settings for the serial port on which remote access is enabled. The settings indicate baud rate, eight bits per character, no parity and one stop bit.

If the Remote Access option is set to Disabled, this option is not available.

The Setup screen displays the system option:

Serial Port Mode [115200 8,n,1]

Available options are:

9600 8,n,1 19200 8,n,1 57600 8,n,1 115200 8,n,1

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