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RAN45728
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Trapeze Software Group WT21A, RAN45728, RAN49110, RAN48790, WT21N User Info

WT21
DATA SHEET
Wednesday, 11 November 2009
Version 1.71
Copyright © 2000-2009 Bluegiga Technologies
All rights reserved.
Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegiga’s products are not authorized for use as critical components in life support devices or systems.
The WRAP is a registered trademark of Bluegiga Technologies
The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies. All other trademarks listed herein are owned by their respective owners.
VERSION HISTORY
Version Comment
0.1 First draft
0.2 Block diagram, descriptions added
0.3 Preliminary version
0.4 Fixed ordering codes added captions
0.5
1.0 Electrical characteristic added. Some minor updates.
1.1
1.2 New template
1.3
1.4 Improved dimensions chapter
1.41 Table 5 fixed (pad types)
1.5 Footprint added
1.6 Footprint fixed. Pin number 3 (NC) added.
1.7
Power control and regulation info added. Layout guide updated. Minor updates and fixes.
Function of the regulator enable pin corrected. Some minor updates.
Pinout fixed (GND pins 1 – 3 removed, pin 23 grounded). Layout guide updated.
Recommended PCB land pattern for WT21-N added, power control and regulation updated. Certification information added
1.71 Information about qualified antenna types added
TABLE OF CONTENTS
1 Ordering Information ................................................................................................8
2 Pinout and Terminal Description .................................................................................9
3 Microcontroller, Memory and Baseband Logic.............................................................. 12
3.1 AuriStream CODEC............................................................................................ 12
3.1.1 AuriStream CODEC Requirements .................................................................. 13
3.1.2 AuriStream Hierarchy...................................................................................13
3.2 Memory Managements Unit ................................................................................ 14
3.3 Burst Mode Controller ........................................................................................ 14
3.4 Physical Layer Hardware Engine DSP ................................................................... 14
3.5 WLAN Coexistence ............................................................................................ 15
3.6 Configurable I/O Parallel Ports ............................................................................15
4 Clock Generation ....................................................................................................16
4.1 32kHz External Reference Clock .......................................................................... 16
5 Serial Peripheral Interface (SPI) ............................................................................... 17
5.1 WT21 Serial Peripheral Interface (SPI) ................................................................. 17
5.2 Instruction Cycle...............................................................................................17
5.2.1 Writing to the Device ................................................................................... 17
5.2.2 Reading from the Device ..............................................................................18
5.2.3 Multi-Slave Operation................................................................................... 18
6 Host Interfaces ...................................................................................................... 19
6.1 Host Selection .................................................................................................. 19
6.2 UART Interface ................................................................................................. 19
6.2.1 UART Configuration While Reset is Active ........................................................ 21
7 CSR Serial Peripheral Interface (CSPI)....................................................................... 22
7.1.1 CSPI Read/Write Cycles................................................................................22
7.1.2 CSPI Register Write Cycle ............................................................................. 23
7.1.3 CSPI Register Read Cycle ............................................................................. 23
7.1.4 CSPI Register Burst Write Cycle..................................................................... 23
7.1.5 CSPI Register Read Cycle ............................................................................. 24
7.2 SDIO Interface ................................................................................................. 25
7.2.1 SDIO/CSPI Deep-Sleep Control Schemes ........................................................ 25
7.2.2 Retransmission ........................................................................................... 25
7.2.3 Signaling.................................................................................................... 25
8 Audio Interfaces..................................................................................................... 26
8.1 PCM Interface...................................................................................................26
8.1.1 PCM Interface Master/Slave ..........................................................................26
8.1.2
Long Frame Sync.........................................................................................27
8.1.3 Short Frame Sync........................................................................................28
8.1.4 Multi-Slot Operation.....................................................................................28
8.1.5 GCI Interface .............................................................................................. 29
8.1.6 Slots and Sample Formats ............................................................................ 29
8.1.7 Additional Features ......................................................................................30
8.1.8 PCM Timing Information ............................................................................... 31
8.1.9 PCM_CLK and PCM_SYNC Generation ............................................................. 34
8.1.10 PCM Configuration ....................................................................................34
8.2 Digital Audio Interface (I2S) ............................................................................... 37
9 Power Control and Regulation................................................................................... 40
9.1 Power Control and Regulation ............................................................................. 40
9.2 VREG_ENABLE.................................................................................................. 40
9.3 RST# .............................................................................................................. 40
9.4 Digital Pin States on Reset ................................................................................. 41
10 Bluetooth Radio................................................................................................... 43
10.1 Bluetooth Receiver....................................................................................... 43
10.1.1 RSSI Analogue to Digital Converter ............................................................. 43
10.2 Bluetooth Transmitter .................................................................................. 43
11 Electrical Characteristics ....................................................................................... 44
11.1 Absolute Maximum Ratings ...........................................................................44
11.2 Recommended Operating Conditions ..............................................................44
11.3 Input/Output Terminal Characteristics ............................................................44
11.3.1 Linear Voltage Regulator............................................................................ 44
11.3.2 Digital ..................................................................................................... 45
11.3.3 Reset ...................................................................................................... 45
11.3.4 32 kHz External Reference Clock .................................................................45
11.4 Power Consumption ..................................................................................... 46
12 Physical Dimensions............................................................................................. 47
13 Layout Guidelines ................................................................................................50
13.1 WT21-N .....................................................................................................50
13.2 WT21-A ..................................................................................................... 50
14 Certifications....................................................................................................... 52
14.1 Bluetooth ................................................................................................... 52
14.2 FCC ...........................................................................................................52
14.3 CE............................................................................................................. 53
14.4 Industry Canada (IC) ................................................................................... 53
14.5
Qualified Antenna Types for WT21-N .............................................................. 53
15 Contact Information .............................................................................................54
WT21 Bluetooth® HCI Module
DESCRIPTION
WT21 is intended for Bluetooth applications where a host processor is capable of running the Bluetooth software stack. WT21 only implements the low level Bluetooth Host Controller Interface (HCI) but still offers advantages of a module - easy implementation and certifications.
APPLICATIONS:
• PCs and laptops
• PDAs
• Embedded systems
FEATURES:
• Fully Qualified Bluetooth v2.1 + EDR System
• Piconet and Scatternet Support
• Low Power Consumption
• 1,8V to 3,6V I/O Voltage
• Integrated 1,8V Regulator
• UART to 4 Mbaud
• SDIO (Bluetooth Type A) and
CSPI Host Interfaces
• Deep-Sleep SDIO Operation
• Support for 802.11 Coexistence
• RoHS Compliant
• AuriStream Baseband Codec
Bluegiga Technologies Oy
oduct series
1 Ordering Information
WT21-A-HCI
Fimrware HCI = HCI firmware
HW version
A = Chip antenna, extended
temperature range
N = RF pin, extended temperature
range
Pr
Page 8 of 54
g
p
2 Pinout and Terminal Description
3
4
5
6
7
8
9
10
11
12
13
14
NC
GND
GND
GND
GND
GND
GND
GND
1V8_OUT
VREGIN
VREG_ENA
PIO1
RFTP
GND
GND
PIO2
PIO3
PIO4
PIO5
PIO7
PIO9
GND
16
1718192021222324252627
15
Figure 1: WT21 pin out
32kHz
SDIO_SD_CS#
UART_RTS#
UART_TX
GND
GND
GND
GND
GND
GND
GND
GND
RST#
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_MISO
PCM_IN
PCM_OUT
PCM_CLK
PCM_SYNC
VDD_PADS
SDIO_CMD
SDIO_CLK
UART_CTS#
UART_RX
GND
28
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PIN NUMBER
NC 3 Not in use Leave floatin
RST# 42
PAD TYPE DESCRIPTION
or connect to GND
Input, weak internal pull-
u
Active low reset. Keep low for >5 ms to cause a reset
GND 23 GND GND
Table 1: Terminal Descriptions
Page 9 of 54
POWER SUPPLIES
VREGIN 12 Input for the internal 1,8V regulator
1v8_OUT 11 1,8V regulator output
VREG_ENA 13 Take high to enable internal voltage regulators
GND
VDD_PADS 33 Positive supply for the digital interfaces
PIN NUMBER DESCRIPTION
4-10, 15-16,
28, 43-50
Ground
Table 2: Terminal Descriptions
PIO PORT
PIO[1] 14
PIO[2] 17
PIO[3] 18
PIN NUMBER
PAD TYPE DESCRIPTION
Bi-directional, programmamble
strength internal pull-down/pull-up
Bi-directional, programmamble
strength internal pull-down/pull-up
Bi-directional, programmamble
strength internal pull-down/pull-up
Programmamble input/output line
Programmamble input/output line
Programmamble input/output line
PIO[4] 19
PIO[5] 20
PIO[7] 21
PIO[9] 22
Bi-directional, programmamble
strength internal pull-down/pull-up
Bi-directional, programmamble
strength internal pull-down/pull-up
Bi-directional, programmamble
strength internal pull-down/pull-up
Bi-directional, programmamble
strength internal pull-down/pull-up
Table 3: Terminal Descriptions
Programmamble input/output line
Programmamble input/output line
Programmamble input/output line
Programmamble input/output line
Page 10 of 54
[0]
p
[1]
p
[2]
[3]
,
p
p
p
SPI INTERFACE
PCM_OUT 36
PCM_IN 37
PCM_SYNC 34
PCM_CLK 35
PIN NUMBER
PAD TYPE DESCRIPTION
Output, tri-state, weak
internal pull-down
Input, weak internal pull-
down
Bi-directional, weak
internal pull-down
Bi-directional, weak
internal pull-down
Synchronous data output
Synchronous data input
Synchronous data sync
Synchronous data clock
Table 4: Terminal Descriptions
SDIO/CSPI/UA RT Interfaces
SDIO_DATA CSPI_MISO CSPI data out UART_TX UART data output, active high SDIO_DATA CSPI_INT CSPI data in UART_RTS# UART request to send, active low SDIO_DATA UART_RX UART data input, active high SDIO_DATA
CSPI_CS#
UART_CTS# UART clear to send, active low SDIO_CLK SDIO clock CSPI_CLK CSPI clock
SDIO_SD_CS# 31
SDIO_CMD SDIO data in CSPI_MOSI CSPI data input
PIN NUMBER
25
26
27
29
30
32
PAD TYPE DESCRIPTION
Bi-directional, tri-
state, weak
internal
Bi-directional,
weak internal pull-
Bi-directional,
weak internal pull-
Bi-directional,
weak internal pull-
Bi-directional,
weak internal pull-
Bi-directional,
weak internal pull-
Bi-directional,
weak internal pull-
ull-down
down
down
down
Synchronous data input/output
Synchronous data input/output
ut
Synchronous data input/output
Synchronous data input/output Chip select for CSR Serial Peripheral Interface
SDIO chip select to allow SDIO accessess
active low
ut
ut
Table 5: Terminal Descriptions
SPI INTERFACE
SPI_MOSI 41 Weak internal
SPI_CS# 40
SPI_CLK 39
SPI_MISO 38
PIN NUMBER
PAD TYPE DESCRIPTION
ull-down SPI data input
Bi-directional, weak
internal pull-down
Bi-directional, weak
internal pull-down
Output, tri-state, weak
internal pull-down
Chip select for Serial Peripheral Interface, active low
SPI clock
SPI data output
Table 6: Terminal Descriptions
Page 11 of 54
3 Microcontroller, Memory and Baseband Logic
3.1 AuriStream CODEC
The AuriStream CODEC works on the principle of transmitting the delta between the actual value of the signal and a prediction rather than the signal itself. Hence, the information transmitted is reduced along with the power requirement. The quality of the output depends on the number of bits used to represent the sample.
The inclusion of AuriStream results in reduced power consumption compared to a CVSD implementation when used at both ends of the system.
Page 12 of 54
3.1.1 AuriStream CODEC Requirements
AuriStream supports the following modes of operation:
Table 7: AuriStream Supported Bitrates
Table Key:
= Standard Mode
= Optional Mode
Where possible, AuriStream shares hardware between the encoder and decoder as well as the G726 and G722 implementations of the standard. The 40kbs and 20kbs modes of the G722 codec are specific to CSR.
The AuriStream module will be required to support the 3Mbps stream transmitted by the BT radio. The worst-case scenario arises when the AuriStream block is configured as 16kbps at 8 kHz, which equates to 2 bits per sample, giving a worst-case symbol rate at the input to the AuriStream block of 1.5Msps to sustain the transmitted bit stream.
Figure 2: AuriStream CODEC and the BT Radio
3.1.2 AuriStream Hierarchy
The AuriStream CODEC is positioned in parallel with the CVSD CODEC as shown in Figure 4.
Page 13 of 54
Figure 3: AuriStream CODEC and the CVSD CODEC
The AuriStream CODEC is controlled by the TX_RX_VOICEmain block and the processor. Raw data from the host is read from the MMU by the transmit block. This data is fed via the TX_RX_VOICE_MAIN module to the required CODEC, the encoded data is then fed back to the transmit block for broadcast over the Bluetooth interface. During reception, the data is sourced from the radio and applied to the required CODEC. The decoded data is then stored back to RAM by the bluetooth receiver.
3.2 Memory Managements Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data that is in transit between the host and the air. The dynamic allocation of memory ensures efficient use of the available Random Access Memory(RAM) and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.
3.3 Burst Mode Controller
During transmission the Burst Mode Controller(BMC) constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception.
3.4 Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:
• Forward error correction
• Header error correction
• Cyclic redundancy check
• Encryption
• Data whitening
• Access code correlation
• Audio transcoding
Page 14 of 54
The following voice data translations and operations are performed by firmware:
• A-law/µ-law/linear voice data (from host)
• A-law/µ-law/Continuously variable Slope Delta (CVSD) (over the air)
• Voice interpolation for lost packets
• Rate mismatches
The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR including AFH and eSCO.
3.5 WLAN Coexistence
Dedicated hardware is provided to implement a variety of coexistence schemes. Channel skipping AFH, priority signalling, channel signalling and host passing of channel instructions are all supported. The features are configured in firmware.
For more information contact Buegiga technical support.
3.6 Configurable I/O Parallel Ports
lines of programmable bi-directional input/outputs (I/O) are provided. PIO[1: 5, 7, 9] are powered from VDD_PADS.
PIO lines can be configured through software to have either weak or strong pull-ups or pull­downs. All PIO lines are configured as inputs with weak pull-downs at reset.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes.
Bluegiga cannot guarantee that the PIO assignments remain as described. Refer to the relevant software release note for the implementation of these PIO lines, as they are firmware build­specific.
Page 15 of 54
4 Clock Generation
WT21 uses an internal 26 MHz crystal as a Bluetooth reference clock. All WT21 internal digital clocks are generated using a phase locked loop, which is locked to the 26 MHz reference clock.
Also supplied to the digits is a watchdog clock, for use in low power modes. This uses a frequency of 32.768kHz from CLK_32K, or an internally generated reference clock frequency of 1kHz, determined by PSKEY_DEEP_SLEEP_EXTERNAL_CLOCK_SOURCE.
The use of the watchdog clock is determined with respect to Bluetooth operation in low power modes.
26 MHz
Watchdog clock
CLK_32kHz
AIO[0]
1 kHz
Bluetooth Radio
PLL
Digits
Figure 4: Clock Architecture
4.1 32kHz External Reference Clock
A 32kHz clock can be applied to CLK_32K, using PSKEY_DEEP_SLEEP_EXTERNAL_CLOCK_SOURCE.
The CLK_32K pad is in the VDD_PADS domain with all the other digital I/O pads and is driven between levels specified in Section 11.3.4.
Page 16 of 54
5 Serial Peripheral Interface (SPI)
5.1 WT21 Serial Peripheral Interface (SPI)
SPI is used for debuging primarily. This section details the considerations required when interfacing to WT21 via the SPI.
Data may be written or read one word at a time or the auto increment feature may be used to access blocks.
5.2 Instruction Cycle
WT21 is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 8 shows the instruction cycle for an SPI transaction.
Table 8: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into the WT21 on the rising edge of the clock line SPI_CLK. When reading, WT21 replies to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high.
Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. To overcome this WT21 offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read.
5.2.1 Writing to the Device
To write to WT21, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16­bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to consecutive locations until the transaction terminates when SPI_CS# is taken high.
Page 17 of 54
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